Abstract: Provided is a semiconductor integrated circuit device capable of realizing an analog circuit required to have a high-precision relative ratio between adjacent transistors, which is reduced in size and cost. A single MOS transistor is provided within each of well regions. A plurality of the MOS transistors is combined to serve as an analog circuit block. Since distances between the well regions and channel regions may be made equal to one another, a high-precision semiconductor integrated circuit device can be obtained.

Abstract: An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.

Abstract: The present invention provides a solid-state imaging device in which high S/N is achieved. A solid-state imaging device includes a photodiode, a transfer transistor, a floating diffusion, a floating diffusion wiring, an amplifying transistor, a power line, and first output signal lines, in which the first output signal lines are formed one on each side of the floating diffusion wiring in a layer having the floating diffusion wiring formed on a semiconductor substrate, and the power line is formed above the floating diffusion wiring.

Abstract: There is provided a solid-state image pickup device including a semiconductor substrate, and a plurality of pixel portions that are provided on the semiconductor substrate. Each of the pixel portions includes a photoelectric converting unit that generates a charge on the basis of incident light, a memory unit that accumulates the charge generated by the photoelectric converting unit, a light shielding portion that shields at least the memory unit from light, a digging portion that digs into the semiconductor substrate between the photoelectric converting unit and the memory unit and is formed of a light shielding material, and a transmitting unit that transmits the charge from the photoelectric converting unit to the memory unit, by forming a channel for transmission in the digging portion.

Abstract: There is provided a linear sensor including a plurality of sensor elements that are disposed in line, each including a light sensing part that senses light, generates an electric charge according to an amount of the sensed light, and accumulates the electric charge, a readout gate used to read out the electric charge accumulated in the light sensing part, and a reset gate used to discharge the electric charge accumulated in the light sensing part so as to be reset, wherein a region having a highest concentration of an impurity included in the light sensing part is formed in a position similarly away from the readout gate and the reset gate in the light sensing part.

Abstract: In each of pixels 10 arranged in an array pattern, an insulating isolation part 22 electrically isolates adjacent photoelectric conversion elements 11, and the photoelectric conversion element 11 and an amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. A low concentration first isolation diffusion layer 23 is formed below the insulating isolation part 22 constituting the first region A, and a high concentration second isolation diffusion layer 24 and a low concentration first isolation diffusion layer 23 are formed below the insulating isolation part 22 constituting the second region B. A source/drain region of the amplifier transistor 14 in the second region B is formed in a well region 25 formed simultaneously with the second isolation diffusion layer 24.

Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion units configured to generate signal charge from light received at light-receiving surfaces thereof, the plurality of photoelectric conversion units being provided in the image-sensing area of a substrate; a charge reading unit configured to read signal charge generated by the photoelectric conversion units, a charge readout channel area thereof being provided in the image-sensing area of the substrate; a transfer register unit configured to transfer signal charge read from the plurality of photoelectric conversion units by the charge reading unit, a charge transfer channel area thereof being provided in the image-sensing area of the substrate; and a light-shielding unit that is provided in the image-sensing area of the substrate and that has an opening through which light is transmitted formed in an area corresponding to a light-receiving surface of a respective photoelectric conversion unit.

Abstract: An image sensor pixel includes a photosensitive element having a first doping type disposed in semiconductor material. A deep extension having the first doping type is disposed beneath and overlapping the photosensitive element in the semiconductor material. A floating diffusion is disposed in the semiconductor material. A transfer gate is disposed over a gate oxide that is disposed over the semiconductor material. The transfer gate is disposed between the photosensitive element and the floating diffusion. The photosensitive element and the deep extension are stacked in the semiconductor material in a “U” shape extending from under the transfer gate.

Abstract: A solid state imaging device 1 is provided with a photoelectric conversion portion 2 having a plurality of photosensitive regions 7, and a potential gradient forming portion 3 having an electroconductive member 8 arranged opposite to the photosensitive regions 7. A planar shape of each photosensitive region 7 is a substantially rectangular shape. The photosensitive regions 7 are juxtaposed in a first direction intersecting with the long sides. The potential gradient forming portion 3 forms a potential gradient becoming higher along a second direction from one of the short sides to the other of the short sides of the photosensitive regions 7. The electroconductive member 8 includes a first region 8a extending in the second direction and having a first electric resistivity, and a second region 8b extending in the second direction and having a second electric resistivity smaller than the first electric resistivity.

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract: A solid-state imaging device is provided with a plurality of photoelectric converting portions each having a photosensitive region and an electric potential gradient forming region, and which are juxtaposed so as to be along a direction intersecting with a predetermined direction, a plurality of buffer gate portions each arranged corresponding to a photoelectric converting portion and on the side of the other short side forming a planar shape of the photosensitive region, and accumulates a charge generated in the photosensitive region of the corresponding photoelectric converting portion, and a shift register which acquires charges respectively transferred from the plurality of buffer gate portions, and transfers the charges in the direction intersecting with the predetermined direction, to output the charges. The buffer gate portion has at least two gate electrodes to which predetermined electric potentials are respectively applied so as to increase potential toward the predetermined direction.

Abstract: Highly efficient, low energy, low light level imagers and photodetectors are provided. In particular, a novel class of Della-Doped Electron Bombarded Array (DDEBA) photodetectors that will reduce the size, mass, power, complexity, and cost of conventional imaging systems while improving performance by using a thinned imager that is capable of detecting low-energy electrons, has high gain, and is of low noise.

Abstract: An object of the present invention is to prevent a sensitivity difference between pixels. There are disposed plural unit cells each including plural photodiodes 101A and 101B, plural transfer MOSFETs 102A and 102B arranged corresponding to the plural photodiodes, respectively, and a common MOSFET 104 which amplifies and outputs signals read from the plural photodiodes. Each pair within the unit cell, composed of the photodiode and the transfer MOSFET provided corresponding to the photodiode, has translational symmetry with respect to one another. Within the unit cell, there are included a reset MOSFET and selecting MOSFET.

Abstract: A photoelectric conversion apparatus of the present invention includes: a plurality of photoelectric conversion elements arranged on a substrate; a transistor for transferring a signal charge; and a plurality of transistors for reading out the signal charge transferred. The plurality of photoelectric conversion elements include a first photoelectric conversion element and a second photoelectric conversion element adjacent to each other. The photoelectric conversion apparatus of the present invention includes: a first semiconductor region having a first conductivity type arranged between the first photoelectric conversion element and the second photoelectric conversion element; and a second semiconductor region having the first conductivity type that is arranged on a region where the plurality of transistors are arranged and that has a width larger than that of the first semiconductor region of the first conductivity type.

Abstract: A solid-state imaging apparatus includes a plurality of pixels, each pixel including: a photoelectric conversion unit; an amplification element; a first signal holding unit and a second signal holding unit arranged on an electric pathway between the photoelectric conversion unit and an input node of the amplification element; a first electric charge transfer unit configured to transfer an electron of the photoelectric conversion unit to the first signal holding unit; and a second electric charge transfer unit configured to transfer an electron held by the first signal holding unit to the second signal holding unit, wherein a voltage supplied to a first control electrode when the electron of the photoelectric conversion unit is transferred to the first signal holding unit is lower than a voltage supplied to a second control electrode when the electron held by the first signal holding unit is transferred to the second signal holding unit.

Abstract: A solid-state image pickup device is provided which includes a substrate; a transistor formed on the substrate; a photoelectric conversion element including a first electrode connected to a drain or a source of the transistor, a semiconductor layer stacked on the first electrode, and a second electrode stacked on the semiconductor layer; an insulating layer disposed on the second electrode; and a bias line formed on the insulating layer to be connected to the second electrode, in which the insulating layer contains at least an inorganic insulating film, and the bias line is connected to the second electrode via a contact hole formed in the insulating layer, and a side surface of the semiconductor layer is in contact with the inorganic insulating film.

Abstract: An image sensor includes a substrate having opposite first and second sides, a multilayer structure on the first side of the substrate, and a photo-sensitive element on the second side of the substrate. The photo-sensitive element is configured to receive light that is incident upon the first side and transmitted through the multilayer structure and the substrate. The multilayer structure includes first and second light transmitting layers. The first light transmitting layer is sandwiched between the substrate and the second light transmitting layer. The first light transmitting layer has a refractive index that is from 60% to 90% of a refractive index of the substrate. The second light transmitting layer has a refractive index that is lower than the refractive index of the first light transmitting layer and is from 40% to 70% of the refractive index of the substrate.

Abstract: An image sensor device includes a substrate including a light sensing region therein and a reflective structure on a first surface of the substrate over the light sensing region. An interconnection structure having a lower reflectivity than the reflective structure is provided on the first surface of the substrate adjacent to the reflective structure. A microlens is provided on a second surface of the substrate opposite the first surface. The microlens is configured to direct incident light to the light sensing region, and the reflective structure is configured to reflect portions of the incident light that pass through the light sensing region back toward the light sensing region. Related devices and fabrication methods are also discussed.

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract: Neutralization capacitances are commonly employed to compensate for the Miller effect; however, at higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization. Here, a layout has been provided where a MOS capacitor is merged with a complementary transistor. By having this merged device, the layout is compact and reduces interconnect area, which reduces the effects of parasitic inductance at higher frequencies (i.e., millimeter wave or terahertz). This layout can also be used to implement linearity enhancement schemes.

Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.

Abstract: A method of producing a solid-state image pickup apparatus, including the steps of: forming a plurality of light-receiving portions on a substrate; forming a plurality of transfer gates to be connected to the plurality of light-receiving portions formed on the substrate; forming an insulation film on the substrate; exposing a base by etching the insulation film so that the etched part of the insulation film between the adjacent transfer gates tapers away; and injecting an impurity into the exposed part using the insulation film that has remained after the etching as a mask to thus form an impurity injection portion.

Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may be a multi junction solar cell. The optoelectronic device may have a bi-layer electrical interconnect that is physically and electrically connected to sidewalls of the array of nanostructures. The optoelectronic device may be operated as a multi junction solar cell, wherein each junction is associated with one portion of the device. The bi-layer electrical interconnect allows current to pass from one portion to the next. Thus, the bi-layer electrical interconnect may serve as a replacement for a tunnel junction, which is used in some conventional multi junction solar cells.

Abstract: A plurality of photoelectric conversion elements including a first photoelectric conversion element, a second photoelectric conversion element, and a third photoelectric conversion element, are arranged in a photoelectric conversion apparatus of the present invention. Provided, between the first photoelectric conversion element and the second photoelectric conversion element, is a first semiconductor region of a first conductivity type and of a first width in which a signal charge is a minor charier. And, provided, between the first photoelectric conversion element and the third photoelectric conversion element, is a second semiconductor region of the first conductivity type in a higher impurity concentration and of a second width narrower than the first width at a position deeper in a semiconductor substrate rather than a depth of the first semiconductor region.

Abstract: In various embodiments, image sensors include strapping grids of vertical and horizontal strapping lines conducting phase-control signals to underlying gate conductors that control transfer of charge within the image sensor.

Abstract: A solid-state imaging device having a protective wiring inserted between adjacent pixel pairs so that the generation of electrical charges caused by a voltage variation in adjacent pixel pairs may be restrained, and a method for manufacturing the same. A solid-state imaging device with an additional protective wiring may be provided between pixel pairs to restrain the generation of electric charges within one of the pixel pairs caused by a voltage variation in the other pixel pair. A method for manufacturing a solid-state imaging device with an additional protective wiring which is provided between pixel pairs to restrain the generation of electric charges within one of the pixel pairs caused by a voltage variation in the other pixel pair.

Abstract: A solid-state imaging apparatus, controlling a potential on a semiconductor substrate for an electronic shutter operation, includes: a first semiconductor region of the first conductivity type for forming a photoelectric conversion region; a second semiconductor region of the first conductivity type, formed separately from the photoelectric conversion region, for accumulating carriers; a third semiconductor region of a second conductivity type arranged under the second semiconductor region, for operating as a potential barrier; a fourth semiconductor region of the second conductivity type extending between the first semiconductor region and the semiconductor substrate, and between the third semiconductor region and the semiconductor substrate; and a first voltage supply portion for supplying a voltage to the third semiconductor region; wherein the first voltage supply portion includes a fifth semiconductor region of the second conductivity type arranged in the pixel region, and a first electrode connected to

Abstract: A semiconductor device comprises a semiconductor substrate, and a multilayer wiring structure arranged on the semiconductor substrate, the multilayer wiring structure including a plurality of first electrically conductive lines, an insulating film covering the plurality of first electrically conductive lines, and a second electrically conductive line arranged on the insulating film so as to intersect the plurality of first electrically conductive lines, where the insulating film has gaps in at least some of a plurality of regions where the plurality of first electrically conductive lines and the second electrically conductive line intersect each other, and the width of the gap in a direction along the second electrically conductive line is not larger than the width of the first electrically conductive line.

Abstract: In a photoelectric conversion apparatus including a plurality of focus detection pixels, each focus detection pixel including a photoelectric conversion element, the photoelectric conversion element having a light receiving surface, and a plurality of wiring layers to read a signal supplied by the photoelectric conversion element, the photoelectric conversion apparatus further includes a light shielding film covering a part of the photoelectric conversion element and having the lower surface positioned closer to a plane, which includes a light receiving surface of the photoelectric conversion element and which is parallel to the light receiving surface, than a lower surface of the lowermost one of the plurality of wiring layers.

Abstract: A solid-state imaging device of the type having photoelectric conversion elements formed in a matrix pattern on a semiconductor substrate, vertical transfer elements each of which reads signal charges from the photoelectric conversion elements arranged in the column direction and transfers the signal charges in the vertical direction, and a horizontal transfer element which transfers in the horizontal direction the signal charges sent from each of the vertical transfer elements, the horizontal transfer element includes: a charge transfer channel; a first transfer electrode; a second transfer electrode; and an interelectrode insulating film; with the first transfer electrode and the second transfer electrode being at the same potential.

Abstract: A solid-state imaging device includes: a photoelectric conversion portion that receives an incident light from a back surface side of a silicon layer to perform photoelectric conversion on the incident light; and a pixel transistor portion that outputs signal charges generated in the photoelectric conversion portion towards a front surface side of the silicon layer, wherein a gettering layer having internal stress is provided on the front surface side of the silicon layer at a position to overlap the photoelectric conversion portion on a plan view layout thereof.

Abstract: A device separation insulating film and a device separation semiconductor layer are provided for a device separation section for separating adjacent devices from each other, end portions of the device separation insulating film and end portions of the device separation semiconductor layer are provided to overlap each other in order to surround two sides of an outer-periphery of the voltage conversion section and also to surround a channel section of the charge transfer device and the light receiving devices and an end portion of the device separation insulating film facing an end face of the light receiving device is arranged inwardly below a control electrode with respect to an end face of the control electrode on the light receiving device side.

Abstract: A solid-state imaging element includes a wiring layer; a charge accumulation unit including a semiconductor layer provided on the wiring layer; and a photoelectric conversion film provided on the semiconductor layer, wherein a pinning layer of a conductivity type opposite to a conductivity type of the charge accumulation unit, the pinning layer including an opening, is provided in a region of the charge accumulation unit, the region being located at an interface between the charge accumulation unit and the photoelectric conversion film.

Abstract: A solid-state imaging device of the present invention is capable of thinning signals for each column. The solid-state imaging device includes: photo diodes, a drain into which charges transferred by first column CCDs are swept-off, and transfer control units each of which is provided to the corresponding first column CCDs, and transfers, to a row CCD and to the drain, the charges transferred by the corresponding first column CCDs. Each of the transfer control units includes: a second column CCD which transfers, in a column direction, the charges transferred by the first column CCDs corresponding to the transfer control unit, and a column CCD terminal gate which is provided between the second column CCD and the row CCD, and forms a potential barrier between the second column CCD and the row CCD.

Abstract: A detector including a layer of scintillation material, a layer of spacer material on the scintillation material, and a spectral purity filter layer on the spacer material.

Abstract: A method is provided for processing a substrate. The substrate has at least one filter region, a plurality of bond pads, and a plurality of scribe lines arranged around the filter region and bond pads. A first planarization layer is formed above the substrate. The planarization layer has a substantially flat top surface overlying the filter region, the bond pads and the scribe lines. At least one color resist layer is formed over the first planarization layer and within the filter region while the first planarization layer covers the bond pads and the scribe lines.

Abstract: A structure which meets a high-quality reading requirement and realizes high-speed color reading when the reading section of a color image forming apparatus adopts a color contact image sensor using CCDs as reading element arrays is disclosed. The image sensor of a color image reading section uses a color contact image sensor in which a plurality of CCDs are aligned as reading element arrays in the main scanning direction. In this case, each CCD has one analog shift register for RGB time-division reading, and three R, G, and B reading apertures arranged parallel to each other at a pitch corresponding to the reading resolution. The pixel pitch in the main scanning direction is constant.

Abstract: A solid-state image capturing apparatus according to the present invention includes: a plurality of photoelectric conversion sections; a charge accumulation section; and a charge readout section, the apparatus further includes: a semiconductor substrate including a plurality of diffusion layers formed thereabove, the diffusion layers constituting the photoelectric conversion sections, the charge accumulation section and the charge readout section; a readout gate electrode formed above the semiconductor substrate and constituting the charge readout section; an insulation sidewall formed on a side surface of the readout gate electrode; and a surface diffusion layer constituting the photoelectric conversion sections, which is positioned in a self-aligning manner with respect to the readout gate electrode by the insulation sidewall.

Abstract: A solid-state image capturing device includes a multilayer wiring layer to open regions above a plurality of respective light receiving sections for performing photoelectric conversion on incident light to generate a signal charge; a color filter of each color provided above the multilayer wiring layer in a corresponding manner to each light receiving section; and a microlens provided on the color filter of each color, for focusing the incident light at each light receiving section, wherein a wiring layer within one layer among the multilayer wiring layer limits an area of a light receiving region for incident light that enters the light receiving section, equally among the light receiving sections.

Abstract: The pixel for use in an image sensor comprises a low-doped semiconductor substrate (A). On the substrate (A), an arrangement of a plurality of floating areas, e.g., floating gates (FG2-FG6), is provided. Neighboring floating gates are electrically isolated from each other yet capacitively coupled to each other. By applying a voltage (V2?V1) to two contact areas (FG1, FG7), a lateral steplike electric field is generated. Photogenerated charge carriers move along the electric-field lines to the point of highest potential energy, where a floating diffusion (D) accumulate the photocharges. The charges accumulated in the various pixels are sequentially read out with a suitable circuit known from image-sensor literature, such as a source follower or a charge amplifier with row and column select mechanisms. The pixel of offers at the same time a large sensing area, a high photocharge-detection sensitivity and a high response speed, without any static current consumption.

Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.

Abstract: In each of pixels 10 arranged in an array pattern, an insulating isolation part 22 electrically isolates adjacent photoelectric conversion elements 11, and the photoelectric conversion element 11 and an amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. A low concentration first isolation diffusion layer 23 is formed below the insulating isolation part 22 constituting the first region A, and a high concentration second isolation diffusion layer 24 and a low concentration first isolation diffusion layer 23 are formed below the insulating isolation part 22 constituting the second region B. A source/drain region of the amplifier transistor 14 in the second region B is formed in a well region 25 formed simultaneously with the second isolation diffusion layer 24.

Abstract: A CMOS image sensor for improving light sensitivity and peripheral brightness ratio, and a method for fabricating the same. The CMOS image sensor includes a substrate on which a light sensor and device isolating insulation films are formed, in which the top of the substrate is coated with a plurality of metal layers and oxide films; a plurality of reflective layers formed inside the metal layers, each being spaced apart; a color filter embedded in a groove formed by etching the oxide films inside the reflective layers by a predetermined thickness; a plurality of protrusions formed on both sides of the top of the color filter, each arranged at a predetermined distance from one another; a flat layer formed on the top of the protrusions and the oxide films; and a micro-lens formed on the top of the flat layer. The reflective layer disposed at the top of the photodiode is made of a material having a high reflectance and low absorptivity.

Abstract: A pixel of a complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of photodiodes for sensing light to thereby generate photoelectric charges in different regions; a plurality of transfer transistors for transferring photoelectric charges of corresponding photodiodes in response to a first control signal; a floating diffusion region for receiving photoelectric charges transferred by the plurality of transfer transistors; a rest transistor connected between a power supply voltage and the floating diffusion region for resetting the floating diffusion region by controlling a voltage loaded on the floating diffusion region in response to a second control signal; a drive transistor connected between the power supply voltage and the floating diffusion region to serve as a source follower buffer amplifier; and a select transistor connected between the drive transistor and a pixel output terminal for performing an addressing operation in response to a third control signal.

Abstract: Disclosed herein is a solid-state imaging device including, a first semiconductor region of the first conduction type, a photoelectric conversion part having a second semiconductor region of the second conduction type formed in the region separated by the isolation dielectric region of the first semiconductor region, pixel transistors formed in the first semiconductor region, a floating diffusion region of the second conduction type which is formed in the region separated by the isolation dielectric region of the first semiconductor region, and an electrode formed on the first semiconductor region existing between the floating diffusion region and the isolation dielectric region and is given a prescribed bias voltage.

Abstract: It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel.

Abstract: The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer (12, 16) of second conductivity type is formed on a main surface of a first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) are formed at least on the second semiconductor layer to separate the device into the regions of photodiodes (PD1-PD4). A conductive layer (18) is formed on the second semiconductor layer 16 in a divided pattern that provides a segment for each photodiode and is connected to the second semiconductor layer (16) along the an outer periphery with respect to all photodiodes. An insulation layer (19, 21) is formed on the entire surface to cover conductive layer (18). An opening, which reaches the second semiconductor layer (16), is formed in the insulation layer (19, 21) in the region inside the pattern of conductive layer (18).

Abstract: An organic electroluminescent device includes first and second substrates facing each other and spaced apart from each other; a gate line on an inner surface of the first substrate; a data line and a power line crossing the gate line and spaced apart from each other; a switching thin film transistor connected to the gate line and the data line; a driving thin film transistor connected to the switching thin film transistor and the power line, the driving thin film transistor including a channel region having a ring shape; an electric connection pattern connected to the driving thin film transistor, the connection pattern being disposed over the driving thin film transistor; and an organic electroluminescent diode on an inner surface of the second substrate, the organic electroluminescent diode being connected to the electric connection pattern.

Abstract: A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates.

Abstract: A solid-state imaging device includes: a semiconductor substrate; photoelectric conversion elements; vertical charge transfer paths that transfer charges generated in photoelectric conversion elements, in a vertical direction; a horizontal charge transfer path that transfers the charges transferred in vertical charge transfer paths, in a horizontal direction orthogonal to the vertical direction; a plurality of charge accumulating sections between the vertical charge transfer paths and the horizontal charge transfer path; a plurality of electrodes disposed above the respective charge accumulating sections, the plurality of electrodes being classified into a plurality of kinds of electrodes; wirings corresponding to the respective kinds of electrodes and extending in the horizontal direction above the plurality of electrodes; and a planarizing layer disposed between the wirings and an uneven surface caused by the plurality of electrodes that are present in areas overlapping the wirings, so as to planarize the u