Abstract: A charge transfer device is provided which is capable of reducing a reset field-through noise in a stable manner without being affected by characteristics of transistors and without occurrence of a mustache-shaped pulse-like noise.

Abstract: In the conventional column-side block redundancy for DRAM, competition for the replacing regions occurs unless a repair address of a large number of bits is stored in order to replace with a small replacement unit. According to one aspect of the invention, replacement decision is performed in order that a second replacement region can be made smaller than a first replacement and that the second replacement is given priority over the first replacement. Therefore, the first replacement can be controlled by a repair address of a small number of bits, thus making it possible to achieve a semiconductor device having a defect repair circuit with small area and high repair efficiency.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: In a charge coupled device, trap levels formed by insulating layers or floating electrodes are formed on a semiconductor layer or a semiconductor substrate. Stationary charges are trapped in some of the trap levels or floating electrodes. The charge transfer electrodes are in self-alignment with potential barrier regions.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer.

Abstract: There is provided a charge transfer device including (a) a charge transfer channel for transferring signal charges therethrough, (b) a floating diffusion region for accumulating therein charges transferred from the charge transfer channel, (c) a field effect transistor for resetting the floating diffusion region so that the floating diffusion region is at a predetermined potential and (d) a bias charge input section through which a bias charge is supplied and which is connected to either the charge transfer channel or the floating diffusion region. The field effect transistor includes a reset gate electrode and a reset drain.

Abstract: A charge transfer structure (30) includes a substrate comprised of semiconductor material and, coupled to a surface of the substrate, a plurality of serially coupled devices each having a gate terminal. The plurality of serially coupled devices include a first single port device (D1) defining a first primary charge storage well, a second single port device (D3) defining a second primary charge storage well, a first two port device (D2) defining a first transfer device, a second two port device (D4) defining a second transfer device, and two instances of a third two port device each defining a cascode device (CD). The ports of these devices are serially coupled together in an order given by D1, D2, CD, D3, D4, CD for transferring charge between the first and second primary charge storage wells. Charge is inserted into and withdrawn from each of the first and second primary charge storage wells through a single diffusion that functions as both an input port and an output port.

Abstract: A bi-directional multi-tapped CCD sensor readout structure includes a well formed in a substrate, a channel formed in the well defining a channel direction, and a clocking structure disposed over the channel and oriented transversely to the channel direction. The clocking structure includes a plurality of register element sets. A first register element set includes a first floating sensing conductor and a plurality of clock signal conductors. The plurality of clock signal conductors includes a first clock signal conductor under which is defined a first junction at the electrical semiconductor junction between the well and the substrate and a second junction at the electrical semiconductor junction between the channel and the well. The first and second junctions define an inter-junction separation. The well is formed in the substrate and the channel is formed in the well so that a length of the inter-junction separation is controllable by a first clock signal applied to the first clock signal electrode.

Abstract: a pixel is formed in a substrate having a first conductivity type, the pixel being coupled to a register for output. The pixel includes a pixel channel of a second conductivity type formed in the substrate, a transfer gate electrode, a storage gate electrode and a photodiode. The pixel channel includes a transfer portion at a first end of the pixel channel proximal to the register, a diode portion at a second end distal to the register and a storage portion between the transfer portion and the diode portion. The transfer gate electrode is insulatively spaced over the transfer portion, and the storage gate electrode is insulatively spaced over the storage portion. The diode is formed within the diode portion using the storage gate electrode as a mask.

Abstract: The present invention is a active pixel sensor cell and method of making and using the same. The active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

Abstract: A CCD sensor includes a readout register formed in substrate, the readout register including a channel, a bus structure and a connection structure. The bus structure includes plural spaced element sets, each element set including a first clock conductor. The first clock conductor of a first element set is a dual function conductor. The connection structure isolates the dual function conductor while coupling together the first clock conductor of each other set of the element sets. Alternatively, the sensor includes vertical and readout registers formed in a well in a substrate. The vertical register includes a vertical channel, a vertical bus structure and a vertical connection structure, and the readout register includes a readout channel, a readout bus structure and a readout connection structure. The readout bus structure includes plural spaced readout element sets, each readout element set including a first readout clock conductor.

Abstract: The disclosure relates to charge-coupled devices taking the form of shift registers and, more specifically, to those working in the MPP (Multi-Pinned Phase) mode, i.e. with high negative polarisation of the electrodes during the phases of waiting or of integration of integration of the photosensitive charges. These registers use a potential barrier created by a P type compensating implantation in a zone 16 located beneath a first electrode of each stage of the register. This barrier separates the stages from one another. To increase the charge storage capacity during the storage phase and the charge transfer capacity during the transfer, it is provided that the compensating implantation of the zone 16 will extend beneath only one part (and not the totality) of the first electrode of each stage of the register. Application to photosensitive image sensors, analog delay lines, charge-coupled analog memories, working in MPP mode during the waiting phases to limit losses of information due to the dark current.

Abstract: The present invention is directed to an improved CCD utilizing a potential gradient along the lengths of the various channels of the CCD during charge transfer to cause generated electrical charge to migrate along the length of the channel to a summing well. The potential gradient is formed by biasing the opposing ends of the electrodes overlying the lengths of the various channels with different voltages.

Abstract: In order to realize a multi-function sensor in which a reduction of a CMOS sensor and an addition of pixel signals are performed in a pixel portion and, further, an addition and a non-addition can be arbitrarily performed, there is provided a solid state image pickup apparatus in which charges generated by a photoelectric converting device are perfectly transferred to a floating diffusion portion through a transfer switch and a change in electric potential of the floating diffusion portion is outputted to the outside by a source-follower amplifier. A few photoelectric converting devices are connected to one floating diffusion portion through the transfer switch. One set of a few source-follower amplifiers are formed for a few pixels. The photoelectric converting device is constructed by an MOS transistor gate and a depletion layer under the gate.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: A MOS device and method of fabricating the same, wherein the source/drain region has polysilicon trench structure which are formed by self-alignment using silicon oxide layers as masks. The source/drain regions extend to the field oxide layer and/or above the gate. Therefore, contacts can be formed on source/drain conductive regions above the field oxide layer.

Abstract: A control structure for stage selection in a CCD sensor includes a well formed in a substrate and a channel formed in the well, the channel defining a channel direction. A bus structure is disposed over the channel and oriented transversely to the channel direction, the bus structure including a plurality of uniformly spaced register element sets. The plurality of uniformly spaced register element sets includes a first register element set and a plurality of remaining register element sets. The first register element set includes a first clock signal conductor and at least one other clock signal conductor. Each set of the plurality of remaining register element sets includes a first clock signal conductor and at least one other clock signal conductor.

Abstract: An active type photoelectric conversion device includes a pixel having a photoelectric conversion area and a gate area which are formed in a surface portion of a semiconductor substrate of a first conductivity type.

Abstract: A solid-state CCD image pick-up device includes optoelectric transducing elements corresponding to pixels vertically and horizontally arrayed in a matrix forming column linear arrays defining a column direction and at least one vertical charge transfer path associated with a corresponding adjacent column linear array. Pixel signals are vertically transferred from the column linear arrays to the vertical charge transfer paths such that gate signals occurring at predetermined times are applied to gate electrodes of the vertical charge transfer paths to permit the pixel signals to be scan read by a horizontal charge transfer path. Switching elements are provided for transfer gate electrodes and a drive circuit sequentially generates drive signals for groups of gate electrodes during periods in which the switching elements are rendered conductive to allow a full frame scan read to be performed by supplying a predetermined number of timing signals to the gate electrodes.

Abstract: A charge transferring apparatus comprising, e.g., a buried type charge coupled device in which a pair of transfer electrodes located at the most downstream point of a charge transfer direction is driven by a drive pulse other than that for any other pair of transfer electrodes and a potential well formed at the pair of the transfer electrodes located at the most downstream point is made shallower than that at any other pair of transfer electrodes allowing the output dynamic range of a charge transfer device to be increased for improving the output quality.

Abstract: The semiconductor device of the present invention is equipped with a plurality of photodiodes, a horizontal transfer part and a vertical transfer part, and in particular, the horizontal transfer part or the vertical transfer part has a configuration described as in the following. Namely, the device has a semiconductor region which is formed by regularly and consecutively arranging a plurality of blocks of the same conductivity type, where each of the plurality of the blocks is equipped with three regions of mutually different impurity concentrations, clock pulses are applied to two regions out of the three regions and the voltage of the high level or low level of the clock pulse is applied to the remaining region out of the three regions as a constant potential.

Abstract: The amplification type solid-state imaging device of this invention includes amplification type photoelectric converting elements arranged in a matrix.

Abstract: A charge transfer device is disclosed in which the number of transfer clocks can be decreased, and also, power consumption, the heating amount and parasitic emissions are also reduced. Three groups of electrodes are repeatedly disposed in an alternating sequence above an N-type channel (transfer channel). Among the three groups of electrodes, a predetermined DC bias voltage supplied from a DC power supply is applied to one group of electrodes. Between the remaining two groups of electrodes, a single-phase transfer clock H.phi. supplied from the exterior of the device is directly applied to one group of electrodes, while a transfer clock H.phi.' produced by delaying the transfer clock H.phi. by a predetermined delay time in a delay circuit is applied to the other group of electrodes. Also disclosed is a solid-state imaging apparatus using the above-described charge transfer device.

Abstract: Channel coupled feedback- technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.

Abstract: A charge generation device configured within a semiconductor region of a substrate. The device includes a source for providing an input charge and an input diffusion which receives said input charge. A barrier gate associated with the input diffusion determines a selected potential of the input diffusion. A preset diffusion presets the input diffusion to the selected potential. An output element receives the input charge from the input diffusion. A first coupling means is provided for coupling the preset diffusion to the input diffusion subsequent to the output diffusion receiving the input charge during a first clock cycle, and for decoupling the preset diffusion from the input diffusion prior to the input diffusion receiving the input charge during a second clock cycle.

Abstract: A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

Abstract: A solid-state image sensing apparatus comprises a charge coupled device, a plurality of photosensors, and a voltage generator. Each of the photosensors receives incident light, generates a voltage logarithmically proportional to an intensity of the incident light, and is connected to a first electrode of the charge coupled device. The voltage generator generates a reference voltage logarithmically proportional to an average intensity of the incident light on the photosensors and is connected to a second electrode of the charge coupled device. Signal charges are injected into the charge coupled device, depending on the voltage impressed on the first and second electrodes, so that a direct current component of an output of the charge coupled device is controlled.

Abstract: A preferred embodiment of this invention is a hybrid semiconductor imaging structure comprising a high speed signal conditioning substrate (e.g. Si 12) and an imaging substrate (e.g. HgCdTe 10) mounted on the conditioning substrate using an adhesive layer (e.g. epoxy 31). Infrared-sensitive time delay and integration CCD columns (14) charge coupled to sense nodes (e.g. diodes 16) are disposed in the imaging substrate. High speed signal processing channels (e.g. capacitive transimpedance amplifier 18, congelated double sampling circuit 20 and multiplexing shift register 22) are disposed in the conditioning substrate. The sense nodes are connected to the signal processing channels with low capacitance hybrid leads (e.g AI 17).

Abstract: The invention relates to a semiconductor device with which input signals can be weighted and the weighted input signals can be summed, and which in conjunction with a neuron can be used, for example, as a synapse in a neural network. The device comprises a number of switched capacitances with a common capacitor plate formed by a surface region 3 in a p-type substrate 1. The region 3 is connected to the inverting input of an amplifier 11 whose +input is connected to a reference voltage and whose output 12 supplies the summed output signal. The output 12 can be fed back to the input 3 via switch S. The other plate of the capacitances is formed by an electrode 6a, 6b, 6c, which can be switched between a reference voltage and an input source. The weight factors are stored in the form of electric charges on a floating gate 5a, 5b, 5c, which is provided between each input electrode 6 and the surface region 3.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: An ionic liquid-channel charge-coupled device that separates ions in a liquid sample according to ion mobility characteristics includes a channel having an inner wall that has a matrix liquid disposed within. An insulating material surrounds the channel, and an introduction element introduces a liquid sample into the channel. The sample is preferably a liquid solution that has at least one ionic specie present in the solution. The device further includes a gating element that establishes at least one charge packet in the channel in response to an externally applied input signal, and a transport element that induces the charge packet to migrate through the channel. The gate element can be a plurality of spaced-apart, electrically conductive, gate structures that are alternately disposable between a high voltage state and a low voltage state. The transport element further includes an application element that applies a variable voltage to the gating element.

Abstract: The charge transfer device according to the present invention includes: a plurality of vertical transfer channels; a first transfer gate electrode placed at the ends of the plurality of vertical transfer channels for receiving signal charge from the plurality of vertical transfer channels and for outputting the signal charge; a plurality of horizontal transfer channels having a plurality of layers of gate electrodes for transferring the signal charge from the first transfer gate electrode in a horizontal direction; at least one second transfer gate electrode disposed between the plurality of horizontal transfer channels for transferring the signal charge from one of the horizontal transfer channels to another horizontal transfer channel; a conductive portion for supplying a transfer control signal to the plurality of horizontal transfer channels; at least one output section for converting the signal charge transferred from the plurality of horizontal transfer channels into a voltage signal and for outputting

Abstract: The present invention is directed toward an image sensor array comprising a plurality of pixels. Each pixel includes a photodiode and a CCD channel region. An overflow drain region is provided adjacent the CCD channel region for extraction of excess charges. An insulated gate read-out transfer electrode is further provided above the CCD channel region and a portion of the substrate between the CCD channel region and the photodiode. Three different potentials are applied to the read-out transfer electrode for respectively storing charge in the photodiode, extracting excess charge from the photodiode while allowing signal charge to remain in the photodiode, and reading out signal charge from the photodiode.

Abstract: A frame interline transfer CCD imager is so adapted that signal charges from the photosensor are read into a vertical transfer unit and are transferred at a high transfer rate from the vertical transfer unit to a storage section. The charges from each photosensor are drained during the high transfer rate transfer so that the photosensors are unable to store the signal charges to prevent the occurrence of blooming.

Abstract: A charge transfer device includes: a transfer channel for transferring a charge in a charge transfer direction; a charge detecting section having a diffusion layer for storing the charge transferred through the transfer channel and for inducing a voltage corresponding to the amount of the stored charge; and a transistor for detecting the induced voltage, the transistor having: a gate electrode formed on the diffusion layer, the gate electrode being in direct contact with the diffusion layer; a gate insulating film formed on the gate electrode; and a channel region formed above the gate electrode.

Abstract: A signal charge transfer device. The device comprises a well of a first conductivity type, a channel region of a second conductivity type formed on the well, and a gate insulation film formed on the channel region. A plurality of equally spaced first charge transfer electrodes of the second conductivity type are formed on the gate insulation film. A plurality of second charge transfer electrodes of the first conductivity type are formed between the plurality of first charge transfer electrodes. An insulation film electrically isolates the plurality of first charge transfer electrodes from the plurality of second charge transfer electrodes.

Abstract: An ionic liquid-channel charge-coupled device that separates ions in a liquid sample according to ion mobility characteristics includes a channel having an inner wall that has a matrix liquid disposed within. An insulating material surrounds the channel, and an introduction element introduces a liquid sample into the channel. The sample is preferably a liquid solution that has at least one ionic specie present in the solution. The device further includes a gating element that establishes at least one charge packet in the channel in response to an externally applied input sisal, and a transport element that induces the charge packet to migrate through the channel. The gate element can be a plurality of spaced-apart, electrically conductive, gate structures that are alternately disposable between a high voltage state and a low voltage state. The transport element further includes an application element that applies a variable voltage to the gating element.

Abstract: A semiconductor apparatus connected between a signal input line and a grounding line is formed on a semiconductor substrate with a protection circuit connected between the signal input line and the grounding line, in parallel with the semiconductor apparatus. The protection circuit is formed, for example, of bipolar transistors, diodes, or MOS transistors.

Abstract: A CCD which is designed and processed so that most of each pixel is covered only with an ultra-thin gate electrode so that the CCD can be frontside illuminated and still achieve good sensitivity in the ultra-violet and soft x-ray spectral range. More specifically, in the present invention, the usual three gate structure and corresponding polysilicon layers 1, 2 and 3 of conventional thickness are reduced in width and supplemented by a fourth ultra-thin layer of polysilicon dubbed herein, poly 4, that is deposited over the entire array. This fourth layer, poly 4, makes contact with poly 3, so that when poly 3 is driven, it also drives poly 4, thus allowing charge to collect and transfer as in a normal three phase CCD. However, because the deposition thickness of the poly 4 layer is on the order of 400 Angsttoms, as opposed to conventional thicknesses of 2000 to 5000 Angsttoms, poly 4 is essentially transparent to photons and thereby allows achievement of high quantum efficiency.

Abstract: In a linear sensor, a charge transfer part is disposed between a one-dimensional array of photodetectors and an overflow drain and includes a CCD having four or more transfer gates for each photodetector for transferring signal charges from the photodetector array in a direction of the photodetector array, transfer gates controlling charge transfer from the photodetectors to the CCD, and shutter gates for controlling charge transfer from the charge transfer part to the overflow drain. Each transfer gate is disposed between each photodetector and a prescribed one of the four or more transfer gates, and each shutter gate is disposed between the prescribed transfer gate and the overflow drain. The four or more CCD transfer gates are controlled by four or more phase driving clocks.

Abstract: A charge transfer device in which a charge transfer section, an output gate, a floating diffused region, a reset gate electrode, a reset drain region, a barrier gate electrode and an absorption drain region are provided in semiconductor substrate. The reset drain region for resetting or draining charges in the floating diffused region is connected via a capacitor to a constant potential terminal. The absorption drain region is provided with a voltage booster for raising the amplitude of the transfer pulse to a level higher than the power source voltage. The output voltage of the voltage booster is supplied to the absorption drain region. The channel potential beneath the barrier gate electrode is set lower than that beneath the reset gate electrode.

Abstract: A solid state imager element has a sensor portion, a register portion and a read gate portion for reading a signal charge from the sensor portion and transferring the same to the register portion, wherein a potential difference is formed in the read gate portion in a reading and transferring direction for directing an unnecessary charge or noise toward the register portion to thereby suppress noise in the sensor portion.

Abstract: A multi-color imaging charge-coupled array comprises a plurality of photosensitive layers, each sensitive to a specific range of wavelengths as would be found in a full-color image. The various photosensitive layers are separated by boundary layers of high band-gap energy, so that charge packets formed within individual layers are insulated from charge packets formed in other layers within the same pixel. The combination of photosensitive layers and high band-gap boundary layers cause charge packets to be formed in potential wells within each pixel area of the charge-coupled array.

Abstract: A CCD image sensor of an interlaced scanning type comprising a plurality of uniformly spaced photodetectors arranged in series in vertical and horizontal directions, a plurality of VCCD regions arranged between sets of said photodetectors arranged in the vertical directions, a plurality of channel stop regions for electrically isolating said plurality of photodetectors from one another, a plurality of gate electrodes formed on said VCCD regions, each of said plurality of gate electrodes being connected simultaneously to transfer gate electrodes of adjacent ones of said plurality of photodetectors on odd and even horizontal lines, a plurality of barrier layers, each formed at a portion of each of said VCCD regions corresponding to a boundary with each of said gate electrodes on said VCCD regions, for forming a desired potential barrier, and a HCCD region formed under said plurality of VCCD regions, for transferring signal charges from said VCCD regions to an output stage.

Abstract: In an output circuit for a charge transfer device, a floating diffusion region is connected to a source side gate electrode of a double-gate read-out field effect transistor having its drain side gate electrode connected to the drain of the read-out transistor itself. Thus, the capacitance between the gate of the read-out transistor connected to the floating diffusion region and the drain of the read-out transistor can be made small, so that the total capacitance of the floating diffusion region is correspondingly reduced, with the result that a high detection sensitivity can be realized.

Abstract: An improved CCD image sensor which contains a plurality of photodetectors is provided with a transfer gate and uses a CCD as a scanner for reading signals, and having photo diodes which are connected consecutively to both the left and right sides of VCCD region and, in the parts without VCCD region, are disposed repeatedly parallel to each other separated by an interval of the width of the channel stop region. A 4 phase clock signal consisting of 4 fields is used for operation of said CCD image sensor. The resultant CCD image sensor has an increased photodetector area which can provide high resolution of video.

Abstract: There is disclosed a solid-state image sensor comprising: photo-detecting devices arranged in a matrix structure for receiving external light signals; vertical charge transfer device interposed between the columns of said photo-detecting device for vertically transferring the charges produced from said photo-detecting device according to external control signal; first horizontal charge transfer device for horizontally transferring the charges coming out of said vertical charge transfer device according to external control signal; output control device for controlling the charges flowing from said first horizontal charge transfer device to said output device; second horizontal charge transfer device for transferring the output charges of said first horizontal charge transfer device controlled by said output control device to said vertical charge transfer device according to external control signal; and a feedback line for connecting the output of said first horizontal charge transfer device to the input of sai

Abstract: A charge-coupled device comprises transfer gate electrodes separated from a substrate by a multi-layer insulating film, and gate electrodes of MIS transistors separated from the substrate by a single layer insulating film. The multilayer insulating film comprising at least a lower silicon oxide layer of 10 nm to 200 nm thickness and an upper silicon nitride layer of 10 nm to 100 nm thickness. Since each of the gate insulating films of the MIS transistors is the same layer as the lower silicon oxide layer, there occurs no degradation in the transistor characteristics due to the surface states or the trapping states present within the silicon nitride layer.

Abstract: An image sensing device that outputs a signal logarithmically proportional to the intensity of the incident light. The image sensing device makes use of a sub-threshold current flowing between the drain and source of a MOS transistor when the gate voltage is below the threshold voltage (above which the MOS transistor is nominally conductive and below which nominally non-conductive). Since the logarithmic conversion is done in the photosensing section of a solid-state image sensing device, the output from the device is already compressed and is easily handled by a small capacity CCD. Some output systems for the image sensing device of the present invention are also described.

Abstract: An interline transfer type area image sensor which operates in a non-interlaced mode and has an array of columns and rows of photoreceptor in which charge from each pixel is transferred into a stage of a vertical two-phase CCD shift register formed by adjacent electrodes of the CCD. Each electrode of a stage has a separate voltage clock. An ion implanted vertical transfer barrier region is formed under an edge of each electrode.