Phase Structure (e.g., Doping Variations To Provide Asymmetry For 2-phase Operation; More Than Four Phases Or "electrode Per Bit") Patents (Class 257/246)
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Patent number: 11937522Abstract: A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.Type: GrantFiled: May 10, 2021Date of Patent: March 19, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dexin Kong, Takashi Ando, Kangguo Cheng, Juntao Li
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Patent number: 11107985Abstract: Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith are disclosed and described. Such electrodes can have a resistivity of from 10 to 100 mOhm·cm.Type: GrantFiled: December 3, 2019Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Valter Soncini, Davide Erbetta
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Patent number: 10892406Abstract: A phase change memory (PCM) cell can include a PCM layer. A first electrode and a second electrode disposed on opposite sides of the PCM layer. The first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer and wherein the metal ceramic composite material layer provides a corresponding electrode with an electrical resistivity of from 10 mOhm-cm to 1000 mOhm-cm.Type: GrantFiled: June 4, 2018Date of Patent: January 12, 2021Assignee: Intel CorporationInventors: Stephen Russell, Andrea Gotti, Andrea Redaelli, Enrico Varesi, Innocenzo Tortorelli, Lorenzo Fratin, Alessandro Sebastiani
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Patent number: 10872649Abstract: Disclosed are memory devices including a variable resistance memory cell and a word line control circuit. A memory device including a variable resistance memory cell including a variable resistance element, a first cell transistor, and a second cell transistor, a first end of the variable resistance element connected to a bit line, a second end of the variable resistance element, a first end of the first cell transistor, and a first end of the second cell transistor connected to the common node, a second end of the first cell transistor and a second end of the second cell transistor connected to a source line, and a word line control circuit configured to separate a sub word line connected to a gate electrode of the second cell transistor from a word line connected to a gate electrode of the first cell transistor in a first write operation and to connect the word line and the sub word line to each other in a second write operation may be provided.Type: GrantFiled: July 10, 2019Date of Patent: December 22, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung Min Lee, Hyunsung Jung
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Patent number: 10680175Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.Type: GrantFiled: December 21, 2018Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Karthik Sarpatwari, Dale Collins, Anna Maria Conti, Fred Daniel Gealy, III, Andrea Gotti, Swapnil Lengade, Stephen Russell
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Patent number: 10281420Abstract: A gas-detecting apparatus includes a gas sensor and a power supply circuit. The gas sensor includes: a first electrode; a second electrode; a metal oxide layer disposed between the first electrode and the second electrode; and an insulation film covering the first electrode, the second electrode, and the metal oxide layer. The insulation file having an opening from which a surface of the second electrode is exposed. The resistance value of the metal oxide layer decreases when gas containing hydrogen atoms comes into contact with the second electrode. The power supply circuit applies a predetermined voltage between the first electrode and the second electrode to increase the resistance value of the metal oxide layer before and/or after the decrease in the resistance value of the metal oxide layer.Type: GrantFiled: March 29, 2017Date of Patent: May 7, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Shunsaku Muraoka, Kazunari Homma, Zhiqiang Wei, Koji Katayama
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Patent number: 10157788Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.Type: GrantFiled: January 19, 2016Date of Patent: December 18, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Fabio Pellizzer, Antonino Rigano, Roberto Somaschini
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Devices for thermally induced transformations controlled by irradiation of functionalized fullerenes
Patent number: 9731013Abstract: An electromagnetic radiation activated device comprises a property changing material and at least one functionalized fullerene that upon irradiation of the functionalized fullerenes with electromagnetic radiation of one or more frequencies a thermally activated chemical or physical transformation occurs in the property changing material. The thermal activated transformation of the property changing material is triggered by the heating or combustion of the functionalized fullerenes upon their irradiation. The device can include a chemical agent that is embedded in the property changing material and is released when the material is heated by the functionalized fullerenes upon irradiation.Type: GrantFiled: March 24, 2015Date of Patent: August 15, 2017Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.Inventors: Vijay Krishna, Karl R. Zawoy, Brij M. Moudgil, Benjamin L. Koopman, Nathanael Ian Stevens, Kevin William Powers -
Patent number: 9362493Abstract: The present invention provides a phase-change storage unit for replacing DRAM and FLASH and a manufacturing method thereof, and the phase-change storage unit includes a phase-change material layer and a cylindrical lower electrode being in contact with and located below the phase-change material layer, where the phase-change material layer is formed by connecting a side wall layer and a round bottom layer, forms a hollow cylinder or hollow inverted conical frustum having an opening at an upper part, and the hollow cylinder or hollow inverted conical frustum is internally filled with a medium layer.Type: GrantFiled: December 26, 2012Date of Patent: June 7, 2016Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCESInventors: Feng Rao, Kun Ren, Zhitang Song, Yuefeng Gong, Wanchun Ren
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Patent number: 9236566Abstract: Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa.Type: GrantFiled: July 14, 2015Date of Patent: January 12, 2016Assignee: Micron Technology, Inc.Inventors: Camillo Bresolin, Valter Soncini, Davide Erbetta
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Patent number: 9184384Abstract: Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first conductive structure. The opening has a bottom level with a bottom width. The opening has a second level over the bottom level, with the second level having a second width which is greater than the bottom width. The bottom level of the opening is filled with a first portion of a multi-portion programmable material, and the second level is lined with the first portion. The lined second level is filled with a second portion of the multi-portion programmable material. A second conductive structure is formed over the second portion. Some embodiments include memory cells.Type: GrantFiled: May 23, 2014Date of Patent: November 10, 2015Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Scott E. Sills
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Patent number: 9118004Abstract: Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa.Type: GrantFiled: April 9, 2014Date of Patent: August 25, 2015Assignee: Micron Technology, Inc.Inventors: Camillo Bresolin, Valter Soncini, Davide Erbetta
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Patent number: 9006793Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.Type: GrantFiled: June 29, 2011Date of Patent: April 14, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
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Patent number: 8952427Abstract: A range image sensor capable of improving its aperture ratio and yielding a range image with a favorable S/N ratio is provided. A range image sensor RS has an imaging region constituted by a plurality of one-dimensionally arranged units on a semiconductor substrate 1 and yields a range image according to a charge amount issued from the units.Type: GrantFiled: November 18, 2010Date of Patent: February 10, 2015Assignee: Hamamatsu Photonics K.KInventors: Takashi Suzuki, Mitsuhito Mase
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Patent number: 8937341Abstract: A charge-coupled unit formed in a semiconductor substrate and including an array of identical electrodes forming rows and columns, wherein: each electrode extends in a cavity with insulated walls formed of a groove, oriented along a row, dug into the substrate thickness, and including, at one of its ends, a protrusion extending towards at least one adjacent row.Type: GrantFiled: June 23, 2010Date of Patent: January 20, 2015Assignee: STMicrelectronics (Crolles 2) SASInventor: François Roy
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Patent number: 8847288Abstract: A spin transistor according to an embodiment includes: a semiconductor layer including a p+-region and an n+-region located at a distance from each other, and an i-region located between the p+-region and the n+-region; a first electrode located on the p+-region, the first electrode including a first ferromagnetic layer; a second electrode located on the n+-region, the second electrode including a second ferromagnetic layer; and a gate located on at least the i-region.Type: GrantFiled: January 25, 2013Date of Patent: September 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
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Patent number: 8803259Abstract: Systems, apparatus, and associated methods of forming the systems and/or apparatus may include imaging devices that may comprise multiple arrays of ultrasonic transducer elements for use in a variety of applications. These multiple arrays of ultrasonic transducer elements can be arranged to form a three-dimensional imaging device. Non-coplanar arrays of ultrasonic transducer elements can be coupled together. These imaging devices may be used as medical imaging devices. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: February 11, 2013Date of Patent: August 12, 2014Assignee: STC.UNM & University of New MexicoInventor: Jingkuang Chen
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Patent number: 8779474Abstract: The electric device (1, 100) has a body (2, 101) with a resistor (7, 250) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 250) has an electric resistance which depends on whether the phase change material is in the first phase or the second phase. The resistor (7, 250) is able to conduct a current for enabling a transition from the first phase to the second phase. The phase change material is a fast growth material which may be a composition of formula Sb1?cMc with c satisfying 0.05?c?0.61, and M being one or more elements selected from the group of Ge, In, Ag, Ga, Te, Zn and Sn, or a composition of formula SbaTebX100?(a+b) with a, b and 100?(a+b) denoting atomic percentages satisfying 1?a/b?8 and 4?100?(a+b)?22, and X being one or more elements selected from Ge, In, Ag, Ga and Zn.Type: GrantFiled: December 3, 2003Date of Patent: July 15, 2014Assignee: NXP, B.V.Inventors: Martijn Henri Richard Lankhorst, Liesbeth Van Pieterson, Robertus Adrianus Maria Wolters, Erwin Rinaldo Meinders
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Patent number: 8772121Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.Type: GrantFiled: April 10, 2012Date of Patent: July 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Man Hwang, Jun-Soo Bae, Sung-Un Kwon, Kwang-Ho Park
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Patent number: 8748945Abstract: Image sensors are provided. The image sensors may include first and second stacked impurity regions having different conductivity types. The image sensors may also include a floating diffusion region in the first impurity region. The image sensors may further include a transfer gate electrode surrounding the floating diffusion region in the first impurity region. Also, the transfer gate electrode and the floating diffusion region may overlap the second impurity region.Type: GrantFiled: February 7, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jong-Cheol Shin
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Patent number: 8728856Abstract: A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.Type: GrantFiled: January 23, 2013Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventor: Federico Pio
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Patent number: 8698209Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.Type: GrantFiled: October 27, 2011Date of Patent: April 15, 2014Assignee: Micron Technology, Inc.Inventor: Jun Liu
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Patent number: 8692379Abstract: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.Type: GrantFiled: August 24, 2012Date of Patent: April 8, 2014Assignee: Macronix International Co., Ltd.Inventor: Shih-Hung Chen
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Patent number: 8686482Abstract: A CIS and a method of manufacturing the same, the CIS including a substrate having a first surface and second surface opposite thereto, the substrate including an APS array region including a photoelectric transformation element and a peripheral circuit region; an insulating interlayer on the first surface of the substrate and including metal wirings electrically connected to the photoelectric transformation element; a light blocking layer on the peripheral circuit region of the second surface of the substrate, exposing the APS array region, and including a plurality of metal wiring patterns spaced apart from one another to form at least one drainage path along a boundary region between the APS array region and the peripheral circuit region; a color filter layer on the second surface of the substrate covering the APS array region and the light blocking layer; and a microlens on the color filter layer on the APS array region.Type: GrantFiled: November 5, 2010Date of Patent: April 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Yun-Ki Lee
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Patent number: 8680500Abstract: A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.Type: GrantFiled: June 13, 2012Date of Patent: March 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Byoung-Jae Bae, Dong-Hyun Im, Doo-Hwan Park
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Patent number: 8674334Abstract: A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer.Type: GrantFiled: May 8, 2013Date of Patent: March 18, 2014Assignee: Micron Technology, Inc.Inventor: Jun Liu
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Patent number: 8637910Abstract: An image sensor includes an active region including a photoelectric conversion region and a floating diffusion region, which are separated from each other, defined by a device isolation region on a semiconductor substrate, and a transfer transistor including a first sub-gate provided on an upper surface of the semiconductor substrate and a second sub-gate extending within a recessed portion of the semiconductor substrate on the active region between the photoelectric conversion region and the floating diffusion region, wherein the photoelectric conversion region includes a plurality of photoelectric conversion elements, which vertically overlap each other within the semiconductor substrate and are spaced apart from the recessed portion.Type: GrantFiled: November 5, 2010Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Junemo Koo, Ihara Hisanori, Yoondong Park, HoonSang Oh, Sangjun Choi, HyungJin Bae, Tae Eung Yoon, Sungkwon Hong
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Patent number: 8624331Abstract: A non-volatile memory device includes: at least one horizontal electrode; at least one vertical electrode disposed to intersect the at least one horizontal electrode at an intersection region; at least one data layer disposed at the intersection region and having a conduction-insulation transition property; and at least one anti-fuse layer connected in series with the at least one data layer.Type: GrantFiled: March 16, 2010Date of Patent: January 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Deok-kee Kim, Choong-rae Cho
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Patent number: 8574991Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.Type: GrantFiled: March 12, 2012Date of Patent: November 5, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
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Patent number: 8445887Abstract: A nonvolatile programmable switch device using a phase-change memory device and a method of manufacturing the same are provided. The switch device includes a substrate, a first metal electrode layer disposed on the substrate and including a plurality of terminals, a phase-change material layer disposed on the substrate and having a self-heating channel structure, the phase-change material layer having a plurality of introduction regions electrically contacting the terminals of the first metal electrode layer and a channel region interposed between the introduction regions, an insulating layer disposed on the first metal electrode layer and the phase-change material layer, a via hole disposed on the first metal electrode layer, and a second metal electrode layer disposed to fill the via hole.Type: GrantFiled: April 23, 2009Date of Patent: May 21, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Min Yoon, Byoung Gon Yu, Soon Won Jung, Seung Yun Lee, Young Sam Park, Joon Suk Lee
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Patent number: 8384135Abstract: A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.Type: GrantFiled: June 20, 2011Date of Patent: February 26, 2013Assignee: SK hynix Inc.Inventors: Cheol Hwi Ryu, Hyung Soon Park, Jong Han Shin, Jum Yong Park, Sung Jun Kim
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Patent number: 8372680Abstract: Medical imaging devices may comprise an array of ultrasonic transducer elements. Each transducer element may comprise a substrate having a doped surface creating a highly conducting surface layer, a layer of thermal oxide on the substrate, a layer of silicon nitride on the layer of thermal oxide, a layer of silicon dioxide on the layer of silicon nitride, and a layer of conducting thin film on the layer of silicon dioxide. The layers of silicon dioxide and thermal oxide may sandwich the layer of silicon nitride, and the layer of conducting thin film may be separated from the layer of silicon nitride by the layer of silicon dioxide.Type: GrantFiled: March 12, 2007Date of Patent: February 12, 2013Assignee: STC.UNMInventor: Jingkuang Chen
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Patent number: 8362576Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).Type: GrantFiled: January 14, 2011Date of Patent: January 29, 2013Assignee: Round Rock Research, LLCInventors: Shuang Meng, Garo J. Derderian, Gurtej S. Sandhu
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Patent number: 8361824Abstract: A lens forming method according to the present invention for forming lenses capable of focusing light on a plurality of respective photoelectric conversion sections constituting of a semiconductor apparatus is described. The method includes a lens forming step of processing a lens forming material, in which an average gradient of a ? curve indicating a residual film thickness with respect to the amount of irradiation light is between ?15 and ?0.8 nm·cm2/mJ within the range of a residual film ratio of 10 to 50% or within the range of the amount of irradiation light of 55 to 137 mJ/cm2 into a lens surface shape, using a photomask with an optical transmittance that is varied according to a lens surface shape, as an exposure mask.Type: GrantFiled: May 5, 2010Date of Patent: January 29, 2013Assignee: Sharp Kabushiki KaishaInventor: Junichi Nakai
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Patent number: 8361833Abstract: A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.Type: GrantFiled: November 22, 2010Date of Patent: January 29, 2013Assignee: Micron Technology, Inc.Inventor: Federico Pio
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Patent number: 8319291Abstract: Provided is a non-volatile memory device including at least one horizontal electrode, at least one vertical electrode, at least one data storage layer and at least one reaction prevention layer. The least one vertical electrode crosses the at least one horizontal electrode. The at least one data storage layer is located in regions in which the at least one vertical electrode crosses the at least one horizontal electrode, and stores data by varying its electrical resistance. The at least one reaction prevention layer is located in the regions in which the at least one vertical electrode crosses the at least one horizontal electrode.Type: GrantFiled: September 11, 2009Date of Patent: November 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Deok-kee Kim, June-mo Koo, Ju-chul Park, Kyoung-won Na, Dong-seok Suh, Bum-seok Seo, Yoon-dong Park
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Patent number: 8293600Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on and in contact with the second electrode layer.Type: GrantFiled: December 6, 2011Date of Patent: October 23, 2012Assignee: Macronix International Co., Ltd.Inventor: Shih-Hung Chen
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Patent number: 8222075Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.Type: GrantFiled: March 17, 2009Date of Patent: July 17, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Eiji Ito
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Patent number: 8188833Abstract: A variable resistance element capable of increasing stability of a resistance changing operation and reducing a current necessary for changing, to a low resistance state for the first time, the variable resistance element in an initial state immediately after manufacture. The variable resistance element includes: a first electrode (101); a memory cell hole (150) formed above the first electrode (101); a first variable resistance layer (201) covering a bottom of the memory cell hole (150) and an upper surface of the first electrode (101); a second variable resistance layer (202) formed on the first variable resistance layer (201); and a second electrode (102) formed on the memory cell hole (150), in which a thickness of the first variable resistance layer (201) at the bottom of the memory cell hole (150) gradually decreases toward an edge area of the memory cell hole (150) and has a local minimum value around the edge area of the memory cell hole (150).Type: GrantFiled: April 14, 2010Date of Patent: May 29, 2012Assignee: Panasonic CorporationInventor: Kiyotaka Tsuji
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Patent number: 8158482Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.Type: GrantFiled: September 2, 2009Date of Patent: April 17, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
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Patent number: 8143089Abstract: A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers.Type: GrantFiled: October 7, 2010Date of Patent: March 27, 2012Assignee: Macronix International Co., Ltd.Inventor: Hsiang-Lan Lung
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Patent number: 8125006Abstract: An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.Type: GrantFiled: August 8, 2008Date of Patent: February 28, 2012Assignee: Qimonda AGInventors: Ulrike Gruening-von Schwerin, Peter Baars, Klaus Muemmler, Stefan Tegen, Thomas Happ
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Patent number: 8115239Abstract: The electric device according to the invention has a resistor comprising a layer of a phase change material which is changeable between a first phase with a first electrical resistivity and a second phase with a second electrical resistivity different from the first electrical resistivity. The phase change material is a fast growth material. The electric device further comprises a switching signal generator for switching the resistor between at least three different electrical resistance values by changing a corresponding portion of the layer of the phase change material from the first phase to the second phase.Type: GrantFiled: March 16, 2005Date of Patent: February 14, 2012Assignee: NXP B.V.Inventors: Martijn Henri Richard Lankhorst, Erwin Rinaldo Meinders, Robertus Adrianus Maria Wolters, Franciscus Petrus Widdershoven
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Patent number: 8093632Abstract: A phase change memory device includes a silicon substrate including a plurality of active regions which extend in a first direction and are arranged at regular intervals in a second direction perpendicular to the first direction. Switching elements are formed in each active region of the silicon substrate and are spaced apart from one another. Phase change patterns are formed in the second direction and have the shape of lines in such that the phase change patterns connect side surfaces of pairs of switching elements which are placed adjacent to each other in a direction diagonal to the first direction.Type: GrantFiled: September 16, 2008Date of Patent: January 10, 2012Assignee: Hynix Semiconductor Inc.Inventor: Heon Yong Chang
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Patent number: 8084842Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on the second electrode layer.Type: GrantFiled: March 25, 2008Date of Patent: December 27, 2011Assignee: Macronix International Co., Ltd.Inventor: Shih-Hung Chen
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Patent number: 8058702Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.Type: GrantFiled: October 26, 2006Date of Patent: November 15, 2011Assignees: Nanya Technology Corporation, Winbond Electronics Corp.Inventor: Te-Sheng Chao
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Patent number: 8013318Abstract: A phase change random access memory for actively removing residual heat and a method of manufacturing the same are presented. The phase change random access memory includes a semiconductor substrate, a phase change pattern, a heating electrode and a cooling electrode. The phase change pattern is on the semiconductor substrate. The heating electrode is electrically coupled to the phase change pattern for heating the phase change pattern. The cooling electrode is electrically coupled to the phase change pattern for removing residual heat from the phase change pattern.Type: GrantFiled: June 30, 2009Date of Patent: September 6, 2011Assignee: Hynix Semiconductor Inc.Inventor: Dae Ho Rho
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Patent number: 7993961Abstract: A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.Type: GrantFiled: July 27, 2009Date of Patent: August 9, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Rok Oh, Sang-Beom Kang, Du-Eung Kim
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Patent number: 7952121Abstract: An image sensor includes a charge storage portion for storing and transferring signal charges, a first electrode for forming an electric field storing the signal charges in the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion and a second electrode for forming another electric field increasing the signal charges in the charge increasing portion, wherein the quantity of the signal charges storable in the charge storage portion is not less than the quantity of the signal charges storable in the charge increasing portion.Type: GrantFiled: August 25, 2008Date of Patent: May 31, 2011Assignee: Sanyo Electric Co., Ltd.Inventors: Mamoru Arimoto, Hayato Nakashima, Kaori Misawa, Ryu Shimizu
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Patent number: 7897969Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.Type: GrantFiled: April 18, 2006Date of Patent: March 1, 2011Assignee: Sony CorporationInventors: Yoshinori Muramatsu, Takahiro Abiru, Takaichi Hirata