Combined With Insulated Gate Field Effect Transistor (igfet) Patents (Class 257/262)
  • Patent number: 10361188
    Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez
  • Patent number: 10283639
    Abstract: A semiconductor structure includes a substrate, a first fin structure disposed over the substrate, a second fin structure disposed over the substrate, and an isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure. The isolation structure includes a first thickness, a second thickness and a third thickness different from each other.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Yu-Lin Yang, Jung-Piao Chiu, Tzu-Chiang Chen
  • Patent number: 10217864
    Abstract: A semiconductor structure includes a substrate and a vertical FinFET disposed over the substrate. The vertical FinFET includes: a bottom source/drain (S/D) region disposed over the substrate, a fin extending vertically upwards from the bottom S/D region, the fin having a first (1st) sidewall, a second (2nd) sidewall and a top portion, an upper S/D region disposed over the top portion of the fin, the fin defining a channel between the bottom S/D region and the upper S/D region, a 1st gate structure having a 1st metal gate, the 1st gate structure disposed on the 1st sidewall of the fin, and a 2nd gate structure having a 2nd metal gate, the 2nd gate structure disposed on the 2nd sidewall of the fin. The 1st and 2nd metal gates are electrically isolated from each other by the fin.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Josef Watts
  • Patent number: 10186574
    Abstract: A super junction MOSFET device including a semiconductor substrate; a base region provided on a primary surface side of the semiconductor substrate and having impurities of a first conductivity type; a source region that includes a portion of a frontmost surface of the base region and has impurities of a second conductivity type; a gate electrode that penetrates through the base region; a source electrode that is provided on the base region and is electrically connected to the source region; and a front surface region that is provided on an entirety of the frontmost surface of the base region in a region differing from a region where the source region and the gate electrode are provided in the base region, is electrically connected to the source electrode provided on the base region, and has a lower impurity concentration of impurities of the second conductivity type than the source region.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: January 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru Shirakawa, Tatsuya Naito, Shigemi Miyazawa
  • Patent number: 10177234
    Abstract: A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 8, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nariaki Tanaka, Tohru Oka
  • Patent number: 10109708
    Abstract: A semiconductor device and methods of formation are provided herein. A semiconductor device includes a conductor concentrically surrounding an insulator, and the insulator concentrically surrounding a column. The conductor, the insulator and the conductor are alternately configured to be a transistor, a resistor, or a capacitor. The column also functions as a via to send signals from a first layer to a second layer of the semiconductor device. The combination of via and at least one of a transistor, a capacitor, or a resistor in a semiconductor device decreases an area penalty as compared to a semiconductor device that has vias formed separately from at least one of a transistor, a capacitor, or resistor.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Cheng-Wei Luo, Hsiao-Tsung Yen
  • Patent number: 9853026
    Abstract: A transistor device may include a substrate that has a well portion. The transistor device may further include a source member and a drain member. The transistor device may further include a fin bar. The fin bar may be formed of a first semiconductor material, may be disposed between the source member and the drain member, and may overlap the well portion. The transistor device may further include a fin layer. The fin layer may be formed of a second semiconductor material, may be disposed between the source member and the drain member, and may contact the fin bar.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: December 26, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: De Yuan Xiao
  • Patent number: 9842917
    Abstract: Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 12, 2017
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 9831327
    Abstract: Electrostatic discharge (ESD) protection devices and methods. The ESD protection devices include a semiconductor substrate, a buried semiconducting layer, and an overlying semiconducting layer. The ESD protection devices also include a first bipolar device that includes a first bipolar device region, a first device base region, and a first device emitter region. The ESD protection devices also include a second bipolar device that includes a second bipolar device region, a second device well, a second device base region, and a second device emitter region. The ESD protection devices further include a sinker well that electrically separates the first bipolar device from the second bipolar device. The ESD protection devices are configured to transition from an off state to an on state responsive to receipt of greater than a threshold ESD voltage by the first device base region. The methods include methods of forming the ESD protection device.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 28, 2017
    Assignee: NXP USA, Inc.
    Inventor: Rouying Zhan
  • Patent number: 9825025
    Abstract: A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: November 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kumagai
  • Patent number: 9793392
    Abstract: A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p?-type region constituting an edge termination structure provided in the flat portion.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 17, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Masahito Otsuki
  • Patent number: 9754887
    Abstract: A semiconductor device includes a first power rail, a second power rail, at least one standard cell and at least one power bridge. The first power rail extends in a first direction over a substrate. The second power rail extends in the first direction over the substrate, and the second power rail is spaced apart from the first power rail in a second direction that intersects the first direction. The at least one standard cell receives a first voltage from the first and the second power rails. The at least one power bridge connects the first power rail and the second power rail in the second direction. The first power rail and the second power rail are formed in a first metal layer and the least one power bridge is formed in a bottom metal layer that is under the first metal layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min-Su Kim
  • Patent number: 9748393
    Abstract: It is an object of the present invention to provide a silicon carbide semiconductor device that reduces a channel resistance and increases reliability of a gate insulating film. The present invention includes a trench partially formed in a surface layer of an epitaxial layer, a well layer formed along side surfaces and a bottom surface of the trench, a source region formed in a surface layer of the well layer on the bottom surface of the trench, a gate insulating film, and a gate electrode. The gate insulating film is formed along the side surfaces of the trench and has one end formed so as to reach the source region. The gate electrode is formed along the side surfaces of the trench and formed on the gate insulating film.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 29, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoichiro Tarui
  • Patent number: 9741837
    Abstract: A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: August 22, 2017
    Assignees: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
    Inventors: Jinping Zhang, Yadong Shan, Gaochao Xu, Xin Yao, Jingxiu Liu, Zehong Li, Min Ren, Bo Zhang
  • Patent number: 9735263
    Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 15, 2017
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Ramakrishna Rao, Peter Almern Losee, Alexander Viktorovich Bolotnikov
  • Patent number: 9704953
    Abstract: According to one embodiment, a semiconductor device includes a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a gate electrode. An impurity concentration of the second conductivity type of the third semiconductor region is higher than an impurity concentration of the second conductivity type of the second semiconductor regions. The fourth semiconductor region is provided on the first semiconductor regions. The gate electrode provided on the fourth semiconductor region with a gate insulation layer interposed. The gate electrode extends in a third direction. The third direction intersects the first direction. The third direction is parallel to a plane including the first direction and the second direction.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: July 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hideyuki Ura, Masahiro Shimura
  • Patent number: 9653387
    Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 16, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Ali Salih
  • Patent number: 9653540
    Abstract: A method of manufacturing semiconductor devices in a semiconductor wafer comprises forming charge compensation device structures in the semiconductor wafer. An electric characteristic related to the charge compensation device structures is measured. At least one of proton irradiation and annealing parameters are adjusted based on the measured electric characteristic. The semiconductor wafer is irradiated with protons and annealed based on the at least one of the adjusted proton irradiation and annealing parameters. Laser beam irradiation parameters are adjusted with respect to different positions on the semiconductor wafer based on the measured electric characteristic. The semiconductor wafer is irradiated with a photon beam at the different positions on the wafer based on the photon beam irradiation parameters.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: May 16, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Wolfgang Jantscher, Hans-Joachim Schulze
  • Patent number: 9633994
    Abstract: A MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 9601614
    Abstract: A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: March 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Won Gi Min, Pete Rodriquez, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9590611
    Abstract: Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using structures configured to cooperatively control a common semi-conductive channel region (SCR). One embodiment includes providing a metal oxide semiconductor field effect transistor (MOSFET) section formed with an exemplary SCR and two junction field effect transistor (JFET) gates on opposing sides of the MOSFET's SCR such that operation of the JFET modulates or controls current through the MOSFET's. With two JFET gate terminals to modulate various embodiments' signal(s), an improved mixer, demodulator, and gain control element in, e.g., analog circuits can be realized. Additionally, a direct current (DC)-biased terminal of one embodiment decreases cross-talk with other devices. A lens structure can also be incorporated into MOSFET structures to further adjust operation of the MOSFET.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: March 7, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Patrick L. Cole, Adam R. Duncan
  • Patent number: 9343526
    Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 17, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9208279
    Abstract: A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a fourth transistor of the first transistor type. A fourth LCS forms a GE of a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. At least two of the electrical connection areas of the first, second, third, and fourth LCS's are located within the inner region. The first and fourth transistors of the first transistor type and the first and fourth transistors of the second transistor type form part of a cross-coupled transistor configuration.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: December 8, 2015
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Jim Mali, Carole Lambert
  • Patent number: 9184100
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: November 10, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Patent number: 9081931
    Abstract: A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 14, 2015
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Jim Mali, Carole Lambert
  • Patent number: 9064943
    Abstract: Disclosed are gate-all-around (GAA) field effect transistors (FETs) and methods of forming them. In one GAAFET, a semiconductor body is on an insulator layer. A gate wraps around the semiconductor body (i.e., is adjacent to the top, bottom and opposing sides of the semiconductor body) at a channel region with a lower portion of the gate being in a cavity in the insulator layer. In another GAAFET, multiple semiconductor bodies are on an insulator layer. A gate wraps around and extends between the semiconductor bodies at channel regions with a lower portion of the gate being contained in a cavity in the insulator layer. To reduce gate resistance and gate-to-source/drain contact capacitance, the lower portion extends a greater distance below the bottom(s) of the semiconductor body(ies) than the upper portion extends above the top(s). To further reduce gate resistance, the length and width of the lower portion increases from the top surface of the insulator layer downward.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Yan Zhang
  • Publication number: 20150115333
    Abstract: This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Inventors: Madhur Bobde, Anup Bhalla, Hamza Yilmaz, Wilson Ma, Lingpeng Guan, Yeeheng Lee, John Chen
  • Patent number: 9018685
    Abstract: The invention relates to a structure comprising an n-type substrate (1) having a bottom surface (10) and a top surface (11), a drain (D) contacting the bottom surface (10) of the substrate (1), a first n-type semiconductor region (2) having a top surface (21) provided with a contact area (210), a source (S) contacting the contact area (210), and a second p-type semiconductor region (3) arranged inside the first semiconductor region (2) and defining first and second conduction channels (C1, C2) between the drain and the source, characterized in that said structure comprises first and second metal gratings (G1, G2), each of which has a portion (40, 71) contacting the first semiconductor region (2) so as to form a Schottky junction.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 28, 2015
    Assignees: Institut National des Sciences Appliquees de Lyon, Centre National de la Recherche Scientifique
    Inventors: Dominique Tournier, Pierre Brosselard, Florian Chevalier
  • Patent number: 9012280
    Abstract: According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Uwe Wahl
  • Patent number: 8969925
    Abstract: A semiconductor device includes a substrate, a body region adjoining the substrate surface, a source contact region within the body region, a drain contact region adjoining the substrate surface and being separated from the body region, a dual JFET gate region located between the body region and the drain contact region, and a lateral JFET channel region adjoining the surface of the substrate and located between the body and the drain contact regions. A vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the enclosed vertical JFET gate and the dual JFET gate regions, a reduced drain resistance region being arranged between the dual JFET gate and the drain contact regions, and a buried pocket located under part of the body region, under the dual JFET gate region and under the vertical JFET channel and reduced drain resistance regions.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: March 3, 2015
    Assignee: K.Eklund Innovation
    Inventors: Klas-Hakan Eklund, Lars Vestling
  • Publication number: 20150054038
    Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 26, 2015
    Inventors: Denis A. Masliah, Alexandre G. Bracale
  • Patent number: 8963217
    Abstract: In one embodiment, a wafer structure configured for a power device can include: (i) a first doping layer having a high doping concentration; (ii) a second doping layer on the first doping layer, where a doping concentration of the second doping layer is less than the high doping concentration; and (iii) a third doping layer on the second doping layer, where a doping concentration of the third doping layer is greater than the doping concentration of the second doping layer. For example, the power device can be part of a switching voltage regulator.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: February 24, 2015
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd
    Inventor: Zhongping Liao
  • Patent number: 8946779
    Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, James A. Teplik
  • Patent number: 8929090
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 6, 2015
    Assignee: NEC Corporation
    Inventors: Yoshiki Nakashima, Shintaro Yamamichi, Katsumi Kikuchi, Kentaro Mori, Hideya Murai
  • Patent number: 8928087
    Abstract: A semiconductor device is equipped with an element region, an electrode, a thermal conduction portion, and a protective membrane. The element region is equipped with a plurality of gate electrodes. The electrode is formed on a surface of the element region. The thermal conduction portion is located on a surface side of a central portion of the electrode, and is higher in thermal conductivity than the element region. The protective membrane is formed on a peripheral portion that is located on the surface side of the electrode and surrounds a periphery of the central portion. In the element region, an emitter central region that is formed on a back side of the central portion of the electrode remains on for a longer time than an emitter peripheral region that is formed on a back side of the peripheral portion of the electrode.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: January 6, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tadashi Misumi
  • Patent number: 8912573
    Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8901623
    Abstract: According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Uwe Wahl
  • Patent number: 8865530
    Abstract: A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8829573
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: September 9, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20140231829
    Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.
    Type: Application
    Filed: September 30, 2011
    Publication date: August 21, 2014
    Inventors: Takamitsu Kanazawa, Satoru Akiyama
  • Patent number: 8810040
    Abstract: A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kentaro Kaneko, Kazuhiro Kobayashi
  • Patent number: 8803241
    Abstract: The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr-Jung Lin, Chih-Han Lin, Ming-Ching Chang
  • Patent number: 8803205
    Abstract: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Hans Weber, Michael Treu
  • Patent number: 8785988
    Abstract: A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: July 22, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Wing-Chor Chan, Li-Fan Chen, Chen-Yuan Lin
  • Patent number: 8785987
    Abstract: An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, —an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, —a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 22, 2014
    Assignee: Acco
    Inventor: Denis Masliah
  • Publication number: 20140197466
    Abstract: A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.
    Type: Application
    Filed: January 11, 2013
    Publication date: July 17, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD
    Inventors: Wing-Chor Chan, Li-Fan Chen, Chen-Yuan Lin
  • Patent number: 8766367
    Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street
  • Patent number: 8736069
    Abstract: A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 27, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chiajung Chiu, Guanru Lee
  • Publication number: 20140117415
    Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 1, 2014
    Applicant: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Rongyao Ma, Tiesheng Li, Lei Zhang, Daping Fu