Junction Field Effect Transistor In Integrated Circuit Patents (Class 257/272)
  • Patent number: 7420232
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: September 2, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 7417266
    Abstract: A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: August 26, 2008
    Assignee: QSpeed Semiconductor Inc.
    Inventors: Jian Li, Daniel Chang, Ho-Yuan Yu
  • Patent number: 7411231
    Abstract: The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: August 12, 2008
    Assignee: Analog Devices, Inc.
    Inventors: Craig Wilson, Derek Bowers, Gregory K. Cestra
  • Patent number: 7378688
    Abstract: A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from one another in a second direction surrounding a portion of the channel to allow for application and removal of a gate voltage. Application of the gate voltage repels majority carriers in the channel to reduce the current that conducts between the source and drain.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventor: Dominik J. Schmidt
  • Publication number: 20080099798
    Abstract: A junction field effect transistor (JFET) device is disclosed for amplifying an input signal. The JFET device includes a first gate region and a substrate/well/bulk region that may form a second gate region. The JFET device also includes a first source/drain region and a second source/drain region. The first source/drain region may receive an input signal and either the first gate region or the second gate region may provide an amplified output signal. A current supplied across the channel region may be substantially independent of a current supplied between the gate region and a bulk region of the substrate. The device may be configured to amplify a time varying input signal to provide an amplified time varying output signal.
    Type: Application
    Filed: October 3, 2007
    Publication date: May 1, 2008
    Inventor: Douglas Kerns
  • Publication number: 20080074908
    Abstract: A depletion mode transistor serving as a start-up control element is provided. The depletion mode transistor includes a first depletion mode junction transistor and a second depletion mode transistor. The first depletion mode junction transistor includes a source and a drain, one of which is coupled to a voltage supply source, and a gate electrically coupled to ground. The second depletion mode transistor includes a source and a drain, one of which is coupled to the other one of the source and the drain of the first depletion mode junction transistor, and a gate being controllable to turn OFF the second depletion mode transistor.
    Type: Application
    Filed: March 5, 2007
    Publication date: March 27, 2008
    Inventors: Kuang-Ming Chang, Shien-Hsing Cheng
  • Publication number: 20080073675
    Abstract: A transistor having a start-up control element is provided. The transistor includes an N-type depletion mode transistor and an N-type enhancement mode transistor. The N-type depletion mode transistor includes a drain for electrically connecting to an external power supply, and a gate normally grounded. The N-type enhancement mode transistor includes a drain electrically connected to the external power supply, and a gate electrically connected to a source of the depletion mode transistor.
    Type: Application
    Filed: January 24, 2007
    Publication date: March 27, 2008
    Inventors: Chien-Hsing Cheng, Kuang-Ming Chang
  • Patent number: 7335952
    Abstract: To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method for the semiconductor device, an n-type silicon layer is deposited on a p-type silicon substrate by epitaxial growth, and then an SOI layer is deposited thereon through the intermediary of a BOX layer. A junction transistor using a part of the n-type silicon layer as a channel region and a MOS transistor using the SOI layer are produced.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: February 26, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroyuki Tanaka
  • Patent number: 7312481
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: December 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • Patent number: 7253071
    Abstract: Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer process, a strain compensating dielectric capping layer process during silicide formation, a two cycle anneal process during silicide formation, an excess nickel process to transform NiSi2 to NiSi.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: August 7, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Tan-Chen Lee
  • Patent number: 7238976
    Abstract: A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second doped region is disposed between the first doped region and the first conductive layer. The plurality of third doped regions are disposed in the second doped region. The first doped region of the semiconductor is heavily doped with a first type of dopant (e.g., phosphorous or arsenic). The second doped region is moderately doped with the first type of dopant. The plurality of third doped regions are moderately to heavily doped with a second type of dopant.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: July 3, 2007
    Assignee: QSpeed Semiconductor Inc.
    Inventors: Ho-Yuan Yu, Chong-Ming Lin
  • Patent number: 7227203
    Abstract: A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23,24).
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: June 5, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Josef Halamik, Jefferson W. Hall
  • Patent number: 7049644
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: May 23, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 6960797
    Abstract: The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 1000˜5,000 ?·cm.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 1, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeaki Okawa, Toshiyuki Ohkoda
  • Patent number: 6927460
    Abstract: A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: August 9, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Steven M. Leibiger, Ronald B. Hulfachor, Michael Harley-Stead, Daniel J. Hahn
  • Patent number: 6906359
    Abstract: According to one exemplary embodiment, a BiFET situated on a substrate comprises an emitter layer segment situated over the substrate, where the emitter layer segment comprises a semiconductor of a first type. The HBT further comprises a first segment of an etch stop layer, where the first segment of the etch stop layer comprises InGaP. The BiFET further comprises a FET situated over the substrate, where the FET comprises source and drain regions, where a second segment of the etch stop layer is situated under the source and drain regions, and where the second segment of the etch stop layer comprises InGaP. The FET further comprises a semiconductor layer of a second type situated under the second segment of the etch stop layer. The etch stop layer increases linearity of the FET and does not degrade electron current flow in the HBT.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: June 14, 2005
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Richard Pierson
  • Patent number: 6903426
    Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 ?m and a signal receiving FET has a gate width of 400 ?m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 7, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Toshikazu Hirai, Mikito Sakakibara
  • Patent number: 6900482
    Abstract: A high-frequency semiconductor device for power amplification has a comb-teeth electrode on each of active regions formed on the front surface of the semiconductor substrate. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a plurality of rectangular-shaped active regions arranged side by side on the front surface of the semiconductor substrate, each of the active regions having interdigited gate, drain and source electrodes thereon which are connected to the respective pads by multilayer interconnection technique. Additionally, the source potential is fed from the back surface of the substrate through a metal plugged via-hole.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: May 31, 2005
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Yoshio Aoki, Yutaka Mimino, Osamu Baba, Muneharu Gotoh
  • Patent number: 6885078
    Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: April 26, 2005
    Assignee: LSI Logic Corporation
    Inventors: Donald M. Bartlett, Gayle W. Miller, Randall J. Mason
  • Patent number: 6777722
    Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: August 17, 2004
    Assignee: Lovoltech, Inc.
    Inventors: Ho-Yuan Yu, Valentino L. Liva, Pete Pegler
  • Patent number: 6768143
    Abstract: An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: July 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gregory J. Fredeman, John W. Golz, David R. Hanson, Hoki Kim
  • Publication number: 20040110345
    Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.
    Type: Application
    Filed: November 26, 2003
    Publication date: June 10, 2004
    Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
  • Publication number: 20040061151
    Abstract: A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includes a first junction, formed between the first semiconducting structure and the substrate, having an area wherein at least one lateral dimension is less than about 75 nanometers.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Inventors: James Stasiak, Jennifer Wu, David E. Hackleman
  • Patent number: 6710426
    Abstract: A field effect transistor (FET) is formed on a semiconductor substrate. A drain terminal, a source terminal, and a gate terminal connected to the FET are also formed on the semiconductor substrate. In an embodiment of the invention, a metal insulator metal (MIM) capacitor for blocking a bias current is disposed between the FET and the drain terminal. A bias terminal is provided between the MIM capacitor and the FET. Passive circuits connected to the drain terminal, the source terminal, and the gate terminal, and a bias circuit connected to the bias terminal are formed on a dielectric substrate. With this arrangement, the circuitry on the semiconductor substrate can be simplified. The general versatility of a resulting semiconductor device can be increased, and the size of the semiconductor device can be reduced.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: March 23, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Motoyasu Nakao, Akihiro Sasabata
  • Patent number: 6690040
    Abstract: A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is disposed over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: February 10, 2004
    Assignee: Agere Systems Inc.
    Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
  • Patent number: 6661056
    Abstract: The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor. A charge carrier zone (30) is provided, situated in the drift zone (14) of DMOS transistor (10), made up of individual partial charge carrier zones (32) situated at a distance from one another and connected to one another in a conducting manner, the charge carrier zone (30) having an opposite charge carrier doping from that of the drift zone (14), and being able to be acted upon by a potential that is negative with respect to a potential present at a drain terminal (24) of the DMOS transistor (10), so that a short-circuit current is prevented.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: December 9, 2003
    Assignee: Robert Bosch GmbH
    Inventors: Robert Plikat, Wolfgang Feiler
  • Patent number: 6627973
    Abstract: A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: September 30, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Robert A. Huertas, Lu You, King Wai Kelwin Ko, Pei-Yuan Gao
  • Patent number: 6555857
    Abstract: The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 1000˜5,000 &OHgr;·cm.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: April 29, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeaki Okawa, Toshiyuki Ohkoda
  • Patent number: 6534807
    Abstract: A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: March 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Dong Gan, Chung H. Lam
  • Publication number: 20030047749
    Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.
    Type: Application
    Filed: September 10, 2001
    Publication date: March 13, 2003
    Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
  • Patent number: 6501110
    Abstract: A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: December 31, 2002
    Assignee: Sony Corporation
    Inventors: Mikio Mukai, Toshio Kobayashi, Yutaka Hayashi
  • Patent number: 6476430
    Abstract: In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain regions, which operation is performed jointly with the LDD implantation. The halo implant, however, decreases the analog performance of transistors. To combine suppression of short-channel effects with a high analog performance, it is proposed to provide only transistors T1, which are not intended for analog functions with the halo implant (16), and to mask the analog transistors T2 with a mask (15) against the halo implant. To avoid short-channel effects in T2, this transistor is provided with a channel whose length is larger than that of transistor T1.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: November 5, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jurriaan Schmitz, Andreas H. Montree
  • Patent number: 6465830
    Abstract: A voltage controlled capacitor sandwiched between a buried oxide and a shallow trench insulator to form a near ideal P+ to n-well diode with minimal parasitic capacitance and resistance.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: October 15, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Gregory E. Howard, Angelo Pinto
  • Patent number: 6347050
    Abstract: A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: February 12, 2002
    Assignee: Sony Corporation
    Inventors: Mikio Mukai, Yutaka Hayashi
  • Patent number: 6313489
    Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by a surface insulation region.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: November 6, 2001
    Assignee: Philips Electronics North America Corporation
    Inventors: Theodore Letavic, Mark Simpson, Richard Egloff, Andrew Mark Warwick
  • Patent number: 6307223
    Abstract: Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally “off” JFETs, one in N-channel and one in P-channel to form Complementary Junction Field Effect Transistors for high speed, low voltage and/or high current applications. The discrete device structure is disclosed in this invention. The integrated Complementary Junction Field Effect Transistors structure processed in standard CMOS process is disclosed in this invention. A vertical gate structure of Complementary Junction Field Effect Transistors is disclosed. Complementary Junction Field Effect Transistors structure is also disclosed in SOI substrate.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: October 23, 2001
    Assignee: Lovoltech, Inc.
    Inventor: Ho-yuan Yu
  • Patent number: 6255710
    Abstract: An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material. The high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: July 3, 2001
    Assignee: Motorola, Inc.
    Inventors: Charles E. Weitzel, Nada El-Zein
  • Patent number: 6160280
    Abstract: A field effect transistor structure which can serve as a low noise amplifier. The field effect transistor has a major surface and source and drain regions extending from the major surface into a body of semiconductor material. A channel region is formed in a portion of the body of semiconductor material separating the source and drain regions. The channel region has a first boundary perpendicular to the major and contiguous with the source region, a second boundary parallel to the first boundary and contiguous with the drain region, a third boundary perpendicular to the first boundary, and a fourth boundary parallel to the channel region. A first portion of the channel region is enclosed by a first border parallel to the first boundary of the channel region, a second border parallel to the second boundary of the channel region, a third boundary of the channel region, and the fourth boundary of the channel region.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: December 12, 2000
    Assignee: Motorola, Inc.
    Inventors: Fred H. Bonn, George B. Norris, John Michael Golio
  • Patent number: 6153453
    Abstract: The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-type channel region at the same time as lightly-doped drain/source regions of the P-channel MOS transistors of; forming an N-type gate region at the same time as lightly-doped drain/source regions of the N-channel MOS transistors; and forming P-type drain/source regions at the same time as heavily-doped drain/source regions of P-channel MOS transistors of channel.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: November 28, 2000
    Assignee: STMicroelectronics S.A.
    Inventor: Jean Jimenez
  • Patent number: 6104048
    Abstract: An electrostatic protection network is disclosed that may be employed in a disk drive having a magneto-resistive read element. The network comprises a ground; and an array that block a signal current flow between the read element and the ground while a signal voltage is below a predetermined value and conducts the signal current from the read element to the ground while the signal voltage is above the predetermined value. The array is formed of a N-channel and P-channel junction field effect transistors. Thus, electrostatic discharge events are dissipated through the network to diminish damage to the read element during an ESD event.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: August 15, 2000
    Assignee: Iomega Corporation
    Inventors: Wenwei Wang, Larry Trung Vo
  • Patent number: 6097046
    Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: August 1, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Donald L. Plumton
  • Patent number: 6084274
    Abstract: A semiconductor memory cell includes a read-out transistor of a first conductivity type which has source/drain regions constituted by a second conductive region and a third semiconducting region, a channel forming region constituted by a surface region of a second semiconducting region, and a conductive gate formed on a barrier layer; a switching transistor of a second conductivity type which has source/drain regions constituted by a first conductive region and the second semiconducting region, a channel forming region constituted by a surface region of a first semiconducting region, and a conductive gate formed on a barrier layer; and a current controlling junction-field-effect transistor of a first conductivity type which has gate regions constituted by a third conductive region and a portion of the second semiconducting region, a channel region constituted by a portion of the third semiconducting region, and one source/drain region extended from one end of the channel region, being constituted by a portion
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: July 4, 2000
    Assignee: Sony Corporation
    Inventors: Mikio Mukai, Yutaka Hayashi, Yasutoshi Komatsu
  • Patent number: 6005284
    Abstract: A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si substrate, the sheet resistance of the polycrystalline Si film forming the base outlet electrode of the npn transistor is decreased to two thirds of the sheet resistance of the polycrystalline Si film forming at least one electrode of at least one other device. The base outlet electrode can be made by first making the polycrystalline Si film on the entire surface of the substrate, then applying selective ion implantation of Si to a selective portion of the polycrystalline Si film for making the base outlet electrode to change it into an amorphous state, and then annealing the product to grow the polycrystalline Si film by solid-phase growth.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: December 21, 1999
    Assignee: Sony Corporation
    Inventors: Hirokazu Ejiri, Hiroyuki Miwa, Hiroaki Ammo
  • Patent number: 5945699
    Abstract: A load device for an MOS transistor, such as that of a memory cell, includes a differentially doped vertical JFET structure that contains two separate and distinct opposite conductivity type regions. The interior region has the same conductivity as the well in which the JFET is formed, and is surrounded by the JFET channel region which has a generally annular shape. The pinch-off voltage of the annular vertical JFET channel is established by its cross-sectional thickness and doping profile. This reduced thickness, annular-shaped, vertical JFET channel provides a limited current flow path that can be very precisely tailored to restrict current flow to what is essentially a leakage current path, and thereby provide a very high load impedance.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: August 31, 1999
    Assignee: Harris Corporation
    Inventor: William R. Young
  • Patent number: 5929502
    Abstract: A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: July 27, 1999
    Assignee: Harris Corporation
    Inventor: James D. Beasom
  • Patent number: 5929503
    Abstract: A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: July 27, 1999
    Assignee: Harris Corporation
    Inventor: James D. Beasom
  • Patent number: 5914508
    Abstract: A microwave system encapsulated by two layers. The first layer is an arylcyclobutene polymer having a thickness greater than the tallest component of the system and only located in predetermined areas. Overlaying the polymer and other preselected areas of the system is a ceramic glass material. These two layers are applied in two layers coating process steps.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: June 22, 1999
    Assignee: The Whitaker Corporation
    Inventors: Costas D. Varmazis, Anthony Kaleta
  • Patent number: 5907168
    Abstract: A Germanium junction field effect transistor (Ge-JFET) is fabricated in a manner to produce low noise and which is particularly suitable for a cryogenic detector. The Ge-JFET in accordance with the present invention comprises a germanium base material on which a phosphorous implanted channel region is implanted thereon. A boron cap layer overlies the channel region. On the cap layer are separately spaced drain and source ohmic contact regions, and a gate ohmic contact region therebetween. The drain and source ohmic contact regions are separately spaced arsenic implant regions and a phosphorous implant region. The gate ohmic contact region is a BF.sub.2 implanted region.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: May 25, 1999
    Assignee: TLC Precision Wafer Technology, Inc.
    Inventor: Timothy T. Childs
  • Patent number: 5747841
    Abstract: A circuit arrangement for comparatively high powers, for example, for gas discharge lamps is protected against high currents, which may be caused inter alia by inrush effects or transients, by a semiconductor current limiter element V. The current limiter element comprises a semiconductor body of substantially a given conductivity type, for example the n-type. The main electrodes are provided at the upper and the lower surface of the semiconductor body and comprise two metal electrodes which are connected to the semiconductor body via highly doped contact zones. The doping of the interposed region is such that current saturation occurs from a certain voltage upon a rise in voltage between the main electrodes. In a first embodiment, buried floating p-type zones are formed in the interposed region, so that the element is a junction field effect transistor with floating gate.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: May 5, 1998
    Assignee: U.S. Philips Corporation
    Inventor: Adrianus W. Ludikhuize
  • Patent number: 5708292
    Abstract: Variations in the waveform of high-frequency signals amplified by a field-effect transistor (FET) in a power amplification circuit due to changes in temperature are reduced. A FET having an n-type active layer, a source electrode, a drain electrode and a gate electrode is formed on a (1 0 0)-crystal plane of a semi-insulating GaAs substrate. The FET is protected by a passivation film. The angle .theta., formed between the longitudinal axial direction of the gate electrode and the <0 -1 -1>-direction, is set at an angle of from 0.degree. to 90.degree. corresponding to the impurity concentration of the n-type active layer, in order that the temperature coefficient of the FET threshold voltage becomes substantially equal to the temperature coefficient of the gate bias voltage applied from a power supply to the gate electrode. If the angle .theta. is set at 45.degree., then the temperature coefficient of the FET threshold voltage becomes zero.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: January 13, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Hidetoshi Furukawa, Daisuke Ueda