With Multiple Channels Or Channel Segments Connected In Parallel, Or With Channel Much Wider Than Length Between Source And Drain (e.g., Power Jfet) Patents (Class 257/287)
  • Patent number: 8823095
    Abstract: It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: September 2, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner
  • Patent number: 8816388
    Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Patent number: 8803247
    Abstract: A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Patent number: 8796697
    Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
  • Patent number: 8716078
    Abstract: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: May 6, 2014
    Assignee: Avogy, Inc.
    Inventors: Donald R. Disney, Richard J. Brown, Hui Nie
  • Patent number: 8710510
    Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: April 29, 2014
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal
  • Patent number: 8704279
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 8698229
    Abstract: Disclosed is a MOSFET including at least one transistor cell. The at least one transistor cell includes a source region, a drain region, a body region and a drift region. The body region is arranged between the source region and the drift region and the drift region is arranged between the body region and the drain region. The at least one transistor cell further includes a compensation region arranged in the drift region and distant to the body region, a source electrode electrically contacting the source region and the body region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a coupling arrangement including a control terminal. The coupling arrangement is configured to electrically couple the compensation region to at least one of the body region, the source region, the source electrode and the gate electrode dependent on a control signal received at the control terminal.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: April 15, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler
  • Patent number: 8674415
    Abstract: There is provided a high frequency semiconductor switch for improving insertion loss characteristics and harmonic characteristics by providing good voltage distribution in a gate wiring. The field effect transistor includes a source wiring electrically connected to a source region formed on a substrate and extending unidirectionally; a drain wiring electrically connected to a drain region formed on the substrate and extending in parallel with the source wiring; a gate having a parallel portion extending between the source wiring and the drain wiring in approximately parallel with the source wiring and the drain wiring; a gate wiring applying voltage to the gate; and a gate via electrically connecting the gate to the gate wiring, the parallel portion including two ends and formed with a path applying voltage to each of the two ends from the gate via.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Tsuyoshi Sugiura
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8642403
    Abstract: In one aspect, a method of forming contacts to source and drain regions in a FET device includes the following steps. A patternable dielectric is deposited onto the device so as to surround each of the source and drain regions. The patternable dielectric is exposed to cross-link portions of the patternable dielectric that surround the source and drain regions. Uncross-linked portions of the patternable dielectric are selectively removed relative to the cross-linked portions of the patternable dielectric, wherein the cross-linked portions of the patternable dielectric form dummy contacts that surround the source and drain regions. A planarizing dielectric is deposited onto the device around the dummy contacts. The dummy contacts are selectively removed to form vias in the planarizing dielectric which are then filled with a metal(s) so as to form replacement contacts that surround the source and drain regions.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Michael A. Guillorn
  • Patent number: 8604563
    Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: December 10, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshito Nakazawa, Yuji Yatsuda
  • Patent number: 8598027
    Abstract: A method for forming a semiconductor structure is disclosed. The method includes forming a high-k dielectric layer over a semiconductor substrate and forming a gate layer over the high-k dielectric layer. The method also includes heating the gate layer to 350° C., wherein, if the gate layer includes non-conductive material, the non-conductive material becomes conductive. The method further includes annealing the substrate, the high-k dielectric layer, and the gate layer in excess of 350° C. and, during the annealing, applying a negative electrical bias to the gate layer relative to the semiconductor substrate. A semiconductor structure is also disclosed. The semiconductor structure includes a high-k dielectric layer over a semiconductor substrate, and a gate layer over the high-k dielectric layer. The gate layer has a negative electrical bias during anneal. A p-channel FET including this semiconductor structure is also disclosed.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventor: Martin Michael Frank
  • Patent number: 8592920
    Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshito Nakazawa, Yuji Yatsuda
  • Patent number: 8546223
    Abstract: The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroki Arai, Nobuyuki Shirai, Tsuyoshi Kachi
  • Patent number: 8541833
    Abstract: A semiconductor component includes a sequence of layers, the sequence of layers including a first insulator layer, a first semiconductor layer disposed on the first insulator layer, a second insulator layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the second insulator layer. The semiconductor component also includes a plurality of devices at least partly formed in the first semiconductor layer. A first one of the plurality of devices is a power transistor formed in a first region of the first semiconductor layer and a first region of the second semiconductor layer. The first region of the first and second semiconductor layers are in electrical contact with one another through a first opening in the second insulator layer.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: September 24, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Helmut Strack, Franz Hirler
  • Patent number: 8541821
    Abstract: The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Shubneesh Batra, Gurtej Sandhu
  • Patent number: 8524552
    Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
  • Patent number: 8513675
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 20, 2013
    Assignee: Power Integrations, Inc.
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 8508047
    Abstract: An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: August 13, 2013
    Assignee: Spansion LLC
    Inventor: Michael Brennan
  • Patent number: 8481372
    Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20130134485
    Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 30, 2013
    Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION
    Inventors: Semiconductor Manufacturing International Corpor, Semiconductor Manufacturing International Corpor
  • Patent number: 8445348
    Abstract: The present invention discloses a manufacturing method of a semiconductor component with a nanowire channel. The method comprises the following steps. The step of forming a stack structure on a substrate is performed. A semiconductor layer is formed on the substrate and the stack structure and further filled into the fillister. The semiconductor layer is patterned to form a source area and a drain area, and the channel region is located between the source area and the drain area. The semiconductor layer located outside the source area, the drain area and the fillister will be removed. And then, the stack structure is then removed. Therefore, the semiconductor layer filled inside the fillister will be exposed to be as a channel. A gate oxide layer is formed to cover the channel, and a gate layer is then formed on the gate oxide layer.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: May 21, 2013
    Assignee: National Chiao Tung University
    Inventors: Po-Yi Kuo, Tien-Sheng Chao, Yi-Hsien Lu
  • Patent number: 8440512
    Abstract: The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: May 14, 2013
    Assignee: AGERE Systems Inc.
    Inventors: Kenneth G. Richardson, Michael Straub
  • Patent number: 8440542
    Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 14, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 8431973
    Abstract: A high frequency semiconductor device includes: a field effect transistor including gate terminal electrodes, source terminal electrodes, and a drain terminal electrode; an input circuit pattern and an output circuit pattern which are disposed adjoining of the field effect transistor; a plurality of input bonding wires configured to connect the plurality of the gate terminal electrodes and the input circuit pattern; and a plurality of output bonding wires configured to connect the drain terminal electrode and the output circuit pattern, which makes matching an input/output signal phase by adjusting an inductance distribution of a plurality of input/output bonding wires, and improves gain and output power, and suppresses an oscillation by unbalanced operation of each FET cell.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: April 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8431974
    Abstract: According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: April 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuma Suzuki, Hiroshi Kono, Takashi Shinohe
  • Patent number: 8421145
    Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: April 16, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kenji Hatori
  • Patent number: 8421129
    Abstract: A CNT channel layer of a transistor is cut along a direction perpendicular to the channel to form a plurality of CNT patches, which are used to connect between a source and a drain. The arrangement of the CNT channel layer formed of a plurality of CNT patches can increase the probability that part of CNT patches becomes a semiconductive CNT patch. Since part of a plurality of CNT patches forming the channel layer is formed of a semiconductive CNT patch, a transistor having a good on/off ratio can be provided.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: April 16, 2013
    Assignee: NEC Corporation
    Inventor: Masahiko Ishida
  • Patent number: 8399907
    Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 19, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee
  • Patent number: 8390059
    Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: March 5, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kenji Hatori
  • Patent number: 8377758
    Abstract: A thin film transistor for a thin film transistor liquid crystal display (TFT-LCD), an array substrate and manufacturing method thereof are provided. The thin film transistor comprises a source electrode, a drain electrode, and a channel region between the source electrode and drain electrode. A source extension region is connected with the source electrode, a drain extension region is connected with the drain electrode, and the source extension region is disposed opposite to the drain extension region to form a channel extension region therebetween.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 19, 2013
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Xinxin Li, Wei Wang, Chunping Long
  • Patent number: 8372755
    Abstract: A method for fabricating a semiconductor device is disclosed.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: February 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiang-Bau Wang, Hun-Jan Tao
  • Patent number: 8354678
    Abstract: A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Benjamin A. Fox, Nathaniel J. Gibbs, Andrew B. Maki, David M. Onsongo, Trevor J. Timpane
  • Patent number: 8354698
    Abstract: A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. The first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second source electrode of the JFET respectively.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: January 15, 2013
    Assignee: System General Corp.
    Inventors: Hsin-Chih Chiang, Han-Chung Tai
  • Patent number: 8338219
    Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 25, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventor: Massimo Cataldo Mazzillo
  • Publication number: 20120319178
    Abstract: A stacked planar device and method for forming the same is shown that includes forming, on a substrate, a stack of layers having alternating sacrificial and channel layers, patterning the stack such that sides of the stack include exposed surfaces of the sacrificial and channel layers, forming a dummy gate structure over a region of the stack to establish a planar area, forming a dielectric layer around the dummy gate structure to cover areas adjacent to the planar area, removing the dummy gate structure to expose the stack, selectively etching the stack to remove the sacrificial layers from the channel layers in the planar area, and forming a gate conductor over and in between the channel layers to form a transistor device.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8278683
    Abstract: Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source area, which increases the base current compared to a L-IGBT with a single MOS gate. The current density may be further increased by extending the base of the bipolar transistor in the L-IGBT vertically to the bottom surface of the silicon on insulator (SOI) film in which the L-IGBT is fabricated. Adding a buffer diffused region around the sinks in the source improves the base current spatial uniformity, which improves the safe operating area (SOA) of the L-IGBT. A L-IGBT of either polarity may be formed with the inventive configurations. A method of forming the inventive L-IGBT is also disclosed.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: October 2, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Philip Leland Hower
  • Patent number: 8264020
    Abstract: A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rectangular contact may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may be significantly increased.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: September 11, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Frank Wirbeleit
  • Patent number: 8264019
    Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 11, 2012
    Assignee: STMicroelectronics S.r.L.
    Inventor: Massimo Cataldo Mazzillo
  • Patent number: 8264058
    Abstract: A MOSFET driver compatible JFET device is disclosed. The JFET device can include a gate contact, a drain contact, and a source contact. The JFET device can further include a first gate region of semiconductor material adjacent the gate contact and a second region of semiconductor material adjacent the first gate region. The first gate region and the second gate region can form a first p-n junction between the first gate region and the second gate region. The JFET device can further include a channel region of semiconductor material adjacent the source contact. The channel region and the second gate region can form a second p-n junction between the second gate region and the channel region.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 11, 2012
    Assignee: University of South Carolina
    Inventors: Enrico Santi, Zhiyang Chen, Alexander Grekov
  • Patent number: 8253170
    Abstract: In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s).
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: August 28, 2012
    Assignee: Soitec SA & Soitec USA, Inc.
    Inventor: Hacène Lahreche
  • Patent number: 8232610
    Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshito Nakazawa, Yuji Yatsuda
  • Patent number: 8222649
    Abstract: A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: July 17, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Keiko Fujihira, Kenichi Otsuka, Masayuki Imaizumi
  • Patent number: 8222681
    Abstract: A trench IGBT is disclosed. One embodiment includes an embedded structure arranged above a collector region and selected from a group consisting of a porous semiconductor region, a cavity, and a semiconductor region including additional scattering centers for holes, the embedded structure being arranged below the body contact region such that the embedded structure and the body contact region overlap in a horizontal projection.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 17, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez
  • Patent number: 8203151
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 19, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8183096
    Abstract: A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rectangular contact may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may be significantly increased.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: May 22, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Frank Wirbeleit
  • Patent number: 8169022
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: May 1, 2012
    Assignee: SS SC IP, LLC
    Inventors: Lin Cheng, Michael Mazzola
  • Patent number: 8148758
    Abstract: A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: April 3, 2012
    Assignee: Alpha and Omega Semiconductor Inc.
    Inventor: Hamza Yilmaz
  • Patent number: 8138054
    Abstract: An enhanced FET capable of controlling current above and below a gate of the FET. The FET is formed on a semiconductor substrate. A source and drain are formed in the substrate (or in a well in the substrate). A first epitaxial layer of similar doping to the source and drain are grown on the source and drain, the first epitaxial layer is thicker than the gate, but not so thick as to cover the top of the gate. A second epitaxial layer of opposite doping is grown on the first epitaxial layer thick enough to cover the top of the gate. The portion of the second epitaxial layer above the gate serves as a body through which the gate controls current flow between portions of the first epitaxial layer over the drain and the source.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: David Howard Allen, Todd Alan Christensen, David Paul Paulsen, John Edward Sheets, II