With Multiple Channels Or Channel Segments Connected In Parallel, Or With Channel Much Wider Than Length Between Source And Drain (e.g., Power Jfet) Patents (Class 257/287)
  • Patent number: 8124961
    Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Kyoung-Hwan Yeo, Ming Li, Yun-Young Yeoh
  • Patent number: 8120074
    Abstract: A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: February 21, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez
  • Patent number: 8110858
    Abstract: One embodiment of the present invention is a thin film transistor array, having an insulating substrate and a stripe-shaped semiconductor layer for a plurality of transistors, the layer extending over the plurality of transistors. Another embodiment of the present invention is an active matrix type display, having the thin film transistor array of the one embodiment and an image display means.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: February 7, 2012
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Ryohei Matsubara, Mamoru Ishizaki
  • Patent number: 8097906
    Abstract: A semiconductor device which has low input inductance is provided.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: January 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8058655
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 15, 2011
    Assignee: SS SC IP, LLC
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 8048745
    Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a transistor structure including a gate electrode and a first channel region and source/drain regions on a substrate, and a second channel region and source/drain regions provided on the transistor structure. Accordingly, transistor operations can utilize the current path above and below the gate electrode.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: November 1, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Chang Young Ju
  • Patent number: 8030706
    Abstract: A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: October 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miho Watanabe, Masaru Izumisawa, Yasuto Sumi, Hiroshi Ohta, Wataru Sekine, Wataru Saito, Syotaro Ono, Nana Hatano
  • Patent number: 8017479
    Abstract: An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate, and a channel active region configured to connect opposite sidewalls within each trench region and having a surface used as a channel region.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: September 13, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae Sik Kim
  • Patent number: 8003466
    Abstract: A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: August 23, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhonghai Shi, David Wu, Jingrong Zhou, Ruigang Li
  • Patent number: 7989855
    Abstract: This invention relates to a semiconductor device having a beam made of a semiconductor to which strain is introduced by deflection, and a current is permitted to flow in the beam.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: August 2, 2011
    Assignee: NEC Corporation
    Inventor: Mitsuru Narihiro
  • Patent number: 7948016
    Abstract: The present disclosure provides a method of making a thin film semiconductor device such as a transistor comprising the steps of: a) providing a substrate bearing first and second conductive zones which define a channel therebetween, where the channel does not border more than 75% of the perimeter of either conductive zone; and b) depositing a discrete aliquot of a solution comprising an organic semiconductor adjacent to or on the channel, where a majority of the solution is deposited to one side of the channel and not on the channel. In some embodiments of the present disclosure, the solution is deposited entirely to one side of the channel, not on the channel, and furthermore the solution is deposited in a band having a length that is less than the channel length. The present disclosure additionally provides thin film semiconductor devices such as a transistors.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: May 24, 2011
    Assignee: 3M Innovative Properties Company
    Inventors: Scott M. Schnobrich, Robert S. Clough, Dennis E. Vogel, Michael E. Griffin
  • Patent number: 7902575
    Abstract: The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate as well as at least one improved structure capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the substrate, can make it possible to save space in the integration of field-effect transistors as well as to improve the performance thereof.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: March 8, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Thomas Ernst, Stephan Borel
  • Patent number: 7880202
    Abstract: A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between the source and drain regions. The transistor is structured such that the threshold voltage for current flow through the channel region varies at different points along the width direction, e.g., to give an improvement in the distortion characteristics of the transistor.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Peter Baumgartner
  • Patent number: 7859053
    Abstract: A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Brian S. Doyle
  • Patent number: 7851832
    Abstract: Electrode placement which applies easy heat dispersion of a semiconductor device with high power density and high exothermic density is provided for the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate 10, and have a plurality of fingers, respectively; gate terminal electrodes G1, G2, . . . , G4, source terminal electrodes S1, S2, . . . , S5, and a drain terminal electrode D which are placed on the first surface, and governs a plurality of fingers, respectively every the gate electrode, the source electrode, and the drain electrode; active areas AA1, AA2, . . . , AA5 placed on the substrate of the lower part of the gate electrode, the source electrode, and the drain electrode; a non-active area (BA) adjoining the active areas and placed on the substrate; and VIA holes SC1, SC2, . . .
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 7834407
    Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshito Nakazawa, Yuji Yatsuda
  • Patent number: 7825480
    Abstract: The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: November 2, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroki Arai, Nobuyuki Shirai, Tsuyoshi Kachi
  • Patent number: 7803675
    Abstract: The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: September 28, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Dong-Won Kim, Kyoung-Hwan Yeo
  • Patent number: 7799627
    Abstract: Embodiments relate to a multi device that may include a first MOS transistor having a first gate oxide film, and a second MOS transistor having a second gate oxide film thicker than the first gate oxide film. According to embodiments, a LDD structure of the first MOS transistor may be a two-layered structure in which a first LDD region and a second LDD region are disposed vertically downward from the surface of a wafer, and the second LDD region is substantially the same as an LDD structure in the second MOS transistor in doping concentration.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: September 21, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Jae-Hyun Yoo, Jong-Min Kim
  • Patent number: 7795083
    Abstract: The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: September 14, 2010
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hung-Shern Tsai, Shang-Hui Tu, Shin-Cheng Lin
  • Patent number: 7786530
    Abstract: A vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: August 31, 2010
    Assignee: Infineon Technologies AG
    Inventors: Ronald Kakoschke, Helmut Tews
  • Patent number: 7759733
    Abstract: A power semiconductor device includes: a first semiconductor substrate; a second semiconductor layer; a plurality of third semiconductor pillar regions and a plurality of fourth semiconductor pillar regions that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor substrate; a first main electrode; and a second main electrode. A concentration of first-conductivity-type impurity in a connective portion between the second semiconductor layer and the third semiconductor pillar regions is lower than concentrations of first-conductivity-type impurity in portions of both sides of the connective portion in a direction from the second semiconductor layer to the third semiconductor pillar regions.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: July 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Wataru Saito
  • Patent number: 7719055
    Abstract: A normally-off cascode power switch circuit is disclosed fabricated in wide bandgap semiconductor material such as silicon carbide or gallium nitride and which is capable of conducting current in the forward and reverse direction under the influence of a positive gate bias. The switch includes cascoded junction field effect transistors (JFETs) that enable increased gain, and hence blocking voltage, while minimizing specific on-resistance.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: May 18, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Ty R. McNutt, John V. Reichl, Harold C. Heame, III, Eric J. Stewart, Stephen D. Van Campen, Victor D. Veliadis
  • Patent number: 7679111
    Abstract: A power semiconductor device having a termination structure that includes a polysilicon field plate, a metallic field plate, and a polysilicon equipotential ring.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: March 16, 2010
    Assignee: International Rectifier Corporation
    Inventors: Jianjun Cao, Nazanin Amani, Daniel M. Kinzer
  • Patent number: 7667247
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: February 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Ya Wang, Wen-Chin Lee, Denny Tang
  • Patent number: 7646045
    Abstract: A nanoelement field effect transistor includes a nanotube disposed on the substrate. A first source/drain region is coupled to a first end portion of the nanoelement and a second source/drain region is coupled to a second end portion of the nanoelement. A recess in a surface region of the substrate is arranged in such a manner that a region of the nanoelement arranged between the first and second end portions is taken out over the entire periphery of the nanoelement. A gate-insulating structure covers the periphery of the nanoelement and a gate structure covers the periphery of the gate-insulating structure.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: January 12, 2010
    Assignee: Qimonda AG
    Inventors: Franz Kreupl, Robert Seidel
  • Patent number: 7642597
    Abstract: A power semiconductor device includes a semiconductor substrate having a plurality of trenches formed in an upper surface thereof; a buried insulating film; a buried field plate electrode; a control electrode; a first main electrode provided on a lower side of the semiconductor substrate; and a second main electrode provided on an upper side of the semiconductor substrate. The semiconductor substrate includes: a first semiconductor; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type; a fourth semiconductor layer; and a fifth semiconductor layer. The buried insulating film is thicker than a gate insulating film. At least one of the second semiconductor layer and the third semiconductor layer has a portion with its sheet dopant concentration varying along a depth direction of the semiconductor substrate.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: January 5, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Saito
  • Patent number: 7633102
    Abstract: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: December 15, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Zeng
  • Patent number: 7629631
    Abstract: A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of JFET regions separated by portions of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and at least two sides of each JFET region is lined with an oxide layer. In one group of embodiments the JFET regions extend from the surface of an epitaxial layer to an interface between the epitaxial layer and an underlying substrate, and the walls of each JFET region are lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region and allowing the JFET regions to be accurately located in the drift region.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: December 8, 2009
    Inventor: Hamza Yilmaz
  • Patent number: 7615802
    Abstract: The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region (2), a current path that runs within the first semiconductor region (2) and a channel region (22). The channel region (22) forms part of the first semiconductor region (2) and comprises a base doping. The current (I) in the channel region (22) can be influenced by means of at least one depletion zone (23, 24). The channel region (22) contains an n-conductive channel region (225) for conducting the current, said latter region having a higher level of doping than the base doping. The conductive channel region (225) is produced by ionic implantation in an epitaxial layer (262) that surrounds the channel region (22).
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: November 10, 2009
    Assignee: SiCED Electronics Development GmbH & Co. KG
    Inventors: Rudolf Elpelt, Heinz Mitlehner, Reinhold Schörner
  • Patent number: 7586137
    Abstract: A non-volatile memory device having an asymmetric channel structure is provided.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-chul Kim, Geum-jong Bae, In-wook Cho, Byoung-jin Lee, Sang-su Kim, Jin-hee Kim, Byou-ree Lim
  • Patent number: 7573108
    Abstract: A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first voltage that is configured to turn on the transistor, and the passive gate may be fixedly coupled to a second voltage different than the first voltage. In some embodiments, the difference in voltage between the first voltage and the second voltage is greater than or substantially equal to a difference in voltage between the first voltage and a substrate voltage.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: August 11, 2009
    Assignee: Micron Technology, Inc
    Inventor: Werner Juengling
  • Patent number: 7569875
    Abstract: A semiconductor device having a substrate; an emitter electrode or source electrode formed on the top surface side of the substrate; a gate electrode formed on the top surface side of the substrate; and a collector electrode or drain electrode formed on the bottom surface side of the substrate. The device includes an insulating region formed so as to surround a device-forming region provided on the top surface side of the substrate; and a drift region of the device-forming region, the drift region being in contact with the insulating region, is formed of a semiconductor layer having the same conduction type as that of a channel formed through application of an electric potential to the gate electrode. The gate electrode is a trench gate. An outer peripheral portion of the emitter electrode or source electrode extends in a width of 20 ?m or more over the top surface of the insulating region.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: August 4, 2009
    Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takashi Suzuki, Sachiko Tanaka, Masayasu Ishiko, Jun Saito, Tsuyoshi Nishiwaki, Yukihiro Hisanaga, Hidehiro Nakagawa, Hirokazu Saito
  • Patent number: 7560756
    Abstract: The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally opposite sidewalls of the carbon nanotube body. A gate electrode is formed on the gate dielectric on the top surface of the carbon nanotube body and adjacent to the gate dielectric on the laterally opposite sidewalls of the carbon nanotube body.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Brian S. Doyle, Jack Kavalieros, Douglas Barlage, Suman Datta
  • Patent number: 7557394
    Abstract: A lateral high-voltage depletion-mode device structure in which fingers of semiconductor material are interdigitated with trench gates. Since the effective channel area is proportional to the depth of the trenches, a large amount of active channel area can be achieved for a given surface area.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: July 7, 2009
    Assignee: Bourns, Inc.
    Inventors: Richard A. Blanchard, Françoise Hébert
  • Patent number: 7538370
    Abstract: In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: May 26, 2009
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Prasad Venkatraman, Irene S. Wan
  • Patent number: 7528426
    Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: May 5, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Publication number: 20090108303
    Abstract: A semiconductor component and method of making a semiconductor component. One embodiment provides a first metallization structure electrically coupled to charge compensation zones via an ohmic contact and to drift zones via a Schottky contact. A second metallization structure, which is arranged opposite the first metallization structure, is electrically coupled to the charge compensation zones via a Schottky contact and to drift zones via an ohmic contact.
    Type: Application
    Filed: October 30, 2008
    Publication date: April 30, 2009
    Applicant: Infineon Technologies Austria AG
    Inventor: Frank Pfirsch
  • Patent number: 7504678
    Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Brian S. Doyle, Jack Kavalieros, Douglas Barlage, Suman Datta
  • Patent number: 7501670
    Abstract: A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: March 10, 2009
    Assignee: Velox Semiconductor Corporation
    Inventor: Michael Murphy
  • Patent number: 7498617
    Abstract: A III-nitride power device that includes a Schottky electrode integrated with a power switch. The combination is used in power supply circuits such as a boost converter circuit.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: March 3, 2009
    Assignee: International Rectifier Corporation
    Inventor: Daniel M. Kinzer
  • Patent number: 7449762
    Abstract: A Lateral Epitaxial Gallium Nitride metal insulator semiconductor field effect transistor (LEGaN-MISFET) is described that includes a body region including at least one layer formed of Gallium Nitride having a first conductivity type formed on the substrate; a resurf layer of Gallium Nitride having a second conductivity type formed the body region; a source region in contact with the resurf layer; a drain region, in contact with the resurf layer and spaced apart from the source region; a gate metal insulator semiconductor (MIS) structure in contact with the body region including a gate contact; and a MIS conductive inversion channel along the surface of the body region in contact with the gate MIS structure. A lateral current conduction path may be formed in the resurf layer between the source region and the drain region connected by the MIS channel, where the lateral current conduction path is controlled by an applied gate source bias.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: November 11, 2008
    Assignee: Wide Bandgap LLC
    Inventor: Ranbir Singh
  • Publication number: 20080272409
    Abstract: A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region.
    Type: Application
    Filed: May 3, 2007
    Publication date: November 6, 2008
    Inventors: Sachin R. Sonkusale, Weimin Zhang, Ashok K. Kapoor
  • Patent number: 7442971
    Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: October 28, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Wirbeleit, Manfred Horstmann, Christian Hobert
  • Patent number: 7427788
    Abstract: A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating region surrounds the at least one pair of elongate channel regions, and a gate electrode surrounds the gate insulating region and the at least one pair of elongate channel regions. Support patterns may be interposed between the semiconductor substrate and the source and drain regions. The elongate channel regions may have sufficiently small cross-section to enable complete depletion thereof. For example, a width and a thickness of the elongate channel regions may be in a range from about 10 nanometers to about 20 nanometers. The elongate channel regions may have rounded cross-sections, e.g., each of the elongate channel regions may have an elliptical cross-section.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: September 23, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ming Li, Sung-min Kim
  • Publication number: 20080217664
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 11, 2008
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
  • Patent number: 7391087
    Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Patrick Morrow
  • Publication number: 20080142853
    Abstract: A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.
    Type: Application
    Filed: February 26, 2008
    Publication date: June 19, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Marius Orlowski
  • Patent number: 7385273
    Abstract: A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a bottom insulation thicker than the first thickness.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: June 10, 2008
    Assignee: International Rectifier Corporation
    Inventors: Hugo R Burke, Simon Green
  • Publication number: 20080128673
    Abstract: A transistor for a phase change memory device includes a semiconductor substrate in which active regions are delimited by an isolation structure. A groove is defined on a surface of a gate forming area of each active region. Portions of the isolation structure, which are adjacent to the gate forming area of the active region, are recessed to expose side faces of the gate forming area of the active region. A gate is formed on the gate forming area of the active region over the gate forming area grooves and exposed side faces thereof as well as the recessed portions of the isolation structure. Junction areas are then formed in the active region on both sides of the gate to complete the transistor of a phase change memory device.
    Type: Application
    Filed: September 14, 2007
    Publication date: June 5, 2008
    Inventors: Heon Yong CHANG, Suk Kyoung HONG, Hae Chan PARK, Nam Kyun PARK