Abstract: A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer. A channel direction connecting the p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.

Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.

Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.

Abstract: SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.

Abstract: This invention achieves a high inverse voltage of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. An n− high resistance region is formed at the periphery of a drift layer composed of a parallel pn layer of n drift regions and p partition regions. The impurity density ND of the n− high resistance region is 5.62×1017×VDSS−1.36(cm−3) or less. VDSS denotes the withstand voltage (V). An n low resistance region is arranged adjacent to the n− high resistance region.

Abstract: A normally “off” enhancement mode junction field effect transistor (JFET) is disclose. The JFET has a low threshold voltage in the range of 0.2 to 0.3 volts and a low on resistance. The Drain-to-Source voltage drop is less than 0.1 volt at a drain current of 100 amperes.

Abstract: The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor. A charge carrier zone (30) is provided, situated in the drift zone (14) of DMOS transistor (10), made up of individual partial charge carrier zones (32) situated at a distance from one another and connected to one another in a conducting manner, the charge carrier zone (30) having an opposite charge carrier doping from that of the drift zone (14), and being able to be acted upon by a potential that is negative with respect to a potential present at a drain terminal (24) of the DMOS transistor (10), so that a short-circuit current is prevented.

Abstract: Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric field can be chosen to have approximately the same magnitude in all of the compensation regions.

Abstract: The invention relates to a high-voltage semiconductor component comprising semiconductor areas (4, 5) of alternating, different conductivity types which are arranged in a semiconductor body in an alternating manner.

Abstract: A semiconductor device includes a plurality of shallow trench isolation bands, a plurality of channels, a source electrode, a drain electrode, and a gate electrode. The shallow trench isolation bands are formed in a band-like shape within an element formation region defined by a shallow trench isolation region. The plurality of channels are isolated from each other by the shallow trench isolation bands and extend parallel to each other. The source electrode is formed at one end of each channel. The drain electrode is formed at the other end of each channel. The gate electrode is formed on the channels across the shallow trench isolation bands. A method of manufacturing this device is also disclosed.

Abstract: The specification describes silicon MOS devices with gate dielectrics having the composition Ta1−xAlxOy, where x is 0.03-0.7 and y is 1.5-3, Ta1−xSixOy, where x is 0.05-0.15, and y is 1.5-3, and Ta1−x−zAlxSizOy, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatures. This retards formation of SiO2 interfacial layers which otherwise dominate the gate dielectric properties and reduce the overall effectiveness of using a high dielectric material.

Abstract: Semiconductor diodes are diode connected vertical cylindrical field effect devices having one diode terminal as the common connection between a gate and a source/drain of the vertical cylindrical field effect devices. Methods of forming the diode connected vertical cylindrical field effect devices are disclosed.

Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Abstract: This invention discloses the concept of the integration of the four terminal switcher and the capacitor pairs for the DC to DC converter or power supplier. This invention can be built by IC process as the DC to DC converter or power supply alone or used as power supply or converter module or block for distributed power in the System-on-Chip. This invention discloses the basic structure of the DC to DC converter or power supply module on standard CMOS IC process and on SOI substrates. This basic structure of the DC to DC converter or power supply module provides high current and low voltage applications for future generations of ICs.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A MOSFET that includes short channel regions for a reduced RDSON, and narrowly spaced, relatively deep base regions for an improved breakdown voltage.

Abstract: A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.

Abstract: This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.

Abstract: A semiconductor device provided with a field effect transistor having a electrode pads for wire-bonding comprises a first electrode pad for wire-bonding directly connected with the field effect transistor, and a second electrode pad for wire-bonding connected with the field effect transistor via a resistor. According to the semiconductor device, a chip used in the field effect transistor can be used in different frequencies by changing bonding.

Abstract: The invention relates to a microelectronics and more particularly to a bipolar static induction transistor.

Abstract: The invention is related to a method for fabricating a channel region of a transistor device by ion implantation with a large angle and the transistor device formed therefrom. The transistor device is formed on a substrate. Furthermore, the ion implantation with a large angle forms the channel of the transistor in order to prevent the punchthrough phenomenon between the source region and the drain region. In addition, the profile of the channel region is compact and non-uniform. Therefore the ion concentration is higher in the middle of the channel region than in the other regions. Thus, the parasitic capacitance and the junction leakage can be reduced. The carrier mobility is higher than that of the prior art. Moreover, the threshold voltage is more easily controlled than that of the prior art.

Abstract: A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current and contact with the gate electrode. This compound semiconductor field effect transistor is improved in breakdown voltage between drain and gate and yet retains the high-speed operability of transistor.

Abstract: A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by an insulation region.

Abstract: A semiconductor device of the present invention includes ohmic source plate electrodes, gate plate electrodes, and drain plate electrodes in parallel from each other in a heat generating region various designs are used to more evenly distribute heat generated in the semiconductor device. A first example has gold-plate electrodes formed on the respective source and drain plate electrodes in parallel with the ohmic plate electrodes. The gold-plate electrode arranged at the central portion of the heat generating region plate electrodes has the widest width and gold-plate electrodes arranged toward the center portion to the peripheral portion of the heat generating region narrow gradually. By the structure mentioned above, the semiconductor device of the present invention has uniform temperature distribution in a heat generating region. A second example uses a plurality of stripe plates perpendicular to the ohmic plate electrodes.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by a surface insulation region.

Abstract: A field effect transistor (FET) having a stabilization circuit with a stabilization condition not affected by another circuit element, for example, a matching circuit. The stabilization circuit is pre-formed inside of the FET, thereby pre-stabilizing the FET in a frequency range in which a power amplifier is used.

Abstract: This invention discloses the concept of the integration of the four terminal switcher and the capacitor pairs for the DC to DC converter or power supplier. This invention can be built by IC process as the DC to DC converter or power supply alone or used as power supply or converter module or block for distributed power in the System-on-Chip. This invention discloses the basic structure of the DC to DC converter or power supply module on standard CMOS IC process and on SOI substrates. This basic structure of the DC to DC converter or power supply module provides high current and low voltage applications for future generations of ICs.

Abstract: A drive transistor for an ink jet print head includes a semiconductor substrate having a serpentine channel of a first type doping, the channel comprising substantially parallel first and second serpentine channel portions, the first and second serpentine channel portions defining an inner region disposed between the first and second serpentine channel portions and an outer region disposed outside the first and second serpentine channel portions. A drain of a second type doping which is disposed within the inner region. A source of a second type doping which is disposed within the outer region. The transistor has a serpentine gate that overlies the serpentine channel. An elongate drain conductor, which tapers from a wide drain conductor end to a narrow drain conductor end, at least partially overlies a portion of the drain and the serpentine channel. An elongate source conductor has two tapered source conductor portions that at least partially overly the source and the serpentine channel.

Abstract: In order to achieve an aspect of the present invention, in a field effect transistor, a compound semiconductor substrate has an active region, and a gate finger electrode is formed on the active region. Source and drain stripe electrodes are formed on the active region to sandwich the gate finger electrode apart from the gate finger electrode. An extended gate electrode is connected with the gate finger electrode and extended source and drain electrodes are connected with the source and drain stripe electrodes, respectively. A resistance section is provided between the gate finger electrode and the extended gate electrode in the transistor forming region.

Abstract: This invention discloses the present invention discloses a junction field effect transistor UFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.

Abstract: Disclosed is an improved field effect transistor (FET) employing both a metal-semiconductor (MES) gate and a metal-insulator-semiconductor (MIS) gate, which FET is particularly useful to provide amplification at microwave frequencies. The use of the MIS gate with appropriate biasing allows the carrier density within a selected portion of the device's channel region to be controlled. The carrier density control increases the breakdown voltage of the FET and enables the FET to be operated with higher maximum channel current and a higher drain to source voltage. As a result, higher output power is provided as compared to prior art MESFET devices of a similar size. Also disclosed is an amplifier circuit including the MES/MIS FET of the preset invention, which amplifier circuit further includes means coupled to the MES/MIS FET for dividing a high frequency input signal to provide a first divided portion and a second divided portion.

Abstract: A semiconductor configuration, in particular based on silicon carbide, is specified which rapidly limits a short-circuit current to an acceptable current value. For this purpose, when a predetermined saturation current is exceeded, a lateral channel region is pinched off, and the current is limited to a value below the saturation current.

Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.

Abstract: A source region 3 and a back-gate region 4 are alternately arranged along one side of a gate electrode 2 in a power MOSFET. The back-gate region 4 is formed so as not to substantially include the region immediately below the gate electrode 2. Thereby, it is possible to prevent a parasitic bipolar transistor from operating while controlling the increase of a channel resistance and thus, the breakdown resistance is improved.

Abstract: A method of fabricating an integrated circuit includes forming a gate stack upon an active region of a substrate which includes a gate dielectric, a polysilicon gate conductor and a polysilicon consumption metal layer portion. The polysilicon consumption metal layer portion is then reacted with the polysilicon gate conductor to form a high conductivity gate conductor (silicide). In one embodiment, the polysilicon gate conductor is fully consumed. In another embodiment, the polysilicon gate conductor is substantially consumed but a portion of the polysilicon gate conductor adjacent the gate dielectric remains. In forming such a gate structure, a gate dielectric layer is first formed and a polysilicon gate layer is formed upon the gate dielectric layer. A polysilicon consumption metal layer is then formed upon the polysilicon gate layer. The surface is then patterned mask so that the location of the gate structures is protected. The substrate is then anisotropically etched to form the gate structures.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer.

Abstract: A semiconductor memory cell includes a read-out transistor of a first conductivity type which has source/drain regions constituted by a second conductive region and a third semiconducting region, a channel forming region constituted by a surface region of a second semiconducting region, and a conductive gate formed on a barrier layer; a switching transistor of a second conductivity type which has source/drain regions constituted by a first conductive region and the second semiconducting region, a channel forming region constituted by a surface region of a first semiconducting region, and a conductive gate formed on a barrier layer; and a current controlling junction-field-effect transistor of a first conductivity type which has gate regions constituted by a third conductive region and a portion of the second semiconducting region, a channel region constituted by a portion of the third semiconducting region, and one source/drain region extended from one end of the channel region, being constituted by a portion

Abstract: A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furnished in its central part with a high-concentration channel injection region containing N-type impurities at a concentration higher than that of the substrate. Between the high-concentration channel injection region on the one hand and the first and the second source drain region and on the other hand, there are formed a first and a second low-concentration channel injection region and having substantially the same impurity concentration as that of the substrate.

Abstract: A semiconductor configuration includes a first semiconductor region which has a predetermined conductivity type and a first surface. There is a contact region disposed on the first surface of the first semiconductor region. There is a second semiconductor region disposed within the first semiconductor region underneath the contact region which has a conductivity type opposite the predetermined conductivity type of the first semiconductor region. A first p-n junction having a first depletion zone is formed between the first semiconductor region and the second semiconductor region. The second semiconductor region extends further than the contact region in all directions parallel to the first surface of the first semiconductor region to form at least one lateral channel region with a bottom in the first semiconductor region. The at least one lateral channel region is bounded toward its bottom by the first depletion zone of the first p-n junction.

Abstract: A semiconductor device includes a transistor (30, 51) having a gate electrode (15, 52) wherein the gate electrode (15, 52) has a highly resistive portion (24, 25, 55). The highly resistive portion (24, 25, 55) is integrated into the gate electrode (15, 52) and is coupled to the gate electrode (15, 52) using a via-less contact method.

Abstract: An N.sup.- type epitaxial layer is formed on a P type semiconductor substrate, and a P.sup.+ type insulative isolating layer is so formed as to reach the semiconductor substrate from the surface of the N.sup.- type epitaxial layer to define a device forming region in the N.sup.- type epitaxial layer. An N.sup.+ type source diffusion layer and an N.sup.+ type drain diffusion layer are formed on the N.sup.- type epitaxial layer in the device forming region, apart from each other in one direction. A plurality of P.sup.+ type gate diffusion layers are formed between the N.sup.+ type source diffusion layer and N.sup.+ type drain diffusion layer, apart from one another in a direction perpendicular to the one direction. Channel regions for controlling the source-drain current are formed between the P.sup.+ type insulative isolating layer and the gate diffusion layer and between adjoining gate diffusion layers.

Abstract: A transistor includes: a source region; at least two drain regions; channels respectively disposed between the source region and each of the at least two drain regions; and a gate electrode provided on each of the channels. The at least two drain regions are electrically isolated from one another; and a drain electrode is provided on each of the drain regions.

Abstract: A boundary of a well 102 of a finger structured MOSFET is positioned between an element region 104 and a gate contact 108. With this geometry, it is feasible to reduce the well and attain a decrease in noises. A well electric potential take-out region 105 is disposed in close proximity to the element region 104 within the well 102, thereby making it possible to reduce an areal size of the well and farther decrease the noises.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) JFET device includes a semiconductor substrate, a buried insulating on the substrate, and a JFET device in a thin semiconductor layer of a first conductivity type on the buried insulating layer. The device includes a source region of the first conductivity type, a control region of a second conductivity type which is laterally spaced apart from the source region and a lateral drift region of the first conductivity type adjacent to the control region. A drain region of the first conductivity type is provided laterally spaced apart from the control region in a first lateral direction by the lateral drift region, and at least one field plate electrode is provided over at least a major portion of the lateral drift region and is insulated from the drift region by an insulation region.

Abstract: A load device for an MOS transistor, such as that of a memory cell, includes a differentially doped vertical JFET structure that contains two separate and distinct opposite conductivity type regions. The interior region has the same conductivity as the well in which the JFET is formed, and is surrounded by the JFET channel region which has a generally annular shape. The pinch-off voltage of the annular vertical JFET channel is established by its cross-sectional thickness and doping profile. This reduced thickness, annular-shaped, vertical JFET channel provides a limited current flow path that can be very precisely tailored to restrict current flow to what is essentially a leakage current path, and thereby provide a very high load impedance.

Abstract: In one aspect, a plurality of layers are formed over a substrate and a series of first trenches are etched into a first of the layers in a first direction. A series of second trenches are etched into the first layer in a second direction which is different from the first direction. Collectively, the first and second trenches define a plurality of different substrate elevations with adjacent elevations being joined by sidewalls which extend therebetween. Sidewall spacers are formed over the sidewalls, and material of the first layer is substantially selectively etched relative to material from which the spacers are formed. Material comprising the spacer material is substantially selectively etched relative to the first material. In a preferred implementation, the etching provides a plurality of cells which are separated from one another by no more than a lateral width dimension of a previously-formed spacer.