Light Responsive Or Combined With Light Responsive Device Patents (Class 257/290)
  • Patent number: 8901691
    Abstract: A touch sensing substrate includes a substrate, a first light sensing element, a second light sensing element and a first bias line. The first light sensing element includes a first gate electrode, a first active pattern overlapping with the first gate electrode, a first source electrode partially overlapping with the first active pattern and a first drain electrode partially overlapping with the first active pattern. The second light sensing element includes a second gate electrode, a second active pattern overlapping with the second gate electrode, a second source electrode partially overlapping with the second active pattern and a second drain electrode partially overlapping with the second active pattern. The first bias line is connected to the first and second gate electrodes.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Jong Yeo, Byeong-Hoon Cho, Ki-Hun Jeong, Hong-Kee Chin, Jung-Suk Bang, Woong-Kwon Kim, Sung-Ryul Kim, Hee-Joon Kim, Dae-Cheol Kim, Kun-Wook Han
  • Patent number: 8902210
    Abstract: An LCD device includes dual gate transistors provided to an output portion of the shift register for outputting a gate voltage. As such, the charge/discharge time of the output portion is reduced so the response time of liquid crystal is improved.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: December 2, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Kyo Ho Moon, Chul Gu Lee, Hoon Choi, Yong Soo Cho, Sang Kug Han
  • Patent number: 8890104
    Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 18, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min Yong Lee, Young Ho Lee, Seung Beom Baek, Jong Chul Lee
  • Publication number: 20140332868
    Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Patent number: 8878264
    Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Sergey Velichko, Jingyi Bai
  • Patent number: 8878265
    Abstract: According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shogo Furuya, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Publication number: 20140312205
    Abstract: Described is an arrangement for registering light, comprising: a MOS-transistor structure (101, 201, 401, 501, 601, 701) having a first source/drain region (103), a second source/drain region (105), and a bulk region (107) at least partially between the first source/drain region and the second source/drain region, wherein the bulk region has a doping type different from another doping type of the first and the second source/drain regions, wherein in the bulk region (107) charge carriers are generated in dependence of light (111) impinging on the bulk region (107), wherein the generated charge carriers control a current flowing from the first source/drain region (103) to the second source/drain region (105) via at least a portion of the bulk region.
    Type: Application
    Filed: March 24, 2014
    Publication date: October 23, 2014
    Applicant: NXP B.V.
    Inventor: Ernst Bretschneider
  • Patent number: 8860099
    Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: October 14, 2014
    Assignee: Sony Corporation
    Inventors: Keiji Tatani, Fumihiko Koga, Takashi Nagano
  • Patent number: 8853754
    Abstract: An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 7, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20140284669
    Abstract: An optoelectronic integrated device includes a body made of semiconductor material, which is delimited by a front surface and includes a substrate having a first type of conductivity, an epitaxial region, which has the first type of conductivity and forms the front surface, and a ring region having a second type of conductivity, which extends into the epitaxial region from the front surface, and delimiting an internal region. The optoelectronic integrated device moreover includes a MOSFET including at least one body region having the second type of conductivity, which contacts the ring region and extends at least in part into the internal region from the front surface. A photodetector includes a photodetector region having the second type of conductivity, and extends into the semiconductor body starting from the front surface, contacting the ring region.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 25, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Luigi ARCURI, MariaEloisa Castagna
  • Publication number: 20140264501
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: SEMICONDUCTOR RESEARCH CORPORATION
    Inventors: Yeul Na, KRISHNA C. SARASWAT
  • Publication number: 20140264500
    Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes disposed on a silicon island formed by a P? epitaxial layer and surrounded by trenches that provide lateral isolation, where the island is separated from the substrate by a porous silicon region that is grown under the island and isolates the lower portions of the photovoltaic device from the highly doped substrate. The trenches extend through the P? epitaxial material into the P+ substrate to facilitate self-limiting porous silicon formation at the bottom of the island, and also to suppress electron-hole recombination. A protective layer (e.g., SiN) is formed on the trench walls to further restrict porous silicon formation to the bottom of the island. Black silicon on the trench walls enhances light capture. The photovoltaic devices form low-cost embedded photovoltaic arrays on CMOS IC devices, or are separated to produce low-cost, HV solar arrays for solar energy sources, e.g. for solar concentrators.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicants: Yissum Research Development Company of The Hebrew University of Jerusalem Ltd., Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Evgeny Pikhay, Irit Chen-Zamero, Ora Eli, Micha Asscher, Amir Saar
  • Publication number: 20140263945
    Abstract: A field effect transistor photodetector that can operate in room temperature includes a source electrode, a drain electrode, a channel to allow an electric current to flow between the drain and source electrodes, and a gate electrode to receive a bias voltage for controlling the current in the channel. The photodetector includes a light-absorbing material that absorbs light and traps electric charges. The light-absorbing material is configured to generate one or more charges upon absorbing light having a wavelength within a specified range and to hold the one or more charges. The one or more charges held in the light-absorbing material reduces the current flowing through the channel.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Inventors: Jinsong Huang, Yongbo Yuan
  • Patent number: 8829332
    Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes disposed on a silicon island formed by a P? epitaxial layer and surrounded by trenches that provide lateral isolation, where the island is separated from the substrate by a porous silicon region that is grown under the island and isolates the lower portions of the photovoltaic device from the highly doped substrate. The trenches extend through the P? epitaxial material into the P+ substrate to facilitate self-limiting porous silicon formation at the bottom of the island, and also to suppress electron-hole recombination. A protective layer (e.g., SiN) is formed on the trench walls to further restrict porous silicon formation to the bottom of the island. Black silicon on the trench walls enhances light capture. The photovoltaic devices form low-cost embedded photovoltaic arrays on CMOS IC devices, or are separated to produce low-cost, HV solar arrays for solar energy sources, e.g. for solar concentrators.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 9, 2014
    Assignees: Tower Semiconductor Ltd., Yissum Research Development Company of the Hebrew University of Jerusalem Ltd.
    Inventors: Yakov Roizin, Evgeny Pikhay, Irit Chen-Zamero, Ora Eli, Micha Asscher, Amir Saar
  • Patent number: 8822897
    Abstract: In various example embodiments, the inventive subject matter is an image sensor and methods of formation of image sensors. In an embodiment, the image sensor comprises a semiconductor substrate and a plurality of pixel regions. Each of the pixel regions includes an optically sensitive material over the substrate with the optically sensitive material positioned to receive light. A pixel circuit for each pixel region is also included in the sensor. Each pixel circuit comprises a charge store formed on the semiconductor substrate and a read out circuit. A non-metallic contact region is between the charge store and the optically sensitive material of the respective pixel region, the charge store being in electrical communication with the optically sensitive material of the respective pixel region through the non-metallic contact region.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: September 2, 2014
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Igor Constantin Ivanov, Edward Hartley Sargent
  • Publication number: 20140239360
    Abstract: A semiconductor device, including: a gate electrode formed on a semiconductor substrate through a gate insulating film; an extension region formed in the semiconductor substrate on a source side of the gate electrode; a source region formed in the semiconductor substrate on the source side of the gate electrode through the extension region; an LDD region formed in the semiconductor substrate on a drain side of the gate electrode; and a drain region formed in the semiconductor substrate on the drain side of the gate electrode through the LDD region; wherein the extension region is formed at a higher concentration than that of the LDD region so as to be shallower than the LDD region.
    Type: Application
    Filed: May 2, 2014
    Publication date: August 28, 2014
    Applicant: Sony Corporation
    Inventor: Ryosuke Nakamura
  • Publication number: 20140239158
    Abstract: A photoelectric converter includes a first pn junction comprised of at least two semiconductor regions of different conductivity types, and a first field-effect transistor including a first source connected with one of the semiconductor regions, a first drain, a first insulated gate and a same conductivity type channel as that of the one of the semiconductor regions. The first drain is supplied with a second potential at which the first pn junction becomes zero-biased or reverse-biased relative to a potential of the other of the semiconductor regions. When the first source turns to a first potential and the one of the semiconductor regions becomes zero-biased or reverse-biased relative to the other semiconductor regions, the first pn junction is controlled not to be biased by a deep forward voltage by supplying a first gate potential to the first insulated gate, even when either of the semiconductor regions is exposed to light.
    Type: Application
    Filed: October 5, 2012
    Publication date: August 28, 2014
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE, RICOH COMPANY, LTD.
    Inventors: Yutaka Hayashi, Toshitaka Ota, Yasushi Nagamune, Hirofumi Watanabe, Takaaki Negoro, Kazunari Kimino
  • Patent number: 8815628
    Abstract: A complementary metal oxide semiconductor (CMOS) device and a method for fabricating the same are provided. The CMOS image sensor includes: a first conductive type substrate including a trench; a channel stop layer formed by using a first conductive type epitaxial layer over an inner surface of the trench; a device isolation layer formed on the channel stop layer to fill the trench; a second conductive type photodiode formed in a portion of the substrate in one side of the channel stop layer; and a transfer gate structure formed on the substrate adjacent to the photodiode to transfer photo-electrons generated from the photodiode.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: August 26, 2014
    Assignee: Intellectual Ventures II LLC
    Inventor: Sang-Young Kim
  • Patent number: 8816363
    Abstract: A method of manufacturing an organic light-emitting element. A first layer is formed above a substrate, and exhibits hole injection properties. A bank material layer is formed above the first layer using a bank material. Banks are formed by patterning the bank material layer, and forming a resin film on a surface of the first layer by attaching a portion of the bank material layer to the first layer, the banks defining apertures corresponding to light-emitters, the resin material being the same as the bank material. A functional layer is formed by applying ink to the apertures that contacts the resin film. The ink contains an organic material. The functional layer includes an organic light-emitting layer. A second layer is formed above the functional layer and exhibits electron injection properties. The hole injection properties of the first layer are then degraded by applying electrical power to an element structure.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: August 26, 2014
    Assignee: Panasonic Corporation
    Inventors: Takashi Isobe, Kosuke Mishima, Kaori Akamatsu, Satoru Ohuchi
  • Patent number: 8816405
    Abstract: An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for additional absorption. In addition, the elevated photosensors reduce the size of the pixel cells while reducing leakage, image lag, and barrier problems.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 26, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 8817144
    Abstract: A photoelectric conversion apparatus includes a semiconductor substrate having a photoelectric conversion portion. An insulator is provided on the semiconductor substrate. The insulator has a hole corresponding to the photoelectric conversion portion. A waveguide member is provided in the hole. An in-layer lens is provided on a side of the waveguide member farther from the semiconductor substrate. A first intermediate member is provided between the waveguide member and the in-layer lens. The first intermediate member has a lower refractive index than the in-layer lens.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 26, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Taro Kato, Mineo Shimotsusa, Hiroaki Sano, Takeshi Ichikawa, Yasuhiro Sekine, Mahito Shinohara, Genzo Momma
  • Publication number: 20140231886
    Abstract: A flexible photosensor includes a flexible substrate, a gate on the flexible substrate, the gate including a conductive material having a planar structure, a gate insulating layer on the flexible substrate and the gate to at least cover the gate, the gate insulating layer including a non-conductive material having a planar structure, and a channel layer on the gate insulating layer, the channel layer including a semiconductor material having a planar structure.
    Type: Application
    Filed: November 13, 2013
    Publication date: August 21, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tian-zi SHEN, Won-jong YOO, Huamin LI, Min-Sup CHOI, Jae-young CHOI
  • Patent number: 8809921
    Abstract: A solid-state imaging apparatus includes a plurality of pixels each including a photoelectric conversion unit and pixel transistors, which are formed on a semiconductor substrate; a floating diffusion unit in the pixel; a first-conductivity-type ion implantation area for surface pinning, which is formed over the surface on the side of the photoelectric conversion unit and the surface of the semiconductor substrate; and a second-conductivity-type ion implantation area for forming an overflow path serving as an overflow path for the floating diffusion unit, the second-conductivity-type ion implantation area being formed below the entire area of the first-conductivity-type ion implantation area. An overflow barrier is formed using the second-conductivity-type ion implantation area. A charge storage area is formed using an area in which the second-conductivity-type semiconductor area and the second-conductivity-type ion implantation area superpose each other.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: August 19, 2014
    Assignee: Sony Corporation
    Inventors: Akihiro Yamada, Atsuhiko Yamamoto, Hideo Kido
  • Patent number: 8809924
    Abstract: According to an aspect of the invention, an imaging device includes a plurality of photoelectric conversion elements and a read-out portion. The photoelectric conversion elements are arranged above a substrate. The read-out portion reads out signal corresponding to charges which are generated from each of the photoelectric conversion elements. Each of the photoelectric conversion elements includes a first electrode that collects the charge, a second electrode that is disposed opposite to the first electrode, a photoelectric conversion layer that generates the charges and disposed between the first electrode and the second electrode, and an electron blocking layer that is disposed between the first electrode and the photoelectric conversion layer. Distance between the first electrodes of adjacent photoelectric conversion elements is 250 nm or smaller. Each of the electron blocking layers has a change in surface potential of ?1 to 3 eV from a first face to a second face.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: August 19, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Hideyuki Suzuki, Kiyohiko Tsutsumi
  • Patent number: 8803057
    Abstract: A method of resetting a photosite is disclosed. Photogenerated charges accumulated in the photosite are reset by recombining the photogenerated charges with charges of opposite polarity.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: August 12, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Fran├žois Roy, Julien Michelot
  • Patent number: 8803268
    Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: John Heck, Ansheng Liu, Michael T. Morse, Haisheng Rong
  • Patent number: 8803209
    Abstract: A photodetector device includes: a first semiconductor region of a first conductivity type electrically connected to a first external electrode: a second semiconductor region of a second conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on the second semiconductor region; and a plurality of fourth semiconductor regions of the second conductivity type formed on the second semiconductor region, each of the plurality of fourth semiconductor regions being surrounded by the third semiconductor region, including a second conductivity type impurity having a concentration higher than a concentration of the second semiconductor region, and electrically connected to a second external electrode.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: August 12, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Noriyuki Nakamura
  • Publication number: 20140217485
    Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.
    Type: Application
    Filed: April 7, 2014
    Publication date: August 7, 2014
    Applicant: International Business Machines Corporation
    Inventors: Solomon Assefa, Tymon Barwicz, Swetha Kamlapurkar, Marwan H. Khater, Steven M. Shank, Yurii A. Vlasov
  • Patent number: 8796747
    Abstract: A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, William M. J. Green, Steven M. Shank, Yurii A. Vlasov
  • Publication number: 20140209985
    Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector.
    Type: Application
    Filed: March 27, 2014
    Publication date: July 31, 2014
    Applicant: International Business Machines Corporation
    Inventors: Solomon Assefa, Jeffrey P. Gambino, Steven M. Shank
  • Publication number: 20140203340
    Abstract: The photodiode has a p-type doped region (2) and an n-type doped region (3) in a semiconductor body (1), and a pn junction (4) between the p-type doped region and the n-type doped region. The semiconductor body has a cavity (5) such that the pn junction (4) has a distance (d) of at most 30 ?m from the bottom of the cavity (7).
    Type: Application
    Filed: May 4, 2012
    Publication date: July 24, 2014
    Applicant: AMS AG
    Inventors: Jochen Kraft, Ingrid Jonak-Auer, Rainer Minixhofer, Jordi Teva, Herbert Truppe
  • Patent number: 8785991
    Abstract: A solid state imaging device includes a photoelectric conversion portion in which the shape of potential is provided such that charge is mainly accumulated in a vertical direction.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 8785932
    Abstract: An IR sensing transistor according to an exemplary embodiment of the present invention includes: a light blocking layer formed on a substrate; a gate insulating layer formed on the light blocking layer; a semiconductor formed on the gate insulating layer; a pair of ohmic contact members formed on the semiconductor; a source electrode and a drain electrode formed on respective ones of the ohmic contact members; a passivation layer formed on the source electrode and the drain electrode; and a gate electrode formed on the passivation layer, wherein substantially all of the gate insulating layer lies on the light blocking layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: July 22, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Suk Won Jung, Byeong Hoon Cho, Sung Hoon Yang, Woong Kwon Kim, Sang Youn Han, Dae Cheol Kim, Ki-Hun Jeong, Kyung-Sook Jeon, Seung Mi Seo, Jung-Suk Bang, Kun-Wook Han
  • Publication number: 20140191302
    Abstract: A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.
    Type: Application
    Filed: January 8, 2013
    Publication date: July 10, 2014
    Applicant: International Business Machines Corporation
    Inventors: Solomon Assefa, William M.J. Green, Steven M. Shank, Yurii A. Vlasov
  • Patent number: 8773336
    Abstract: Illumination devices and related systems and methods are closed that can be used for LCD (Liquid Crystal Display) backlights, LED lamps, or other applications. The illumination devices can include a photo detector, such as a photodiode or an LED or other light detecting device, and one or more LEDs of different colors. A related method can be implemented using these illumination devices to maintain precise color produced by the blended emissions from such LEDs. One application for the illumination devices is backlighting for FSC (Field Sequential Color) LCDs (Liquid Crystal Displays). FSC LCDs temporally mix the colors in an image by sequentially loading the red, green, and blue pixel data of an image in the panel and flashing the different colors of an RGB backlight. Precise and uniform color temperature across such a display can be advantageously maintained by continually monitoring ratios of photodiode currents induced by the different colored LEDs in each illumination device as each color is flashed.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: July 8, 2014
    Assignee: Ketra, Inc.
    Inventor: David J. Knapp
  • Publication number: 20140183606
    Abstract: According to an embodiment of the invention, there is provided a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming a trench downward from an upper face of a semiconductor layer at a position where an element isolation area is formed in the semiconductor layer, and melting the upper face of the trench-formed semiconductor layer to close an open end of the trench.
    Type: Application
    Filed: May 29, 2013
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazunori KAKEHI, Hisashi Aikawa, Yosuke Kitamura
  • Patent number: 8764462
    Abstract: The invention concerns a semiconductor component with a layered arrangement with an electrode, an organic semiconductor layer, an injection layer, and an additive layer, which consists of an additive, which on contact with the molecular doping material modifies its doping affinity with respect to the organic material of the organic semiconductor layer, wherein in the injection layer a layered region is formed with a first doping affinity of the molecular doping material with respect to the organic material and a further layered region is formed with a second, in comparison to the first doping affinity smaller, doping affinity of the molecular doping material with respect to the organic material. Furthermore the invention concerns a method for the manufacture of a semiconductor component and also the application of a semiconductor component.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: July 1, 2014
    Assignee: Novaled AG
    Inventors: Sascha Dorok, Rudolf Lessmann, Tobias Canzler, Qiang Huang, Christiane Koehn
  • Patent number: 8766157
    Abstract: A method of operating a CMOS pixel is disclosed. The CMOS pixel includes a photodiode (PPD), a transfer gate coupled to the PPD, and an anti-blooming drain coupled to the transfer gate. A potential barrier is formed between a potential well underlying the PPD and the transfer gate. Charge is accumulated in the potential well in response to electromagnetic radiation during a first integration time. Excess charge is removed from the potential well to the anti-blooming drain that exceeds the first potential barrier. A size of the potential barrier is increased. Charge is accumulated in the potential well during a second integration time.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: July 1, 2014
    Assignee: SRI International
    Inventors: Peter Alan Levine, Rui Zhu
  • Patent number: 8766337
    Abstract: A first thin film diode (100A) has a first semiconductor layer (10A) and a first light blocking layer (12A) disposed on the substrate side of the first semiconductor layer. A second thin film diode (100B) has a second semiconductor layer (10B) and a second light blocking layer (12B) disposed on the substrate side of the second semiconductor layer. An insulating film (14) is formed between the first semiconductor layer (10A) and the first light blocking layer (12A) and between the second semiconductor layer (10B) and the second light blocking layer (12B). A thickness D1 of a portion of the insulating film (14) positioned between the first semiconductor layer (10A) and the first light blocking layer (12A) is different from a thickness D2 of a portion of the insulating film (14) positioned between the second semiconductor layer (10B) and the second light blocking layer (12B).
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: July 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroshi Aichi
  • Patent number: 8759873
    Abstract: A bispectral detector comprising upper and lower semiconductor layers of a first conductivity type in order to absorb a first and a second electromagnetic spectrum, separated by an intermediate layer that forms a barrier; semiconductor zones of a second conductivity type implanted in upper layer and lower layer and each implanted at least partially in the bottom of an opening that passes through upper layer and intermediate layer; and conductor elements connected to semiconductor zones. At least that part of each opening that passes through upper layer is separated from the latter by a semiconductor cap layer: whereof the concentration of dopants of the second conductivity type is greater than 1017 cm?3; and whereof the thickness is chosen as a function of said concentration so that it exceeds the minority carrier diffusion length in the cap layer.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: June 24, 2014
    Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
    Inventors: Olivier Gravrand, Jacques Baylet
  • Patent number: 8748953
    Abstract: Methods and devices that incorporate microlens arrays are disclosed. An image sensor includes a pixel layer and a dielectric layer. The pixel layer has a photodetector portion configured to convert light absorbed by the pixel layer into an electrical signal. The dielectric layer is formed on a surface of the pixel layer. The dielectric layer has a refractive index that varies along a length of the dielectric layer. A method for fabricating an image sensor includes forming an array of microlenses on a surface of the dielectric layer, emitting ions through the array of microlenses to implant the ions in the dielectric layer, and removing the array of microlenses from the surface of the dielectric layer.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: June 10, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Giovanni Margutti, Andrea Del Monte
  • Patent number: 8734008
    Abstract: An active sensor apparatus includes an array of sensor elements arranged in a plurality of columns and rows of sensor elements. The sensor apparatus includes a plurality of column and row thin film transistor switches for selectively activating the sensor elements, and a plurality of column and row thin film diodes for selectively accessing the sensor elements to obtain information from the sensor elements. The thin film transistor switches and thin film diodes are formed on a common substrate.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: May 27, 2014
    Assignee: Next Biometrics AS
    Inventor: Matias N. Troccoli
  • Patent number: 8735882
    Abstract: A semiconductor device may include a composite represented by Formula 1 below as an active layer. x(Ga2O3).y(In2O3).z(ZnO)??Formula 1 wherein, about 0.75?x/z?about 3.15, and about 0.55?y/z? about 1.70. Switching characteristics of displays and driving characteristics of driving transistors may be improved by adjusting the amounts of a gallium (Ga) oxide and an indium (In) oxide mixed with a zinc (Zn) oxide and improving optical sensitivity.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-jung Kim, I-hun Song, Dong-hun Kang, Young-soo Park
  • Publication number: 20140131778
    Abstract: Pixel Front end circuits particularly applicable to photodetectors requiring wide bias ranges and/or with high background currents. In various versions, wide bias ranges, short protection, and background current subtraction, both predetermined and automatically sampled, are disclosed.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Inventor: Kenton Veeder
  • Patent number: 8723278
    Abstract: A sensor element array and method of fabricating the same are provided. The sensor element array is disposed on a substrate and includes a first patterned conductive layer, a channel layer, a first insulation layer, a second patterned conductive layer, a second insulation layer, and a third patterned conductive layer. The first patterned conductive layer includes a sensing line, a first power line, a source/drain pattern and a branch pattern. The channel layer includes a first channel and a second channel. Margins of the first insulation layer and the second patterned conductive layer are substantially overlapped. The second patterned conductive layer includes a selecting line, a gate pattern, and a gate connecting pattern. The second insulation layer has a first connecting opening for exposing the gate connecting pattern. The third patterned conductive layer includes a sensing electrode electrically connected to the gate connecting pattern.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: May 13, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Ming Lai, Yung-Hui Yeh
  • Patent number: 8715814
    Abstract: A method, apparatus and material produced thereby in an amorphous or crystalline form having multiple elements with a uniform molecular distribution of elements at the molecular level.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 6, 2014
    Inventor: L. Pierre de Rochemont
  • Patent number: 8717468
    Abstract: A solid-state imaging device is disclosed. The solid-state image device has pixels in which an absorption film that absorbs short wavelength-side light is formed on a photoelectric conversion portion for desired color light through an insulation film.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: May 6, 2014
    Assignee: Sony Corporation
    Inventor: Kazuichiro Itonaga
  • Patent number: 8710559
    Abstract: A solid-state imaging apparatus includes a transfer gate electrode formed on a semiconductor substrate; a photoelectric conversion unit including an electric charge storage area that is formed from a surface side of the semiconductor substrate in a depth direction, a transfer auxiliary area formed of a second conductive type impurity area that is formed in such a manner as to partially overlap the transfer gate electrode, and a dark current suppression area that is a first dark current suppression area formed in an upper layer of the transfer auxiliary and formed so as to have positional alignment in such a manner that the end portion of the transfer auxiliary area on the transfer gate electrode side is at the same position as the end portion of the transfer auxiliary area; and a signal processing circuit configured to process an output signal output from the solid-state imaging apparatus.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 29, 2014
    Assignee: Sony Corporation
    Inventors: Mikiko Kobayashi, Sanghoon Ha
  • Patent number: 8710558
    Abstract: There is provided a photoelectric conversion apparatus which is characterized by comprising a plurality of photoelectric conversion regions of a first conductivity type, and a plurality of semiconductor regions of a second conductivity type opposite to the first conductivity type; and in that the plurality of photoelectric conversion regions of the first conductivity type and the plurality of semiconductor regions are alternately arranged, and a voltage controlling unit is further provided to change a width of a depletion layer formed in a semiconductor substrate by controlling a voltage to be applied to the semiconductor region of the second conductivity type provided between the plurality of photoelectric conversion regions of the first conductivity type.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: April 29, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Daisuke Inoue, Tetsunobu Kochi, Yukihiro Kuroda, Hideo Kobayashi, Kouji Maeda
  • Publication number: 20140110771
    Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, a first line provided in the peripheral circuit area and on a first principal surface of the semiconductor substrate, a second line provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a first through electrode connected to one end of the first line and one end of the second line and passing through the semiconductor substrate, and a second through electrode connected to the other end of the first line and the other end of the second line and passing through the semiconductor substrate.
    Type: Application
    Filed: July 23, 2013
    Publication date: April 24, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoyuki YODA, Jiro Hayakawa, Ikuko Inoue, Eiji Sato, Takeshi Kitahara