With Ferroelectric Material Layer Patents (Class 257/295)
  • Patent number: 10381556
    Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 13, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mark L. Doczy, Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Kevin P. O'Brien, Satyarth Suri, Tejaswi K. Indukuri
  • Patent number: 10381407
    Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventors: Beom Yong Kim, Soo Gil Kim
  • Patent number: 10374054
    Abstract: A ferroelectric memory device includes a substrate having a source electrode and a drain electrode therein, a first interfacial dielectric layer including an anti-ferroelectric material disposed on the substrate between the source electrode and the drain electrode, a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric layer, and a gate electrode disposed on the ferroelectric gate dielectric layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10358680
    Abstract: Plasmonics-active nanoprobes are provided for detection of target biomolecules including nucleic acids, proteins, and small molecules. The nucleic acids that can be detected include RNA, DNA, mRNA, microRNA, and small nucleotide polymorphisms (SNPs). The nanoproprobes can be used in vito in sensitive detection methods for diagnosis of diseases and disorders including cancer. Multiplexing can be performed using the nanoprobes such that multiple targets can be detected simultaneously in a single sample. The methods of use of the nanoprobes include detection by a visible color change. The nanoprobes can be used in vivo for treatment of undesireable cells in a subject.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 23, 2019
    Assignee: DUKE UNIVERSITY
    Inventors: Tuan Vo-Dinh, Hsin-Neng Wang
  • Patent number: 10361359
    Abstract: A Magnetic Random Access Memory apparatus device having a memory element formed as a magnetic tunnel junction (MTJ) pillar and having a heating element for maintaining a desired minimum temperature of the memory element. The heating element is separated from the memory element by a thin, non-magnetic, electrically insulating wall, which can be constructed of alumina. The heating element is connected with circuitry that controllably delivers electrical current to the heating element to maintain a desired minimum temperature of the memory element.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 23, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Manfred Ernst Schabes, Thomas D. Boone, Mustafa Pinarbasi
  • Patent number: 10355199
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; an interlayer dielectric layer formed over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure comprises: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and including a material having a lower etch rate than that of silicon nitride (SiN); a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyung-Suk Lee, Do-Yeon Kim
  • Patent number: 10355201
    Abstract: A laminated structure according to an embodiment includes: a ferromagnetic layer; and a multiferroic layer formed on one surface of the ferromagnetic layer, wherein the multiferroic layer includes a first region having a tetragonal crystal located on a surface side on the ferromagnetic layer side and a second region having a rhombohedral crystal located further inside than the first region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 16, 2019
    Assignee: TDK CORPORATION
    Inventors: Eiji Suzuki, Katsuyuki Nakada, Shogo Yonemura
  • Patent number: 10347820
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Altansargai Buyandalai, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi
  • Patent number: 10332957
    Abstract: A layered structure including a tri-stack dielectric layer and a plurality of metal layers insulated from each other by the tri-stack dielectric layer. The plurality of metal layers includes a set of first-type metal layers and a set of second-type metal layers. An adjacent pair of the plurality of metal layers includes a first-type metal layer and a second-type metal layer. The tri-stack dielectric layer includes a first tri-stack layer including Al2O3, a second tri-stack layer including HfO2; and a third tri-stack layer including Al2O3.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Vijay Narayanan, Adam M. Pyzyna
  • Patent number: 10332893
    Abstract: Techniques and mechanisms for exchanging signals with one or more transistors at a front side of a semiconductor substrate. In an embodiment, an integrated circuit include a cell—such as a static random access memory (SRAM) cell—comprising transistor structures variously disposed in or on a first side of a substrate. After fabrication of such transistor structures, substrate material may be thinned to expose a second side of the substrate, opposite the first side. A first interconnect and a second interconnect are coupled each to exchange a signal or a voltage. In another embodiment, respective portions of the first interconnect and the second interconnect extend on opposite sides of the substrate, wherein the first side and the second side each extend between such interconnect portions. Positioning of interconnect structures on opposite sides of the substrate allow for performance improvements due to low interconnect resistances.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Eric A. Karl
  • Patent number: 10332874
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jin-Ping Han, Yulong Li, Dennis M. Newns, Paul M. Solomon, Xiao Sun
  • Patent number: 10332570
    Abstract: A memory device includes a memory cell coupled to a bitline and a bitline complement. A first capacitive structure is charged with a first voltage source such as a memory supply voltage. A second capacitive structure is charged with a second voltage source such as a core supply voltage. A coupling structure selectively and capacitively couples the first capacitive structure and the second capacitive structure to the bitline or the bitline complement, thereby applying a negative bitline write assist to the memory cell during a write operation.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Tawfik Ahmed
  • Patent number: 10310553
    Abstract: A display apparatus for a vehicle and including a display; a heating element configured to provide heat to the display; an interface configured to receive at least one of interior temperature information and exterior temperature information about the vehicle; and a processor configured to control the heating element to produce heat based on the received at least one of the interior temperature information and the exterior temperature information about the vehicle.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: June 4, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Changgeun Choi, Soono Song, Daehyun An
  • Patent number: 10312238
    Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • Patent number: 10304731
    Abstract: Disclosed herein is an apparatus that includes a ferroelectric capacitor disposed on a damascene barrier film, and fabrication methods thereof. The damascene barrier film includes a hydrogen barrier region and an oxygen barrier region, with the oxygen barrier being in contact with a bottom surface of the ferroelectric capacitor. Other embodiments are also disclosed herein.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: May 28, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Fan Chu
  • Patent number: 10305037
    Abstract: A variable resistive memory device includes a first electrode layer, a variable resistive pattern structure located on the first electrode layer and including a variable resistive layer, a capping layer formed on opposite side walls of the variable resistive pattern structure and including regions having different impurity concentrations, and a second electrode layer formed on the capping layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sug-woo Jung
  • Patent number: 10290700
    Abstract: A tri-layer dielectric stack is provided for a metal-insulator-metal capacitor (MIMCAP). Also, a metal-insulator-metal capacitor (MIMCAP) is provided having three or more electrodes. The tri-layer dielectric stack includes a first layer formed from a first metal oxide electrical insulator. The tri-layer dielectric stack further includes a second layer, disposed over the first layer, formed from ZrO2. The tri-layer dielectric stack also includes a third layer, disposed over the second layer, formed from a second metal oxide electrical insulator.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Hemanth Jagannathan, Paul C. Jamison
  • Patent number: 10283703
    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Andrea Ghetti
  • Patent number: 10283469
    Abstract: A method of forming a passivation layer on an integrated circuit (IC) chip including a device layer on a substrate. The method may include forming a crosslinked precursor passivation layer on the IC chip, and curing the crosslinked precursor passivation layer at a first temperature to form a passivation layer. The method may further include maintaining the device layer at a second, lower temperature during the curing of the crosslinked precursor passivation layer. Maintaining the device layer at the second, lower temperature may mitigate and/or prevent damage to the device layer conventionally caused by exposure to the first temperature during the curing of the crosslinked precursor passivation layer. The method may include using a curing system including a chamber, an infrared source for controlling the first temperature for curing the crosslinked precursor passivation layer, and a temperature control device for controlling the second, lower temperature of the device layer.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qin Yuan, Jun Liu
  • Patent number: 10276513
    Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Szu-Yu Wang, Chung-Yi Yu
  • Patent number: 10263040
    Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
  • Patent number: 10263036
    Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Asif Khan, Raseong Kim, Tahir Ghani, Ian A. Young
  • Patent number: 10255961
    Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 9, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Han-Jong Chia, Sumio Ikegawa, Michael Tran, Jon Slaughter
  • Patent number: 10256288
    Abstract: A nonvolatile memory device can be manufactured without adding any major modification to a structure and component elements of a conventional MOS type silicon device, and is realized without deteriorating an electrical characteristic of an insulating-film/semiconductor interface and on the basis of a new operational principle. The nonvolatile memory device 10 is a capacitor configured by a metal electrode 16, two kinds of insulating films 13 and 15, and an interface structure of an insulating film 12/semiconductor 11, and has a MIS structure of providing a monolayer-level O-M1-O layer 14 to an insulating-film 13/semiconductor 15 interface. The nonvolatile memory device 10 realizes a nonvolatile information storage operation by changing strength or polarities of interface dipoles induced near the O-M1-O layer 14 through electrical stimulation applied from a gate electrode.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 9, 2019
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Noriyuki Miyata
  • Patent number: 10249765
    Abstract: To provide a highly reliable semiconductor device that is suitable for miniaturization and higher density. A semiconductor device includes a first electrode including a protruding portion, a first insulator over the protruding portion, a second insulator covering the first electrode and the first insulator, and a second electrode over the second insulator. The second electrode includes a first region which overlaps with the first electrode with the first insulator and the second insulator provided therebetween and a second region which overlaps with the first electrode with the second insulator provided therebetween. The peripheral portion of the second electrode is provided in the first region.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Patent number: 10249366
    Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 2, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Makoto Kitagawa, Tomohito Tsushima, Wataru Otsuka, Takafumi Kunihiro
  • Patent number: 10243134
    Abstract: An object is to cause a piezoelectric film to perform a piezoelectric operation at a higher voltage than the conventional piezoelectric film. An aspect of the present invention is a piezoelectric film, wherein a voltage at which a piezoelectric butterfly curve that is a result obtained by measuring a piezoelectric property of a piezoelectric film takes a minimum value is larger by 2 V or more than a coercive voltage of a hysteresis curve that is a result obtained by measuring a hysteresis property of said piezoelectric film. The piezoelectric film includes an anti-ferroelectric film, and a ferroelectric film formed on the anti-ferroelectric film.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: March 26, 2019
    Assignee: ADVANCED MATERIAL TECHNOLOGIES, INC.
    Inventors: Takeshi Kijima, Yasuaki Hamada, Takeshi Nomura
  • Patent number: 10229723
    Abstract: A spin orbit torque magnetoresistive random access memory (SOT MRAM) cell includes a magnetic tunnel junction that contains a free layer having two bi-stable magnetization directions, a reference magnetic layer having a fixed magnetization direction, and a tunnel barrier layer located between the free layer and the reference layer, and a nonmagnetic spin Hall effect layer. The spin Hall effect layer may include an alternating stack of beta phase tungsten layers and noble metal nonmagnetic dusting layers. Alternatively or in addition, a hafnium layer may be located between the nonmagnetic spin Hall effect layer and the free layer.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: March 12, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Young-Suk Choi, Brian York, Neil Smith
  • Patent number: 10230044
    Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30× that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: March 12, 2019
    Assignee: Headway Technologies, Inc.
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Patent number: 10229727
    Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kiyotake Sakurai, Yasushi Matsubara
  • Patent number: 10229921
    Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10224238
    Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 5, 2019
    Assignee: Apple Inc.
    Inventors: Chang Ming Lu, Chia-Yu Chen, Chih Pang Chang, Ching-Sang Chuang, Hung-Che Ting, Jung Yen Huang, Sheng Hui Shen, Shih Chang Chang, Tsung-Hsiang Shih, Yu-Wen Liu, Yu Hung Chen, Kai-Chieh Wu, Lun Tsai, Takahide Ishii, Chung-Wang Lee, Hsing-Chuan Wang, Chin Wei Hsu, Fu-Yu Teng
  • Patent number: 10224199
    Abstract: A method of exchanging or transforming end groups in and/or improving the ferroelectric properties of a PVDF-TrFE co-polymer is disclosed. A bulky or chemically dissimilar end group, such as an iodine, sulfate, aldehyde or carboxylic acid end group, may be transformed to a hydrogen, fluorine or chlorine atom. A method of making a PVDF-TrFE co-polymer is disclosed, including polymerizing a mixture of VDF and TrFE using an initiator, and transforming a bulky or chemically dissimilar end group to a hydrogen, fluorine or chlorine atom. A PVDF-TrFE co-polymer or other fluorinated alkene polymer is also disclosed. The co-polymer may be used as a ferroelectric, electromechanical, piezoelectric or dielectric material in an electronic device.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: March 5, 2019
    Inventors: Jakob Nilsson, Christian Brox-Nilsen
  • Patent number: 10224370
    Abstract: A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 5, 2019
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Wei Lu
  • Patent number: 10217522
    Abstract: In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: February 26, 2019
    Assignee: Regents of the University of Minnesota
    Inventors: Jian-Ping Wang, Mahdi Jamali, Sachin S. Sapatnekar, Meghna G. Mankalale, Zhaoxin Liang, Angeline Klemm Smith, Mahendra DC, Hyung-il Kim, Zhengyang Zhao
  • Patent number: 10203380
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignees: SK Hynix Inc., Toshiba Memory Corporation
    Inventors: Ku-Youl Jung, Guk-Cheon Kim, Toshihiko Nagase, Daisuke Watanabe, Won-Joon Choi, Youngmin Eeh, Kazuya Sawada
  • Patent number: 10204742
    Abstract: A variable capacitance element includes a variable capacitance layer made of a dielectric material, an electrode to obtain electrostatic capacitance in the variable capacitance layer, insulating elements that face each other via the variable capacitance layer, and a lead element extending from the electrode, wherein the insulating elements are made of an insulating material which contains Sr and at least one of Ti and Zr.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 12, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Keisuke Kageyama
  • Patent number: 10203830
    Abstract: An electronic device, a manufacturing method and an operation method thereof, and an electronic copy system. Each pixel unit of the electronic device includes a Hall-effect working electrode including a first, second, third and fourth contact position, a thin film transistor, a gate line, a first common line, a second common line, a data line and a sensing line. A line connecting the first contact position and the second contact position intersects a line connecting the third contact position and the fourth contact position; the thin film transistor includes a gate electrode connected with the gate line, a source electrode connected with the data line and a drain electrode, the drain electrode and sensing line are respectively connected with the first and second contact position; the first and second common line are respectively connected with the Hall-effect working electrode through the third and fourth contact position.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 12, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yingwei Liu, Ning Chen
  • Patent number: 10199165
    Abstract: Embodiments of a high-permittivity, low-leakage energy storage device, such as a capacitor, and methods of making the energy storage device are disclosed. The disclosed device includes electrically conductive first and second electrodes, and a sterically constrained dielectric film disposed between the first and second electrodes. The sterically constrained dielectric film comprises a plurality of polymeric molecules, and at least some of the polymeric molecules are bound to the first electrode. The disclosed device may include an insulative layer between the first electrode and the dielectric film and/or between the second electrode and the dielectric film.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: February 5, 2019
    Assignee: Carver Scientific, Inc.
    Inventors: David Reginald Carver, Robert Glenn Carver, Bradford Wesley Fulfer, Jaime Hayes Gibbs, Sean Claudius Hall, Aaron Trent Priddy, Sean William Reynolds
  • Patent number: 10192867
    Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Puneet H. Suvarna, Hiroaki Niimi, Steven J. Bentley, Ali Razavieh
  • Patent number: 10193059
    Abstract: A perpendicularly magnetized spin-orbit magnetic device including a heavy metal layer, a magnetic tunnel junction, a first antiferromagnetic layer, a first block layer and a first stray field applying layer is provided. The magnetic tunnel junction is disposed on the heavy metal layer. The first block layer is disposed between the magnetic tunnel junction and the first antiferromagnetic layer. The first stray field applying layer is disposed between the first antiferromagnetic layer and the first block layer. The first stray field applying layer provides a stray magnetic field parallel to a film plane. The first antiferromagnetic layer contacts the first stray field applying layer to define the direction of the magnetic moment in the first stray field applying layer.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: January 29, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Hsin-Han Lee, Shan-Yi Yang, Yu-Sheng Chen, Yao-Jen Chang
  • Patent number: 10186570
    Abstract: A high dielectric constant (k?40), low leakage current (?10?6 A/cm2 at 0.6 nm or lower equivalent oxide thickness) non-crystalline metal oxide is described, including an oxide of two or more compatible metals selected from the group consisting of bismuth, tantalum, niobium, barium, strontium, calcium, magnesium, titanium, zirconium, hafnium, tin, and lanthanide series metals. Metal oxides of such type may be formed with relative proportions of constituent metals being varied along a thickness of such oxides, to enhance their stability. The metal oxide may be readily made by a disclosed atomic layer deposition process, to provide a metal oxide dielectric material that is usefully employed in DRAM and other microelectronic devices.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: January 22, 2019
    Assignee: Entegris, Inc.
    Inventors: Bryan C. Hendrix, Philip S. H. Chen, Weimin Li, Woosung Jang, Dingkai Guo
  • Patent number: 10186525
    Abstract: The present invention provides a circuit board having excellent productivity, particularly a circuit board having excellent productivity with respect to a semiconductor layer and source layer forming step, a display device, and a process for producing a circuit board. The circuit board of the present invention is a circuit board including an oxide semiconductor layer and an electrode connected to the oxide semiconductor layer, wherein the electrode is formed by essentially laminating a layer made of a metal other than copper and a layer containing copper.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 22, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yuichi Saito, Yohsuke Kanzaki, Yudai Takanishi, Tetsuya Okamoto, Yoshiki Nakatani, Yoshimasa Chikama
  • Patent number: 10180341
    Abstract: A multi-layer wireless sensor construct is provided. The construct includes a first dielectric layer adapted to be attached to a portion of a first surface of an electrically-conductive material. A layer of mu metal is provided on the first dielectric layer. A second dielectric layer is provided on the layer of mu metal. An electrical conductor is provided on the second dielectric layer wherein the second dielectric layer separates the electrical conductor from the layer of mu metal. The electrical conductor has first and second ends and is shaped to form an unconnected open-circuit that, in the presence of a time-varying magnetic field, resonates to generate a harmonic magnetic field response having a frequency, amplitude and bandwidth.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 15, 2019
    Assignee: THE UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF NASA
    Inventors: Kenneth L. Dudley, George N. Szatkowski, Chuantong Wang, Laura J. Smith, Larry A. Ticatch, Truong X. Nguyen, Jay J. Ely, Sandra V. Koppen
  • Patent number: 10181461
    Abstract: A capacitor includes a body including a substrate having first and second capacitor regions, and first to third terminal electrodes disposed on an external surface of the body. The first capacitor region includes a plurality of first trenches, and a first capacitor layer disposed on one surface of the substrate and in the first trenches in the first capacitor region and including at least one first dielectric layer and first and second electrodes disposed with the at least one first dielectric layer interposed therebetween. The second capacitor region includes a plurality of second trenches, and a second capacitor layer disposed on one surface of the substrate and the second trenches in the second capacitor region and including at least one second dielectric layer and third and fourth electrodes disposed with the at least one second dielectric layer interposed therebetween. The second capacitor layer has a specific surface area greater than that of the first capacitor layer.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 15, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: No Il Park, In Young Kang, Hyun Ho Shin, Seung Mo Lim, Jeong Hoon Ryou
  • Patent number: 10177197
    Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic spacer layer between reference and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a length in a first direction, a width in a second direction perpendicular to the first direction, an exchange stiffness and an aspect ratio equal to the length divided by the width. The aspect ratio is greater than one. The exchange stiffness is not less than 2×10?6 erg/cm.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dmytro Apalkov, Shuxia Wang, Jang-Eun Lee
  • Patent number: 10170697
    Abstract: Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Hiroyuki Miyazoe
  • Patent number: 10170692
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices having an integrated magnetic tunnel junction (MTJ), and relates to methods of fabricating the semiconductor devices. In one aspect, a semiconductor device includes a stack including successive layers of: a first metallization layer, a first dielectric layer, a second metallization layer, a second dielectric layer, and a third metallization layer. A magnetic tunnel junction (MTJ) device is formed in the first dielectric layer and in the second metallization layer and electrically connected to a first metallization layer and the third metallization layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Gouri Sankar Kar, Jürgen Bömmels, Davide Crotti
  • Patent number: 10163661
    Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 10158014
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 18, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Ming-Han Liao, Minghwei Hong