With Ferroelectric Material Layer Patents (Class 257/295)
  • Patent number: 10784374
    Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10784441
    Abstract: A perpendicularly magnetized spin-orbit magnetic device including a heavy metal layer, a magnetic tunnel junction, a first antiferromagnetic layer, a first block layer and a first stray field applying layer is provided. The magnetic tunnel junction is disposed on the heavy metal layer. The first block layer is disposed between the magnetic tunnel junction and the first antiferromagnetic layer. The first stray field applying layer is disposed between the first antiferromagnetic layer and the first block layer. The magnetic tunnel junction comprises a free layer, a tunneling barrier layer, and pinned layer. The tunneling barrier layer is disposed on the free layer. The pinned layer is disposed on the tunneling barrier layer. A film plane area of the free layer is greater than a film plane area of the tunneling barrier layer and a film plane area of the pinned layer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 22, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Hsin-Han Lee, Shan-Yi Yang, Yao-Jen Chang, I-Jung Wang, Jeng-Hua Wei
  • Patent number: 10784351
    Abstract: A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 22, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yen Lin, Si-Chen Lee, Samuel C. Pan, Kuan-Chao Chen
  • Patent number: 10783932
    Abstract: To provide a magnetic memory for storing multi-level information capable of reading while sufficiently securing a read margin. Provided is a magnetic memory including: first and second magnetic storage elements that are provided between a first wiring and a second wiring crossing each other, and are electrically connected in series; a third wiring electrically connected between the first and second magnetic storage elements; a first determination unit that determines a magnetization state of the first magnetic storage element on the basis of a current flowing to the first magnetic storage element through the third wiring; and a second determination unit that determines a magnetization state of the second magnetic storage element on the basis of a current flowing to the first and second magnetic storage elements through the first wiring, in which the determination state of the second determination unit is changed on the basis of the determination result of the first determination unit.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 22, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Hiroyuki Uchida, Yo Sato, Naoki Hase
  • Patent number: 10784440
    Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huang-Wen Tseng, Cheng-Chou Wu, Che-Jui Chang
  • Patent number: 10777248
    Abstract: A magnetoresistive random access memory (MRAM) memory cell comprises a pinned layer having fixed direction of magnetization that is perpendicular to a plane of the pinned layer, a first free layer having a direction of magnetization that can be switched and is perpendicular to a plane of the first free layer, a tunnel barrier positioned between the pinned layer and the first free layer, a second free layer having a direction of magnetization that can be switched, and a spacer layer positioned between the first free layer and the second free layer. Temperature dependence of coercivity of the second free layer is greater than temperature dependence of coercivity of the first free layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 15, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Goran Mihajlovic, Neil Smith, Michael Grobis, Michael Tran
  • Patent number: 10777247
    Abstract: A technique relates to a magnetic device. A configuration in a memory layer of the magnetic device is adjusted, the configuration affecting stochastic fluctuations in a free magnetic layer of a magnetic tunnel junction coupled to the memory layer. The stochastic fluctuations are used to define a random number according to the configuration in the memory layer.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jonathan Zanhong Sun
  • Patent number: 10777355
    Abstract: [Object] provide a dielectric composition with high voltage resistance and favorable reliability, and an electronic component using the dielectric composition. [Solving Means] A dielectric composition contains, as a main component, a tungsten bronze type composite oxide represented by a chemical formula (Sr1.00?s?tBasCat)6.00?xRx(Ti1.00?aZra)x+2.00(Nb1.00?bTab)8.00?xO30.00, in which the R is at least one element selected from Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and s, t, x, a, and b satisfy 0.70?s?1.00, 0?t?0.30, 0.70?s+t?1.00, 0?x?0.50, 0.10?a?1.00, and 0?h?1.00. At least one or more elements selected from Mn, Mg, Co, V, W, Mo, Si, Li, B, and Al are contained as a sub component in 0.10 mol or more and 20.00 mol or less with respect to 100 mol of the main component.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: September 15, 2020
    Assignee: TDK CORPORATION
    Inventors: Sanshiro Aman, Hiroki Akiba, Keiko Takeuchi
  • Patent number: 10777354
    Abstract: A dielectric composition with high voltage resistance and favorable reliability, and an electronic component using the dielectric composition. The dielectric composition contains, as a main component, a tungsten bronze type composite oxide represented by a chemical formula (Sr1.00?s?tBasCat)6.00?xRx(Ti1.00?aZra)x+2.00(Nb1.00?bTab)8.00?xO30.00 in which the R is at least one element selected from Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and s, t, x, a, and b satisfy 0.50?s?1.00, 0?t?0.50, 0.50?s+t?1.00, 0.50<x?1.50, 0.30?a?1.00, and 0?b?1.00. At least one or more elements selected from Mn, Mg, Co, V, W, Mo, Si, Li, B, and Al are contained as a sub component in 0.10 mol or more and 20.00 mol or less with respect to 100 mol of the main component.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: September 15, 2020
    Assignee: TDK CORPORATION
    Inventors: Sanshiro Aman, Hiroki Akiba, Keiko Takeuchi
  • Patent number: 10770653
    Abstract: A method is presented for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region. The method includes forming protective layers in the MRAM region to preserve integrity of underlying dielectric layers, forming a bottom electrode in direct contact with the protective layers, and constructing an MRAM pillar over the bottom electrode, wherein the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Penny, Marc A. Bergendahl, Michael Rizzolo, Christopher J. Waskiewicz
  • Patent number: 10770652
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The method first provides an electrically conductive structure embedded in an interconnect dielectric material layer of a magnetoresistive random access memory device. A conductive landing pad is located on a surface of the electrically conductive structure. A multilayered magnetic tunnel junction (MTJ) structure and an MTJ cap layer is formed on the landing pad. Then there is formed a first conductive layer on top the MTJ cap layer and a second conductive metal layer formed on top the first conductive layer. A pillar mask structure is then patterned and formed on the second conductive layer. The resulting structure is subject to lithographic patterning and etching to form a patterned bilayer metal hardmask pillar structure on top the MTJ cap layer. Subsequent etch processing forms an MTJ stack having sidewalls aligned to the patterned bilayer metal hardmask pillar.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nathan P. Marchack, Bruce B. Doris, Pouya Hashemi
  • Patent number: 10770457
    Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Robert S. Jones, III, Xiankun Jin
  • Patent number: 10770509
    Abstract: According to one embodiment, a magnetic device includes a first memory cell including a magnetoresistive effect element, a selector, and a first barrier material disposed between the selector and the magnetoresistive effect element, wherein the first barrier material has a thermal conductivity of 5 W/mK or lower.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Furuhashi
  • Patent number: 10759709
    Abstract: A dielectric composition with high voltage resistance and favorable reliability, and an electronic component using the dielectric composition. The dielectric composition contains, as a main component, a tungsten bronze type composite oxide represented by a chemical formula (Sr1.00-(s+t)BasCat)6.00-xRx(Ti1.00-aZra)x+2.00(Nb1.00-bTab)8.00-xO30.00, in which the R is at least one element selected from Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and s, t, x, a, and b satisfy 0.50?s?1.00, 0?t?0.30, 0.50?s+t?1.00, 1.50<x?3.00, 0.20?a?1.00, and 0?b?1.00. At least one selected from Mn, Mg, Co, V, W, Mo, Si, Li, B, and Al is contained as a sub component in 0.10 mol or more and 20.00 mol or less with respect to 100 mol of the main component.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: September 1, 2020
    Assignee: TDK CORPORATION
    Inventors: Hiroki Akiba, Sanshiro Aman, Keiko Takeuchi
  • Patent number: 10756256
    Abstract: A magnetoresistive random access memory and a method for manufacturing the same are provided, with which a stress layer covers a part of the protective layer along a direction of a current in the spin-orbit coupling layer, so that a stress is generated on the part of the magnetic layer locally due to the stress layer, thus a lateral asymmetric structure is formed in a direction perpendicular to the current source. In a case that a current is supplied to the spin-orbit coupling layer, the spin-orbit coupling effect in the magnetic layer is asymmetric due to the stress on the part of the magnetic layer, thereby realizing a deterministic switching of the magnetic moment under the function of the stress.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 25, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Meiyin Yang, Jun Luo, Tengzhi Yang, Jing Xu
  • Patent number: 10756261
    Abstract: The invention provides a magnetoresistance element with a configuration such that a stable switching action is possible with a current flowing in response to the application of a unipolar electrical pulse, and a non-volatile semiconductor storage device using the magnetoresistance element. A magnetoresistance element 1-1 includes a magnetic tunnel junction portion 13 configured by sequentially stacking a perpendicularly magnetized first magnetic body 22, an insulation layer 21, and a perpendicularly magnetized second magnetic body 200. The second magnetic body 200 has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer 21 side interface.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 25, 2020
    Assignee: III HOLDINGS 3, LTD.
    Inventors: Michiya Yamada, Yasuchi Ogimoto
  • Patent number: 10738394
    Abstract: The present invention discloses a molecular beam epitaxy under vector strong magnetic field and an in-situ characterization apparatus thereof. The apparatus mainly consists of an inverted T-shaped ultrahigh vacuum growth and characterization chamber with a compact structure and a strong magnet. The inverted T-shaped vacuum chamber portion, which disposed in the room-temperature chamber of the strong magnet, includes a compact epitaxial growth sample stage, a device capable of rotating angle between the growth and magnetic field directions, and an in-situ characterization apparatus. The portion disposed below the strong magnet includes a molecular beam source component such as evaporation source, plasma source etc., and a vacuum-pumping system.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: August 11, 2020
    Inventors: Junyong Kang, Chunmiao Zhang, Zhiming Wu, Ting Chen, Na Gao, Yaping Wu, Heng Li
  • Patent number: 10741417
    Abstract: A method for forming an interconnect structure is provided. The method includes: forming a dielectric layer on a substrate, and forming an opening in the dielectric layer; forming a first metal layer, a second metal layer, and a third metal layer sequentially over the dielectric layer. The opening of the dielectric layer is filled with the first metal layer to form a conductive via. The method also includes: performing one or multiple etch operation to etch the first metal layer, the second metal layer, and the third metal layer, so as to form a metal line corresponding to the first metal layer, an intermediate metal layer corresponding to the second metal layer, and a metal pillar corresponding to the third metal layer. In particular, the width of the metal line is greater than the width of the metal pillar.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 10741755
    Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
  • Patent number: 10741752
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekharan Kothandaraman, John R. Sporre
  • Patent number: 10734578
    Abstract: A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a lateral barrier layer connected to the bottom contact, the memory layer, and the conductive top electrode, where the lateral barrier layer is configured to substantially prevent conduction of ions or vacancies from the bottom contact, the memory layer, and the conductive top electrode to the lateral barrier layer.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 4, 2020
    Assignee: 4DS MEMORY, LIMITED
    Inventors: Seshubabu Desu, Michael Van Buskirk
  • Patent number: 10734409
    Abstract: A semiconductor device includes a stack structure having a plurality of interlayer insulation layers and a plurality of gate electrode layers which are alternately stacked on a substrate, a ferroelectric insulation layer and a channel layer sequentially stacked on a sidewall of a trench that penetrates the stack structure, and a capping oxide pattern disposed between the ferroelectric insulation layer and each of the plurality of interlayer insulation layers. The capping oxide pattern and the ferroelectric insulation layer include the same metal oxide material.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10734053
    Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive member includes a first layer. The first layer includes at least one selected from the group consisting of HfN having a NaCl structure, HfN having a fcc structure, and HfC having a NaCl structure. The first magnetic layer is separated from the first layer in a first direction. The second magnetic layer is provided between the first layer and the first magnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 4, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mizue Ishikawa, Yushi Kato, Soichi Oikawa, Hiroaki Yoda
  • Patent number: 10726916
    Abstract: A device is disclosed that includes a driver and a plurality of resistive memory cells each being electrically connected to the driver through a first line. The driver has a variable resistance corresponding to various locations of a conducted resistive memory cell, relative to the driver, in the plurality of resistive memory cells.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chung-Cheng Chou
  • Patent number: 10727251
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rounded shaped transistors and methods of manufacture. The structure includes a gate structure composed of a metal electrode and a rounded ferroelectric material which overlaps an active area in a width direction into an isolation region.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stefan Dünkel, Johannes Müller, Lars Müller-Meskamp
  • Patent number: 10728478
    Abstract: An electronic device includes a driving circuit suitable for driving an output node with an input voltage signal based on a control voltage applied to a control node, a boost circuit suitable for boosting voltage of the output node based on an output boost signal, and a compensating circuit suitable for applying the control voltage to the control node based on control signals to compensate for voltage drop caused by the driving circuit.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hyinx Inc.
    Inventor: Tae-Gyu Kim
  • Patent number: 10727077
    Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Patent number: 10720437
    Abstract: A ferroelectric memory device according to an embodiment includes a base conduction layer, a channel layer extending in a vertical direction from the base conduction layer, a ferroelectric layer disposed on the channel layer, a plurality of ferroelectric memory cell transistor stacked in a vertical direction on the base conduction layer, a control transistor disposed over the plurality of ferroelectric memory cell transistors, and a bit line pattern electrically connected to the channel layer.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10714500
    Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Yunseong Lee, Sanghyun Jo
  • Patent number: 10712399
    Abstract: A MLU cell for sensing an external magnetic field, including a magnetic tunnel junction including a sense layer having a sense magnetization adapted to be oriented by the external magnetic field; a reference layer having a reference magnetization; a tunnel barrier layer; a biasing layer having a biasing magnetization and a biasing antiferromagnetic layer pinning the biasing magnetization substantially parallel to the pinned reference magnetization at a low threshold temperature and freeing it at a high threshold temperature. A biasing coupling layer is between the sense layer and the basing layer and configured for magnetically coupling the biasing layer and the sense layer such that the sense magnetization is oriented substantially perpendicular to the pinned biasing magnetization and to the pinned reference magnetization. The present disclosure further concerns a magnetic sensor device for sensing an external magnetic field, including a plurality of the MLU cells.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 14, 2020
    Inventor: Sebastien Bandiera
  • Patent number: 10714679
    Abstract: An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Zhongjian Teng, Yu-Jen Wang
  • Patent number: 10714466
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Patent number: 10714438
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinchan Ahn, Won-young Kim, Chanho Lee
  • Patent number: 10700093
    Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 30, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Alan Kalitsov, Derek Stewart, Daniel Bedau, Gerardo Bertero
  • Patent number: 10692569
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 23, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag, Mourad El Baraji
  • Patent number: 10693058
    Abstract: A magnetic tunnel junction device and a magnetic memory device. The magnetic tunnel junction device includes a magnetic tunnel junction including a fixed magnetic body, an insulator, and a free magnetic body sequentially stacked and a conducting wire disposed adjacent the free magnetic body of the magnetic tunnel junction to apply in-plane current. The fixed magnetic body has a fixed magnetization direction and is a thin film including a material magnetized directionally perpendicular to a film surface. The free magnetic body has a structure of [auxiliary free magnetic layer/free non-magnetic layer]N/main free magnetic layer, where N is a positive integer greater than or equal to 2 and indicates that an [auxiliary free magnetic layers/free non-magnetic layers] structure is stacked repeatedly N times.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 23, 2020
    Assignee: Korea University Research and Business Foundation
    Inventor: Kyung-Jin Lee
  • Patent number: 10692962
    Abstract: A display panel includes a first conductive layer including a first layer, a second layer, and a third layer sequentially stacked, and a second conductive layer on the first conductive layer and contacting the third layer. The first layer includes a first metal. The second layer includes the first metal and oxygen in a first composition ratio. The third layer includes the first metal and oxygen at a second composition ratio. The second composition ratio is smaller than the first composition ratio. Conductivity of the third layer is higher than conductivity of the second layer. The first composition ratio is a ratio of an atom percent of the first metal to an atom percent of oxygen in the second layer. The second composition ratio is a ratio of an atom percent of the first metal to an atom percent of oxygen in the third layer.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki Hyun Kim, Young Gil Park, Sung Chan Jo
  • Patent number: 10686043
    Abstract: [Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 16, 2020
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM R&D CORPORATION
    Inventors: Shigeki Sakai, Mitsue Takahashi, Masaki Kusuhara, Masayuki Toda, Masaru Umeda, Yoshikazu Sasaki
  • Patent number: 10685869
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first conductive pattern and a conductive mask disposed over the first conductive pattern. The semiconductor device further includes a second conductive pattern disposed over the conductive mask, and electrically connecting with the first conductive pattern through the conductive mask. The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern. A method for forming the semiconductor device is also provided.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pin-Ren Dai, Hsi-Wen Tien, Wei-Hao Liao, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 10686040
    Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Takashi Ando, Xiao Sun, Jin Ping Han, Vijay Narayanan
  • Patent number: 10686072
    Abstract: A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 16, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yu-Hung Liao, Samuel C. Pan, Sheng-Ting Fan, Min-Hung Lee, Chee-Wee Liu
  • Patent number: 10680170
    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Andrea Ghetti
  • Patent number: 10680071
    Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 9, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tadashi Yamaguchi
  • Patent number: 10680105
    Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin-Ping Han, Ramachandran Muralidhar, Dennis M. Newns, Paul M. Solomon
  • Patent number: 10679794
    Abstract: A plurality of first and second capacitor parts and second capacitor parts are formed on opposed main surfaces of a foil shaped conductive substrate to sandwich the conductive substrate. The first and second capacitor parts are respectively coated with insulative protection layers. Terminal electrodes are respectively formed on main surfaces of the protection layers. The terminal electrodes and conductive parts of the first and second capacitor parts are respectively electrically connected via first via conductors and the terminal electrodes and the conductive substrate 1 are electrically connected to second via conductors.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: June 9, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuo Fujii, Hiromasa Saeki
  • Patent number: 10672978
    Abstract: In a method of manufacturing a variable resistance memory device, an MTJ structure layer is formed on a substrate. The MTJ structure layer is etched in an etching chamber to form an MTJ structure. The substrate having the MTJ structure thereon is transferred to a deposition chamber through a transfer chamber. A protection layer covering a sidewall of the MTJ structure is formed in the deposition chamber. The etching chamber, the transfer chamber, and the deposition chamber are kept in a high vacuum state equal to or more than about 10?8 Torr.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Lee, Ju-Hyun Kim, Jung-Hwan Park, Se-Chung Oh, Dong-Kyu Lee, Kyung-Il Hong
  • Patent number: 10672983
    Abstract: A method of forming a resistive random access memory (ReRAM) device is provided. The method includes depositing a lower cap layer on a substrate, depositing a dielectric memory layer on the lower cap layer, and depositing an upper cap layer on the dielectric memory layer. The method further includes removing portions of the lower cap layer to form a lower cap slab, dielectric memory layer to form a dielectric memory slab on the lower cap slab, and upper cap layer to form an upper cap slab on the dielectric memory slab, wherein the lower cap slab, dielectric memory slab, and upper cap slab form a resistive memory element.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10672894
    Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: June 2, 2020
    Assignee: IMEC vzw
    Inventors: Jan Van Houdt, Hanns Christoph Adelmann, Han Chung Lin
  • Patent number: 10665775
    Abstract: There is disclosed an information storage element including a first layer including a ferromagnetic layer with a magnetization direction perpendicular to a film face; an insulation layer coupled to the first layer; and a second layer coupled to the insulation layer opposite the first layer, the second layer including a fixed magnetization so as to be capable of serving as a reference of the first layer. The first layer is capable of storing information according to a magnetization state of a magnetic material, and the magnetization state is configured to be changed by a spin injection. A magnitude of an effective diamagnetic field which the first layer receives is smaller than a saturated magnetization amount of the first layer.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: May 26, 2020
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Hiroyuki Uchida, Tetsuya Asayama
  • Patent number: 10665283
    Abstract: A semiconductor storage element includes a first transistor including a gate insulator film at least partially formed by a ferroelectric material, a second transistor connecting with a gate of the first transistor at one of a source or a drain, and a third transistor connecting with a drain of the first transistor at one of a source or a drain. The semiconductor storage element is arranged in a matrix, and each of the second and third transistors connects with a word line at a gate and connects with a bit line at another one of the source or the drain.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 26, 2020
    Assignee: SONY CORPORATION
    Inventor: Masanori Tsukamoto