Tunneling Through Region Of Reduced Conductivity Patents (Class 257/30)
  • Patent number: 10283693
    Abstract: Structures and techniques, using superconducting Josephson-junction based circuits, to directly engineer physical multiqubit (or “many-qubit”) interactions in a non-perturbative manner. In one embodiment, a system for multiqubit interaction includes: a multispin coupler including a plurality of loops, each loop having a pair of Josephson junctions; and a plurality of qubits each inductively coupled to the multispin coupler.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: May 7, 2019
    Assignee: Massachusetts Institute of Technology
    Inventor: Andrew J. Kerman
  • Patent number: 10205014
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 12, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 10187065
    Abstract: Structures and techniques, using superconducting Josephson-junction based circuits, to directly engineer physical multiqubit (or “many-qubit”) interactions in a non-perturbative manner. In one embodiment, a system for multiqubit interaction includes: a multispin coupler including a plurality of loops, each loop having a pair of Josephson junctions; and a plurality of qubits each inductively coupled to the multispin coupler.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: January 22, 2019
    Assignee: Massachusetts Institute of Technology
    Inventor: Andrew J. Kerman
  • Patent number: 10170681
    Abstract: A qubit may be formed by forming a Josephson junction between two capacitive plates. The Josephson junction may be annealed with a thermal source. The thermal source may be a laser that generates a Gaussian beam. An axicon lens may be exposed to the Gaussian beam. Annealing the Josephson junction may alter the resistance of the Josephson junction.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Jason S. Orcutt
  • Patent number: 10164183
    Abstract: A semiconductor device includes at least one bottom electrode, a resistive layer, and a top electrode. The bottom electrode has two opposite sidewalls. The resistive layer is disposed on the bottom electrode, extends past at least one of the two opposite sidewalls of the at least one bottom electrode, and has a variable resistance. The resistive layer is disposed on the bottom electrode and extends past at least one of the two opposite sidewalls of the at least one bottom electrode.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Yen Chou, Ching-Pei Hsieh
  • Patent number: 10115891
    Abstract: According to one embodiment, a magnetoresistive memory device includes bottom electrodes provided on a substrate, a magnetoresistive element provided on each of the bottom electrodes, a top electrode provided on each of the magnetoresistive elements, an insulating film provided on sides of the bottom electrode, the magnetoresistive element and, the top electrode, and a magnetic layer provided on the top electrode, the magnetic layer extending on the insulating film to connect a plurality of those of the top electrodes.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyuki Kanaya
  • Patent number: 9983275
    Abstract: Method for sensing an external magnetic field using a magnetic sensor cell including: a magnetic tunnel junction including a reference layer having a reference magnetization oriented parallel to the plane of the reference layer, a sense layer having a sense magnetization, and a tunnel barrier layer between the sense and reference layers. A field line is configured for passing a field current for providing a sense magnetic field adapted for aligning the sense magnetization. The sense layer magnetization is orientable between a direction parallel to the plane of the sense layer and a direction perpendicular to the plane of the sense layer when the sense magnetic field is provided. The external magnetic field includes an in-plane component oriented parallel to the plane of the sense layer and an out-of-plane component perpendicular to the plane of the sense layer. The method includes sensing the out-of-plane component; and sensing the in-plane component.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: May 29, 2018
    Assignee: CROCUS TECHNOLOGY SA
    Inventor: Sebastien Bandiera
  • Patent number: 9912334
    Abstract: According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 6, 2018
    Assignee: ARM Ltd.
    Inventors: Shidhartha Das, Anand Savanth, David Bull
  • Patent number: 9873815
    Abstract: A polymer includes a first moiety represented by Chemical Formula 1, and a second moiety including a substituted or unsubstituted C6 to C60 cyclic group, a substituted or unsubstituted C6 to C60 hetero cyclic group, or a combination thereof: In Chemical Formula 1, X is phosphorus (P), nitrogen (N), boron (B), or P?O, Y1 and Y2 are independently hydrogen or a moiety including at least one substituted or unsubstituted benzene ring, provided that at least one of Y1 and Y2 is the moiety including at least one substituted or unsubstituted benzene ring, Y3 is another moiety including at least one substituted or unsubstituted benzene ring, and * is a linking point.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Soohyoun Mun, Hyo Young Kwon, Ran Namgung, Younhee Nam, Hyunji Song
  • Patent number: 9806710
    Abstract: A voltage-controlled magnetic based device is described that includes a magnetic insulator; a topological insulator adjacent the magnetic insulator; and magnetic dopants within the topological insulator. The magnetic dopants are located within an edge region of the topological insulator to inhibit charge current flow in the topological insulator during a switching operation using an applied electric field generating by applying a switching voltage across two electrodes at opposite sides of the topological insulator. Power dissipation due to carrier-based currents can be avoided or at least minimized by the magnetic dopants at the edges of the topological insulator.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 31, 2017
    Assignee: UNIVERSITY OF IOWA RESEARCH FOUNDATION
    Inventor: Michael Flatté
  • Patent number: 9721632
    Abstract: Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.
    Type: Grant
    Filed: January 14, 2017
    Date of Patent: August 1, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Dimitri Houssameddine, Jon Slaughter
  • Patent number: 9710758
    Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 18, 2017
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Mohammad H. S. Amin, Richard G. Harris, Trevor Michael Lanting, Mark W. Johnson, Jeremy P. Hilton, Emile M. Hoskinson
  • Patent number: 9621161
    Abstract: According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 11, 2017
    Assignee: ARM Ltd.
    Inventors: Shidhartha Das, Anand Savanth, David Bull
  • Patent number: 9564331
    Abstract: A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: February 7, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Shenqing Fang, Tung-Sheng Chen, Tim Thurgate, Di Li
  • Patent number: 9548095
    Abstract: Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: January 17, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Dimitri Houssameddine, Jon Slaughter
  • Patent number: 9537092
    Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a lower electrode overlying a substrate, an insulating layer overlying the lower electrode, and an upper electrode overlying the insulating layer. The lower electrode, the insulating layer, and the upper electrode form a stack having a side surface. A phase change spacer is adjacent to the side surface, where the phase change spacer is electrically connected to the lower electrode and the upper electrode.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zheng Zou, Alex See, Shyue Seng Tan
  • Patent number: 9478733
    Abstract: A MTJ for a spintronic device includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 25, 2016
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Patent number: 9472754
    Abstract: Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guohan Hu, Daniel C. Worledge
  • Patent number: 9443934
    Abstract: To provide a transistor having high field effect mobility. To provide a transistor having stable electrical characteristics. To provide a transistor having low off-state current (current in an off state). To provide a semiconductor device including the transistor. The semiconductor device includes a semiconductor; a source electrode and a drain electrode including regions in contact with a top surface and side surfaces of the semiconductor; a gate insulating film including a region in contact with the semiconductor; and a gate electrode including a region facing the semiconductor with the gate insulating film provided therebetween. A length of a region of the semiconductor, which is not in contact with the source and drain electrodes, is shorter than a length of a region of the semiconductor, which is in contact with the source and drain electrodes, in a channel width direction.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 13, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kobayashi, Daisuke Matsubayashi
  • Patent number: 9443200
    Abstract: A method for interaction-free entanglement of quantum bits in quantum computers, in which the quantum bits to be entangled are available in the state ?44 with arbitrarily real phases ? and ? as an elementary quantum system. The two quantum bits (1) and (2) are localized in spatial regions (6) and (6?) and surrounded by switchable sheaths (7) and (7?) preferably a superconductor with the jump temperature TSU. The switchable sheaths, in the activated state, completely displace a global, homogeneous magnetic field Bz from the spatial regions (6) and (6?). In the inactivated state, the switchable sheaths do not shield the spatial regions (6) and (6?). If the switchable sheaths are switched from the activated state into the inactivated state while observing the boundary condition (R3), as a result of this, the two quantum bits (1) and (2) are transferred into the entangled state ??.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: September 13, 2016
    Inventor: Gerhart Schroff
  • Patent number: 9391265
    Abstract: A MTJ for a domain wall motion device includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 12, 2016
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Patent number: 9373778
    Abstract: A MTJ for a spintronic device includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a dipole layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 21, 2016
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Patent number: 9373777
    Abstract: A MTJ for a spintronic device includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 21, 2016
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Patent number: 9365949
    Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ji-Soo Park
  • Patent number: 9362383
    Abstract: A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: June 7, 2016
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9355364
    Abstract: One aspect of the present invention includes a reciprocal quantum logic (RQL) readout system. The system includes an input stage on which a read pulse is provided and an output stage configured to propagate an output pulse. The system also includes an RQL comparator comprising a first Josephson junction and a second Josephson junction that are coupled to a qubit. A bias current switches between a first Josephson junction in a first quantum state of the qubit and a second Josephson junction in a second quantum state of the qubit. The first Josephson junction triggers to provide the output pulse on the output stage in the first quantum state in response to the read pulse and the second Josephson junction triggers to provide no output pulse on the output stage in the second quantum state in response to the read pulse.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 31, 2016
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Donald L. Miller, Ofer Naaman
  • Patent number: 9236520
    Abstract: Techniques for using photo detectors as tunable proximity sensors for detection of target objects and ascertaining their distance from the proximity sensors are disclosed. In one embodiment, the techniques may be realized as a proximity sensor system including a photo detector having a first doped region, a gate, a second doped region and a light absorbing region, a control circuitry for generating a plurality of control signals to be applied to the photo detector, and a signal detector to detect an output signal from the photo detector.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: January 12, 2016
    Assignee: ACTLIGHT S.A.
    Inventors: Serguei Okhonin, Maxim Gureev
  • Publication number: 20150144888
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 28, 2015
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20150144887
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 28, 2015
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Patent number: 9012960
    Abstract: A photo detector comprising a first doped impurity region (adapted to receive a first voltage) disposed in or on a substrate; a body region, juxtaposed the first doped impurity region; a gate (adapted to receive a second voltage) spaced from a first portion of the body region; a light absorbing region, juxtaposed a second portion of the body region, includes a material which, in response to light incident thereon, generates carrier pairs including a first and second type carriers; a contact region (adapted to receive a third voltage) juxtaposed the light absorbing region; wherein, in response to incident light, the gate attracts first type carriers of the carrier pairs to the first portion of the body region which causes second carriers from the first doped impurity region to flow to the contact region, and the contact region attracts second type carriers.
    Type: Grant
    Filed: May 28, 2012
    Date of Patent: April 21, 2015
    Assignee: Actlight, S.A.
    Inventor: Serguei Okhonin
  • Patent number: 9006704
    Abstract: A magnetic element is disclosed wherein first and second interfaces of a free layer with a Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to lower switching current or increase thermal stability in a magnetic tunnel junction (MTJ). In a MTJ with a bottom spin valve configuration where the Hk enhancing layer is an oxide, the capping layer contacting the Hk enhancing layer is selected to have a free energy of oxide formation substantially greater than that of the oxide. The free layer may be a single layer or composite comprised of an Fe rich alloy such as Co20Fe60B20. With a thin free layer, the interfacial perpendicular anisotropy may dominate the shape anisotropy to generate a magnetization perpendicular to the planes of the layers. The magnetic element may be part of a spintronic device or serve as a propagation medium in a domain wall motion device.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: April 14, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru Ying Tong, Witold Kula, Cheng Horng
  • Patent number: 8987702
    Abstract: Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8975123
    Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Ze Zhang
  • Patent number: 8970018
    Abstract: A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Jay M. Gambetta
  • Patent number: 8963156
    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
  • Patent number: 8865537
    Abstract: A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Jay M. Gambetta
  • Patent number: 8852959
    Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Northrup Grumman Systems Corporation
    Inventors: John J. Talvacchio, Erica C. Folk, Sean R. McLaughlin, David J. Phillips
  • Patent number: 8847200
    Abstract: A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 30, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Roy E. Scheuerlein
  • Patent number: 8835203
    Abstract: An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 16, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Hyunho Kim, Seokwoo Lee, Heedong Choi, Sangjin Lee, Seongmoh Seo
  • Patent number: 8742401
    Abstract: A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: June 3, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Steven Sapp, Nathan Kraft, Ashok Challa
  • Patent number: 8722211
    Abstract: A magnetic memory device may include a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer arranged on a substrate. The tunnel barrier layer may include a crystal structure and may be arranged between the first ferromagnetic layer and the second ferromagnetic layer. At least the first ferromagnetic layer may include a first layer in contact with the tunnel barrier layer and a second layer in contact with the first layer, and an orientation of the first layer with respect to the tunnel barrier layer may be greater than an orientation of the second layer with respect to the tunnel barrier layer.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woojin Kim, Jangeun Lee, Sechung Oh, KyungTae Nam, Dae Kyom Kim, Junho Jeong
  • Patent number: 8702929
    Abstract: A system that incorporates teachings of the present disclosure may include, for example, a solid-state selector having a vessel for carrying a liquid medium with one or more molecules surrounded by ions, a solid state conductive structure doped with impurities having one or more through-holes extending between two surfaces of the solid state conductive structure positioned within the liquid medium of the vessel, a voltage source coupled to the solid state conductive structure to selectively stimulate the ions surrounding the one or more molecules to pass through the one or more through-holes. Additional embodiments are disclosed.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 22, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Jean-Pierre Leburton, Gregory Timp, Maria E. Gracheva, Julien Vidal
  • Patent number: 8669598
    Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 11, 2014
    Inventor: Hoon Kim
  • Patent number: 8669599
    Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 11, 2014
    Inventor: Hoon Kim
  • Publication number: 20140054551
    Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.
    Type: Application
    Filed: August 29, 2012
    Publication date: February 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Damon Farmer
  • Patent number: 8654578
    Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: February 18, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Rupert M. Lewis, Ofer Naaman
  • Patent number: 8586968
    Abstract: The present invention provides an organic light emitting device comprising a first electrode, a second electrode, and at least two organic material layers interposed therebetween, including a light emitting layer, wherein the organic material layers comprise at least one layer of a hole injecting layer, a hole transporting layer and a hole injecting and transporting layer, and at least one of the hole injecting layer, the hole transporting layer and the hole injecting and transporting layer comprises a material with a HOMO energy level of ?4 eV or less, and a material with a LUMO energy level of ?4 eV or less, and a process for preparing the same.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: November 19, 2013
    Assignee: LG Chem, Ltd.
    Inventors: Jun-Gi Jang, Chang-Hwan Kim, Dong-Seob Jeong, Sang-Young Jeon, Kong-Kyeom Kim, Wook-Dong Cho, Ji-Eun Kim, Byung-Sun Jeon
  • Patent number: 8575597
    Abstract: The use of liquid metal contacts for devices based on thermotunneling has been investigated. Electric and thermal characteristics of low wetting contact Hg/Si, and high wetting contacts Hg/Cu were determined and compared. Tunneling I-V characteristics for Hg/Si were obtained, while for Hg/Cu, I-V characteristics were ohmic. The tunneling I-V characteristic is explained by the presence of a nanogap between the contact materials. Heat conductance of high wetting and low wetting contacts were compared, using calorimeter measurements. Heat conductance of high wetting contact was 3-4 times more than of low wetting contact. Both electric and thermal characteristics of liquid metal contact indicated that it could be used for thermotunneling devices. To reduce the work function and make liquid metal more suitable for room temperature cooling, Cs was dissolved in liquid Hg. Work function as low as 2.6 eV was obtained.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 5, 2013
    Assignee: Borealis Technical Limited
    Inventors: Avto Tavkhelidze, Leri Tsakadze, Zaza Taliashvili, Larissa Jangidze, Rodney Thomas Cox
  • Patent number: 8569806
    Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: October 29, 2013
    Inventor: Hoon Kim
  • Publication number: 20130270523
    Abstract: A boron or boron containing dusting layer such as CoB or FeB is formed along one or both of top and bottom surfaces of a free layer at interfaces with a tunnel barrier layer and capping layer to improve thermal stability while maintaining other magnetic properties of a MTJ stack. Each dusting layer has a thickness from 0.2 to 20 Angstroms and may be used as deposited, or at temperatures up to 400° C. or higher, or following a subsequent anneal at 400° C. or higher. The free layer may be a single layer of CoFe, Co, CoFeB or CoFeNiB, or may include a non-magnetic insertion layer. The resulting MTJ is suitable for STT-MRAM memory elements or spintronic devices. Perpendicular magnetic anisotropy is maintained in the free layer at temperatures up to 400° C. or higher. Ku enhancement is achieved and the retention time of a memory cell for STT-MRAM designs is increased.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Yu-Jen Wang, Witold Kula, Ru-Ying Tong, Guenole Jan