Abstract: A superconducting device which includes a substrate, multiple niobium leads formed on the substrate, a niobium silicide (NbSix) passivation layer formed on a surface of at least one of the multiple niobium leads, and an aluminum lead formed directly on at least a portion of the NbSix passivation layer such that an interface therebetween is substantially free of oxygen and oxidized material, where the multiple niobium leads and the aluminum lead are constructed to carry a supercurrent while in use.

Abstract: A method of forming a superconductor structure is disclosed. The method comprises forming a superconductor line in a first dielectric layer, forming a resistor with an end coupled to an end of the superconductor line, and forming a second dielectric layer overlying the resistor. The method further comprises etching a tapered opening through the second dielectric layer to the resistor, and performing a contact material fill with a normal metal material to fill the tapered opening and form a normal metal connector coupled to the resistor.

Abstract: A broadband multi-purpose optical device includes a semiconductor layer having a light absorption characteristic, a first active layer having a light absorption band different from a light absorption band of the semiconductor layer, a first two-dimensional (2D) material layer adjacent to the first active layer, and a first interfacial layer configured to control a pinning potential of the semiconductor layer and the first active layer. The broadband multi-purpose optical device may further include at least one second active layer, and may include a tandem structure that further includes at least one second 2D material layer. The first active layer and the second active layer may have different light absorption bands. The broadband multi-purpose optical device may further include a second interfacial layer adjacent to the first 2D material layer.

Abstract: A sensor includes two electrodes and a modulatable electrically conductive channel attached to the two electrodes. The modulatable electrically conductive channel includes a modified, partially double stranded nucleic acid polymer electrically connected to the two electrodes and bridging the space between the two electrodes. The modified, partially double stranded nucleic acid polymer includes two polynucleotide chains partially bonded together, a gap in a first of the polynucleotide chains wherein nucleotide bases are missing, and a plurality of nucleotide bases of a second of the polynucleotide chains exposed at the gap in the first of the polynucleotide chains.

Abstract: The present invention provides with an electron-accepting compound having a structure of the following formula (1):

Abstract: According to an embodiment of the present invention, a system for non-invasively characterizing a qubit device includes a characterization probe chip. The characterization probe chip includes a substrate and a characterization resonator formed on a first surface of the substrate. The characterization resonator includes a superconducting stripline, and a superconducting antenna coupled to an end of the superconducting stripline, the superconducting antenna positioned to align with a qubit on the qubit device being characterized. The characterization probe chip also includes and a superconducting ground plane formed on a second surface of the substrate, the second surface opposing the first surface. In operation, the superconducting antenna is configured to capacitively couple the characterization resonator to the qubit aligned with the superconducting antenna for characterization of the qubit.

Abstract: A method of fabricating a hydrophilic-hydrophobic transformable composite film is provided. The method includes forming a silicon-containing layer on an iron-containing substrate; coating a titanium-containing sol-gel film on the said silicon-containing layer; and heating the iron-containing substrate with the silicon-containing layer and the titanium-containing sol-gel film thereon.

Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: A memristor circuit that can increase a maximum rate of change of a conductance of the memristor circuit while maintaining linearity and symmetry in the change in the conductance is provided. A memristor circuit includes: a first magnetoresistance effect element including a first resistance change unit configured to change a resistance value thereof based on a current flowing therein, a first electrode provided at a first end of the first resistance change unit, and a second electrode provided at a second end of the first resistance change unit; and a first field effect transistor including a gate electrode, the gate electrode being connected to a transmission path between the first electrode connected to a power supply and the power supply.

Abstract: Provided are a light-receiving element which has more capability of detecting wavelengths than that of existing silicon light-receiving elements and a unit pixel of an image sensor by using it. The light-receiving element includes: a light-receiving unit which is floated or connected to external voltage and absorbs light; an oxide film which is formed to come in contact with a side of the light-receiving unit; a source and a drain which stand off the light-receiving unit with the oxide film in between and face each other; a channel which is formed between the source and the drain and forms an electric current between the source and the drain; and a wavelength expanding layer which is formed in at least one among the light-receiving unit, the oxide film and the channel and forms a plurality of local energy levels by using strained silicon.

Abstract: Provided are a light-receiving element which has more capability of detecting wavelengths than that of existing silicon light-receiving elements and a unit pixel of an image sensor by using it. The light-receiving element includes: a light-receiving unit which is floated or connected to external voltage and absorbs light; an oxide film which is formed to come in contact with a side of the light-receiving unit; a source and a drain which stand off the light-receiving unit with the oxide film in between and face each other; a channel which is formed between the source and the drain and forms an electric current between the source and the drain; and a wavelength expanding layer which is formed in at least one among the light-receiving unit, the oxide film and the channel and forms a plurality of local energy levels by using strained silicon.

Abstract: Techniques, systems, and devices are disclosed for implementing light-emitting hyperbolic metasurfaces. In one exemplary aspect, a light-emitting device includes a surface; a plurality of quantum heterostructures positioned on the surface, each of the plurality of quantum heterostructures including multiple quantum wells distributed along an axis perpendicular to the surface and separated by multiple quantum barriers, wherein each two adjacent quantum heterostructures of the plurality quantum heterostructures form a gap; and a monocrystalline material at least partially filling gaps between the plurality quantum heterostructures.

Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.

Abstract: One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.

Abstract: Quantum device comprising: a quantum component forming a qubit, formed in an active layer of a substrate and comprising: a confinement region; charge carrier reservoirs; a first front gate covering the confinement region; first lateral spacers arranged around the first gate and covering access regions; an FET transistor formed in the active layer, comprising channel, source and drain regions formed in the active layer, a second front gate covering the channel region, and second lateral spacers arranged around the second front gate and covering source and drain extension regions; and wherein a width of the first lateral spacers is greater than that of the second lateral spacers.

Abstract: Structures and techniques, using superconducting Josephson-junction based circuits, to directly engineer physical multiqubit (or “many-qubit”) interactions in a non-perturbative manner. In one embodiment, a system for multiqubit interaction includes: a multispin coupler including a plurality of loops, each loop having a pair of Josephson junctions; and a plurality of qubits each inductively coupled to the multispin coupler.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: Structures and techniques, using superconducting Josephson-junction based circuits, to directly engineer physical multiqubit (or “many-qubit”) interactions in a non-perturbative manner. In one embodiment, a system for multiqubit interaction includes: a multispin coupler including a plurality of loops, each loop having a pair of Josephson junctions; and a plurality of qubits each inductively coupled to the multispin coupler.

Abstract: A qubit may be formed by forming a Josephson junction between two capacitive plates. The Josephson junction may be annealed with a thermal source. The thermal source may be a laser that generates a Gaussian beam. An axicon lens may be exposed to the Gaussian beam. Annealing the Josephson junction may alter the resistance of the Josephson junction.

Abstract: A semiconductor device includes at least one bottom electrode, a resistive layer, and a top electrode. The bottom electrode has two opposite sidewalls. The resistive layer is disposed on the bottom electrode, extends past at least one of the two opposite sidewalls of the at least one bottom electrode, and has a variable resistance. The resistive layer is disposed on the bottom electrode and extends past at least one of the two opposite sidewalls of the at least one bottom electrode.

Abstract: According to one embodiment, a magnetoresistive memory device includes bottom electrodes provided on a substrate, a magnetoresistive element provided on each of the bottom electrodes, a top electrode provided on each of the magnetoresistive elements, an insulating film provided on sides of the bottom electrode, the magnetoresistive element and, the top electrode, and a magnetic layer provided on the top electrode, the magnetic layer extending on the insulating film to connect a plurality of those of the top electrodes.

Abstract: Method for sensing an external magnetic field using a magnetic sensor cell including: a magnetic tunnel junction including a reference layer having a reference magnetization oriented parallel to the plane of the reference layer, a sense layer having a sense magnetization, and a tunnel barrier layer between the sense and reference layers. A field line is configured for passing a field current for providing a sense magnetic field adapted for aligning the sense magnetization. The sense layer magnetization is orientable between a direction parallel to the plane of the sense layer and a direction perpendicular to the plane of the sense layer when the sense magnetic field is provided. The external magnetic field includes an in-plane component oriented parallel to the plane of the sense layer and an out-of-plane component perpendicular to the plane of the sense layer. The method includes sensing the out-of-plane component; and sensing the in-plane component.

Abstract: According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

Abstract: A polymer includes a first moiety represented by Chemical Formula 1, and a second moiety including a substituted or unsubstituted C6 to C60 cyclic group, a substituted or unsubstituted C6 to C60 hetero cyclic group, or a combination thereof: In Chemical Formula 1, X is phosphorus (P), nitrogen (N), boron (B), or P?O, Y1 and Y2 are independently hydrogen or a moiety including at least one substituted or unsubstituted benzene ring, provided that at least one of Y1 and Y2 is the moiety including at least one substituted or unsubstituted benzene ring, Y3 is another moiety including at least one substituted or unsubstituted benzene ring, and * is a linking point.

Abstract: A voltage-controlled magnetic based device is described that includes a magnetic insulator; a topological insulator adjacent the magnetic insulator; and magnetic dopants within the topological insulator. The magnetic dopants are located within an edge region of the topological insulator to inhibit charge current flow in the topological insulator during a switching operation using an applied electric field generating by applying a switching voltage across two electrodes at opposite sides of the topological insulator. Power dissipation due to carrier-based currents can be avoided or at least minimized by the magnetic dopants at the edges of the topological insulator.

Abstract: Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.

Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.

Abstract: According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

Abstract: A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

Abstract: Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.

Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a lower electrode overlying a substrate, an insulating layer overlying the lower electrode, and an upper electrode overlying the insulating layer. The lower electrode, the insulating layer, and the upper electrode form a stack having a side surface. A phase change spacer is adjacent to the side surface, where the phase change spacer is electrically connected to the lower electrode and the upper electrode.

Abstract: A MTJ for a spintronic device includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

Abstract: A method for interaction-free entanglement of quantum bits in quantum computers, in which the quantum bits to be entangled are available in the state ?44 with arbitrarily real phases ? and ? as an elementary quantum system. The two quantum bits (1) and (2) are localized in spatial regions (6) and (6?) and surrounded by switchable sheaths (7) and (7?) preferably a superconductor with the jump temperature TSU. The switchable sheaths, in the activated state, completely displace a global, homogeneous magnetic field Bz from the spatial regions (6) and (6?). In the inactivated state, the switchable sheaths do not shield the spatial regions (6) and (6?). If the switchable sheaths are switched from the activated state into the inactivated state while observing the boundary condition (R3), as a result of this, the two quantum bits (1) and (2) are transferred into the entangled state ??.

Abstract: To provide a transistor having high field effect mobility. To provide a transistor having stable electrical characteristics. To provide a transistor having low off-state current (current in an off state). To provide a semiconductor device including the transistor. The semiconductor device includes a semiconductor; a source electrode and a drain electrode including regions in contact with a top surface and side surfaces of the semiconductor; a gate insulating film including a region in contact with the semiconductor; and a gate electrode including a region facing the semiconductor with the gate insulating film provided therebetween. A length of a region of the semiconductor, which is not in contact with the source and drain electrodes, is shorter than a length of a region of the semiconductor, which is in contact with the source and drain electrodes, in a channel width direction.

Abstract: A MTJ for a domain wall motion device includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A MTJ for a spintronic device includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A MTJ for a spintronic device includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a dipole layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

Abstract: One aspect of the present invention includes a reciprocal quantum logic (RQL) readout system. The system includes an input stage on which a read pulse is provided and an output stage configured to propagate an output pulse. The system also includes an RQL comparator comprising a first Josephson junction and a second Josephson junction that are coupled to a qubit. A bias current switches between a first Josephson junction in a first quantum state of the qubit and a second Josephson junction in a second quantum state of the qubit. The first Josephson junction triggers to provide the output pulse on the output stage in the first quantum state in response to the read pulse and the second Josephson junction triggers to provide no output pulse on the output stage in the second quantum state in response to the read pulse.

Abstract: Techniques for using photo detectors as tunable proximity sensors for detection of target objects and ascertaining their distance from the proximity sensors are disclosed. In one embodiment, the techniques may be realized as a proximity sensor system including a photo detector having a first doped region, a gate, a second doped region and a light absorbing region, a control circuitry for generating a plurality of control signals to be applied to the photo detector, and a signal detector to detect an output signal from the photo detector.

Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.

Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.

Abstract: A photo detector comprising a first doped impurity region (adapted to receive a first voltage) disposed in or on a substrate; a body region, juxtaposed the first doped impurity region; a gate (adapted to receive a second voltage) spaced from a first portion of the body region; a light absorbing region, juxtaposed a second portion of the body region, includes a material which, in response to light incident thereon, generates carrier pairs including a first and second type carriers; a contact region (adapted to receive a third voltage) juxtaposed the light absorbing region; wherein, in response to incident light, the gate attracts first type carriers of the carrier pairs to the first portion of the body region which causes second carriers from the first doped impurity region to flow to the contact region, and the contact region attracts second type carriers.

Abstract: A magnetic element is disclosed wherein first and second interfaces of a free layer with a Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to lower switching current or increase thermal stability in a magnetic tunnel junction (MTJ). In a MTJ with a bottom spin valve configuration where the Hk enhancing layer is an oxide, the capping layer contacting the Hk enhancing layer is selected to have a free energy of oxide formation substantially greater than that of the oxide. The free layer may be a single layer or composite comprised of an Fe rich alloy such as Co20Fe60B20. With a thin free layer, the interfacial perpendicular anisotropy may dominate the shape anisotropy to generate a magnetization perpendicular to the planes of the layers. The magnetic element may be part of a spintronic device or serve as a propagation medium in a domain wall motion device.

Abstract: Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.

Abstract: A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device.

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.