Stacked Capacitor Patents (Class 257/303)
  • Patent number: 9196672
    Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: November 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Khanh Tran, Joseph P. Ellul, Anuranjan Srivastava, Kiyoko Ikeuchi, Scott W. Barry
  • Patent number: 9177947
    Abstract: The invention includes: multiple bit lines b1 to b5 arranged in parallel to each other at a first line pitch; multiple word lines w1 to w4 arranged in parallel to each other at a second line pitch greater than the first line pitch and intersecting with bit lines b1 to b5; and multiple capacitors. Respective center positions 4 of the multiple capacitors lie above the bit lines and are displaced by given distance C from the intersection of the bit line and the word line in a direction of arranging the word lines.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 3, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 9153504
    Abstract: A semiconductor device includes one or more metal-insulator-metal (MiM) capacitors. The semiconductor device includes a bottom electrode, a dielectric layer located above, and in physical contact with, the bottom electrode, a top electrode located above, and in physical contact with, the dielectric layer, a first top contact contacting the top electrode, a first bottom contact contacting the bottom electrode from a top electrode direction, a first metal bump connecting to the top contact, and a second metal bump connecting to the bottom contact. The top electrode has a smaller area than the bottom electrode. The bottom electrode, the dielectric layer, and the top electrode is a MiM capacitor. Top electrodes of a number of MiM capacitors and bottom electrodes of a number of MiM capacitors are daisy chained to allow testing of the conductivity of the electrodes.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Tung-Liang Shao, Ching-Jung Yang
  • Patent number: 9129849
    Abstract: A stacked capacitor structure of the instant disclosure comprises a substrate and a plurality of stacked capacitors. The substrate has an insulating layer formed thereon and a plurality of contact plugs in the insulating layer, wherein the contact plugs are exposed on the upper surface of the insulating layer. Specially, each of the stacked capacitors comprises a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is arranged on one of the contact plugs and has a columnar base portion and a crown shaped upper portion. The dielectric layer is arranged on the lower electrode and covers the outer surface of the lower electrode. The upper electrode is arranged above the lower electrode, wherein the dielectric layer is intermediately between the upper electrode and the lower electrode.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 8, 2015
    Assignee: Inotera Memories, Inc.
    Inventor: Tzung-Han Lee
  • Patent number: 9041154
    Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 26, 2015
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Chien-An Yu, Chih-Huang Wu
  • Patent number: 9041153
    Abstract: According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: May 26, 2015
    Assignee: BROADCOM CORPORATION
    Inventors: Xiangdong Chen, Henry Kuo-Shun Chen, Wei Xia, Bruce Chih-Chieh Shen
  • Patent number: 9012967
    Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
  • Patent number: 9006810
    Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Jeffrey W. Sleight
  • Patent number: 9000562
    Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shean-Ren Horng, Kuo-Nan Hou, Feng-Liang Lai
  • Patent number: 8987086
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Kuo-Chi Tu, Chun-Yao Chen
  • Patent number: 8987800
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
  • Patent number: 8975633
    Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
  • Patent number: 8969938
    Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination of which is accompanied with appropriate etch.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam Shahidi
  • Patent number: 8952436
    Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Cremer, Frédérìc Lalanne, Marc Vernet
  • Patent number: 8946044
    Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Iwaki, Takamasa Itou, Kana Shimizu
  • Patent number: 8940388
    Abstract: Methods of forming an insulative element are described, including forming a first metal oxide material having a first dielectric constant, forming a second metal oxide material having a second dielectric constant different from the first, and heating at least portions of the structure to crystallize at least a portion of at least one of the first dielectric material and the second dielectric material. Methods of forming a capacitor are described, including forming a first electrode, forming a dielectric material with a first oxide and a second oxide over the first electrode, and forming a second electrode over the dielectric material. Structures including dielectric materials are also described.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vassil Antonov, Jennifer K. Sigman, Vishwanath Bhat, Matthew N. Rocklein, Bhaskar Srinivasan, Chris Carlson
  • Patent number: 8941165
    Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Cho, Seung-Young Son, Chang-Jin Kang, Kyeong-Koo Chi, Ji-Chul Shin
  • Patent number: 8937344
    Abstract: The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jung Ryul Ahn, Jum Soo Kim
  • Patent number: 8921911
    Abstract: A vertical semiconductor charge storage structure includes a substrate, at least one lower electrode, a dielectric layer and an upper electrode. The lower electrode includes a lower conductor, and a first side conductor and a second side conductor connected to the lower conductor. The first side conductor and the second side conductor are parallel to each other and form an included angle with the lower conductor. A height of the first side conductor from the substrate is greater than a height of the second side conductor from the substrate. The dielectric layer and the upper electrode are sequentially formed on surfaces of the substrate and the lower electrode. Accordingly, by forming the first side conductor and the second side conductor at different heights, an aperture ratio is increased to reduce difficulty in filling or deposition in subsequent processes to further enhance an overall yield rate.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Rexchip Electronics Corporation
    Inventors: Pin-Yuan Yu, Yi-Chun Shao, Chien-Hua Chu
  • Patent number: 8916436
    Abstract: A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Dundulachi, Antonio Molfese
  • Patent number: 8912629
    Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: JungWoo Seo
  • Patent number: 8901708
    Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Imran Hashim, Hanhong Chen, Tony Chiang, Indranil De, Nobumichi Fuchigami, Edward Haywood, Pragati Kumar, Sandra Malhotra, Sunil Shanker
  • Patent number: 8901629
    Abstract: A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jung Ryul Ahn, Yun Kyoung Lee
  • Patent number: 8890224
    Abstract: A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A metal-insulator-metal (MIM) capacitor structure is disposed over the substrate. A dual damascene structure disposed over and electrically coupled with the TSV structure, wherein the dual damascene structure includes a via portion and a trench portion A first dielectric layer is disposed around the via portion of the dual damascene structure. A second dielectric layer disposed around the trench portion of the dual damascene, wherein the second dielectric layer is disposed over the MIM capacitor structure.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Sung-Hui Huang, Der-Chyang Yeh
  • Patent number: 8884288
    Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Qiang Li, Zhuanlan Sun, Changhui Yang
  • Patent number: 8884350
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota
  • Patent number: 8878338
    Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 8835250
    Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
  • Patent number: 8829647
    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Edward Haywood, Sandra Malhotra, Hiroyuki Ode
  • Patent number: 8816418
    Abstract: A semiconductor memory device includes at least one supporting pattern on a substrate, a storage node penetrating the supporting pattern, an electrode layer disposed around the storage node and the supporting pattern, and a capacitor dielectric interposed between the storage node and the electrode layer. The supporting pattern includes germanium oxide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyongsoo Kim, Eunkee Hong, Kwangtae Hwang
  • Patent number: 8816419
    Abstract: Provided is a semiconductor device having a high switching speed. A semiconductor device is provided with an n-type epitaxial layer having a plurality of trenches arranged at prescribed intervals; an embedded electrode formed on an inner surface of the trench through a silicon oxide film to embed each trench; and a metal layer, which is capacitively coupled with the embedded electrode by being arranged above the embedded electrode through a silicon oxide film. In the semiconductor device, a region between the adjacent trenches operates as a channel (current path). A current flowing in the channel is interrupted by covering the region with a depletion layer formed at the periphery of the trenches, and the current is permitted to flow through the channel by eliminating the depletion layer at the periphery of the trenches.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: August 26, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8802532
    Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: August 12, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Nam Joo Kim
  • Patent number: 8796795
    Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 5, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Kimihiro Satoh, Yiming Huai, Jing Zhang, Ebrahim Abedifard
  • Patent number: 8779490
    Abstract: A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Babar A. Khan, Effendi Leobandung
  • Patent number: 8772862
    Abstract: A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 8, 2014
    Assignee: SK Hynix Inc.
    Inventor: Heung-Jae Cho
  • Patent number: 8766345
    Abstract: An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Shu-Jen Han, George S. Tulevski
  • Patent number: 8766399
    Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Maeda, Yasushi Sekine, Tetsuya Watanabe
  • Patent number: 8759893
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor disposed on the substrate, the capacitor having an anode component that includes a plurality of first conductive features and a cathode component that includes a plurality of second conductive features. The first conductive features and the second conductive features each include two metal lines extending along the first axis. At least one metal via extending along a third axis that is perpendicular to the surface of the substrate and interconnecting the two metal lines. The first conductive features are interdigitated with the second conductive features along both the second axis and the third axis.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiu-Ying Cho
  • Patent number: 8754501
    Abstract: An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Imran Mahmood Khan, John Paul Campbell, Neal Thomas Murphy
  • Patent number: 8742540
    Abstract: A metal-insulator-metal (MIM) capacitor and a method for forming the same are provided. The MIM capacitor includes an insulator on a bottom metal plate, a top metal plate on the insulator, a dielectric layer on the top metal plate and on at least sidewalls of the top metal plate and the insulator, and an anti-reflective coating (ARC) layer over the top metal plate and the bottom metal plate. The dielectric layer preferably extends on an exposed portion of the bottom metal plate not covered by the top metal plate and the insulator.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yao Hsiang Liang
  • Patent number: 8723249
    Abstract: A non-volatile memory includes a substrate, a gate dielectric layer, a gate conductive layer, a nitride layer, a spacer, a first oxide layer, and a second oxide layer. The gate conductive layer, substrate and gate dielectric layer cooperatively constitute a symmetrical opening thereamong. The nitride layer has an L-shape and formed with a vertical part extending along a sidewall of the gate conductive layer and a horizontal part extending into the opening, wherein the vertical part and the horizontal part are formed as an integral structure and a height of the vertical part is below a top surface of the gate conductive layer. The spacer is disposed on the substrate and the nitride layer. The first oxide layer is disposed among the gate conductive layer, the nitride layer and the gate dielectric layer. The second oxide layer is disposed among the gate dielectric layer, the nitride layer and the substrate.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: May 13, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Hung Chen, Tzu-Ping Chen, Yu-Jen Chang
  • Patent number: 8716778
    Abstract: Metal-insulator-metal capacitors are provided that are formed in integrated circuit dielectric stacks. A line-plate-line capacitor is provided that alternates layers that contain metal plates with layers that contain straight or angled parallel lines of alternating polarity. A segmented-plate capacitor is provided that has metal plates that alternate in polarity both within a layer and between layers. The line-plate-line and segmented-plate capacitors may exhibit a reduced parasitic inductive coupling. The capacitances of the line-plate-line capacitor and the metal-insulator-metal capacitor may have an enhanced contribution from an interlayer capacitance component with a vertical electric field than a horizontal intralayer capacitance component with a horizontal electric field.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: May 6, 2014
    Assignee: Altera Corporation
    Inventors: Shuxian Chen, Jeffrey T. Watt, Mojy Curtis Chian
  • Patent number: 8710564
    Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
  • Patent number: 8704283
    Abstract: A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Kyu Kim, Sang-Sup Jeong, Sung-Gil Choi, Heung-Sik Park, Kuk-Han Yoon, Yong-Joon Choi
  • Patent number: 8698147
    Abstract: Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a thin-film transistor (TFT), which includes an active layer, a gate electrode, and source/drain electrodes; an organic electroluminescent device electrically connected to the TFT and includes a pixel electrode formed on the same layer as the gate electrode, an intermediate layer including an organic light emitting layer, and a counter electrode that are stacked in the order stated; and a capacitor, which includes a bottom electrode, which is formed on the same layer and of the same material as the active layer and is doped with an impurity; a top electrode formed on the same layer as the gate electrode; and a metal diffusion medium layer formed on the same layer as the source/drain electrodes and is connected to the bottom electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Choi, Na-Young Kim, Dae-Woo Lee
  • Patent number: 8698219
    Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state (off-state current) between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or to the memory cell by applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another so that the predetermined amount of charge is held in the node. The memory window width is changed by 2% or less, before and after 1×109 times of writing.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yusuke Sekine, Yutaka Shionoiri, Kiyoshi Kato, Shunpei Yamazaki
  • Patent number: 8693163
    Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Jhih Su, Chi-Chun Hsieh, Tzu-Yu Wang, Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 8680602
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jae-Bok Baek
  • Patent number: 8680599
    Abstract: To provide a more reliable semiconductor device including a lower-cost and more reliable capacitor and a method of manufacturing the same. This manufacturing method comprises the steps of: preparing a semiconductor substrate; and forming, over one of the major surfaces of the semiconductor substrate, a first metal electrode including an aluminum layer, a dielectric layer over the first metal electrode, and a second metal electrode over the dielectric layer. In the step of forming the first metal electrode, the aluminum layer is formed so that the surface thereof satisfies a relationship of Rmax<80 nm, Rms<10 nm, and Ra<9 nm. The step of forming the first metal electrode comprises the steps of: forming at least one first barrier layer; forming the aluminum layer over the first barrier layer; and recrystallizing a crystal constituting the aluminum layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Mitsuyama, Yasuhisa Fujii, Keiichi Yamada
  • Patent number: 8680649
    Abstract: A multi-layer capacitor of staggered construction is formed of one or more layers having tapered sidewall(s). The edge(s) of the capacitor film(s) can be etched to have a gentle slope, which can improve adhesion of the overlying layers and provide more uniform film thickness. The multi-layer capacitor can be used in various applications such as filtering and decoupling.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Guillaume Guégan