Stacked Capacitor Patents (Class 257/306)
  • Patent number: 9704854
    Abstract: A DC-to-DC converter includes: a substrate having a switching element region defined by an isolation layer; a transistor formed over the switching element region; a landing plate formed over the isolation layer; a capacitor formed over the landing plate and includes a bottom plate, a dielectric layer and a top plate; multi-layer metal lines disposed in an upper portion of the transistor and coupled with the transistor; and an interconnection portion coupled with the multi-layer metal lines to electrically connect the transistor with the capacitor.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: July 11, 2017
    Assignee: SK Hynix Inc.
    Inventors: Heon-Joon Kim, Jae-Ho Hwang
  • Patent number: 9691981
    Abstract: The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: June 27, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, D.V. Nirmal Ramaswamy
  • Patent number: 9691818
    Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. The source region and the drain region of the active line are formed of a first material and the channel region of the active line is formed of a second material being different from the first material.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 27, 2017
    Assignee: SK Hynix Inc.
    Inventor: Suk Ki Kim
  • Patent number: 9685433
    Abstract: In some embodiments, a capacitor device includes a metal-oxide-metal (MOM) capacitor array and a varactor array configured overlapping with the MOM capacitor array. The MOM capacitor array includes a first MOM capacitor unit. The first MOM capacitor unit includes a first electrode pattern and a second electrode pattern in a first metallization layer. The first electrode pattern includes a plurality of first fingers and a first bus interconnecting the plurality of first fingers. The second electrode pattern includes a plurality of second fingers and a second bus interconnecting the plurality of second fingers. The varactor array includes a first varactor unit. The first varactor unit includes a first electrode contacting region and a second electrode contacting region. The first electrode pattern contacts the first electrode contacting region. The second electrode pattern contacts the second electrode contacting region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chao-Chieh Li
  • Patent number: 9679917
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 13, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ricardo A. Donaton, Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage
  • Patent number: 9679964
    Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: June 13, 2017
    Assignee: Micron Technologies, Inc.
    Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew J. King
  • Patent number: 9673102
    Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: June 6, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jun Liu, Sanh D. Tang, David H. Wells
  • Patent number: 9660040
    Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
  • Patent number: 9647057
    Abstract: A capacitor 3D-cell formed on a silicon substrate is designed for producing low equivalent serial resistance and high capacitor surface-density. It combines a trench capacitor structure, multiple contact pads to at least one of the electrodes and a track which connects the electrode through the multiple contact pads so as to bypass said electrode between trench portions which are located apart from each other.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: May 9, 2017
    Assignee: IPDIA
    Inventor: Frédéric Voiron
  • Patent number: 9646919
    Abstract: A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: May 9, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen St. Germain, Roger Arbuthnot, Peter Moens
  • Patent number: 9640587
    Abstract: A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. A gate electrode having a lower height than each active line is formed on a sidewall of the active line. A first insulating layer having a height lower than that of the active line and higher than that of the gate electrode is buried between active lines, and a silicide layer is formed on an exposed upper surface and a lateral surface of the active line.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 2, 2017
    Assignee: SK Hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 9634096
    Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen
  • Patent number: 9627215
    Abstract: A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hua Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Cherng-Shiaw Tsai
  • Patent number: 9613965
    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Ting, Kuo-Ching Huang
  • Patent number: 9607680
    Abstract: One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. The capacitors may be physically placed near the logic components for which the capacitors are providing decoupling capacitance, in an embodiment. The capacitors may be series connections of at least two capacitors, or at least one capacitor and a switch, to provide decoupling capacitance in the face of defects, in an embodiment. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 28, 2017
    Assignee: Apple Inc.
    Inventor: Sanjay Dabral
  • Patent number: 9607991
    Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: March 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takeshi Aoki
  • Patent number: 9601545
    Abstract: The present disclosure relates to a method of forming an integrated circuit that prevents damage to MIM decoupling capacitors, and an associated structure. In some embodiments, the method comprises forming one or more lower metal interconnect structures within a lower ILD layer over a substrate. A plurality of MIM structures are formed over the lower metal interconnect structures, and one or more upper metal interconnect structures are formed within an upper ILD layer over the plurality of MIM structures. Together the lower and upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential. By placing the MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Chin-Chieh Yang, Wen-Ting Chu
  • Patent number: 9594041
    Abstract: Provided is a capacitive humidity sensor. The capacitive humidity sensor includes an upper electrode disposed on a first plane, a plurality of first electrodes included in the upper electrode, a plurality of second electrodes disposed between the first electrodes, and a humidity sensitive layer surrounding the second electrodes.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: March 14, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Sang Geun Koo, Kwan Soo Kim
  • Patent number: 9590232
    Abstract: A three dimensional electrode structure having a first layer of interdigitated stripes of material oriented in a first direction, and a second layer of interdigitated stripes of material oriented in a second direction residing on the first layer of interdigitated stripes of material. A method of manufacturing a three dimensional electrode structure includes depositing a first layer of interdigitated stripes of an active material and an intermediate material on a substrate in a first direction, and depositing a second layer of interdigitated stripes of the active material and the intermediate material on the first layer in a second direction orthogonal to the first direction.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 7, 2017
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Corie Lynn Cobb, Chang-Jun Bae
  • Patent number: 9589962
    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: March 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
  • Patent number: 9553193
    Abstract: A semiconductor device is provided that includes a fin having a first upper gate on a sidewall of the fin in a first trench and a second upper gate formed on the opposite sidewall of the fin. The device also includes a first lower gate on the sidewall and a second lower gate on the opposite sidewall, wherein the first upper gate is formed above the first lower gate and the second upper gate is formed above the second lower gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first upper gate and second upper gate to preselect the transistors of a fin and then biasing the first lower gate and second lower gate to operate the transistors of the fin.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 9541463
    Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 10, 2017
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiyang He, Chenglong Zhang
  • Patent number: 9536888
    Abstract: The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Ming Wu, Harry-Hak-Lay Chuang, Shih-Chang Liu
  • Patent number: 9508788
    Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 29, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Roehner, Stefano Aresu
  • Patent number: 9496381
    Abstract: A semiconductor device may include a substrate including an active pattern delimited by a device isolation pattern, a gate electrode crossing the active pattern, a first impurity region and a second impurity region in the active pattern on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region with the bit line, and a first nitride pattern on a lower side surface of the first contact. A width of the first contact measured perpendicular to an extending direction of the bit line may be substantially equal to that of the bit line.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 15, 2016
    Assignee: SAMSUNG ELECTTONICS CO., LTD.
    Inventors: Mongsup Lee, Yoonho Son, Woogwan Shim, Chan Min Lee, Inseak Hwang
  • Patent number: 9484335
    Abstract: A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 1, 2016
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park, Tae-Yoon Kim, Ju-Hyun Myung, Kyu-Hyung Yoon
  • Patent number: 9472563
    Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: October 18, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Masatomi Okanishi
  • Patent number: 9449977
    Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: JungWoo Seo
  • Patent number: 9443799
    Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Benjamin V. Fasano, Shidong Li
  • Patent number: 9437300
    Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Kamata, Toshifumi Minami, Teppei Higashitsuji, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara
  • Patent number: 9434614
    Abstract: The present invention relates to a perovskite-type strontium titanate, wherein the strontium titanate is Y- and Ni-doped and has the general formula (Sr,Y)(Ti,Ni)O3. A method of preparing the perovskite-type strontium titanate and its use are also provided.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 6, 2016
    Assignee: Agency for Science, Technology and Research
    Inventors: Wei Wang, Liang Hong, Zetao Xia, Zhaolin Liu, Teng Sheng Peh
  • Patent number: 9431604
    Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Liao, Wen-Ting Chu, Kuo-Chi Tu, Chin-Chieh Yang, Chih-Yang Chang, Hsia-Wei Chen
  • Patent number: 9425308
    Abstract: A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a substrate and an active layer on the substrate. A gate electrode is disposed on the active layer. A first electrode and a second electrode are disposed on the active layer, on opposite sides of the gate electrode. A first metal pattern is coupled to the first electrode. A second metal pattern is coupled to the second electrode. A first insulating layer is disposed on the first and second metal patterns. A third metal pattern covers the first insulating layer, coupled to the second metal pattern. An interface between the third metal pattern and the first insulating layer is a substantially planar surface.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: August 23, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Wen-Chia Liao
  • Patent number: 9425282
    Abstract: A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. A gate electrode having a lower height than each active line is formed on a sidewall of the active line. A first insulating layer having a height lower than that of the active line and higher than that of the gate electrode is buried between active lines, and a silicide layer is formed on an exposed upper surface and a lateral surface of the active line.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: August 23, 2016
    Assignee: SK Hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 9419098
    Abstract: A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Gwan Sin Chang, Zhiqiang Wu, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 9412940
    Abstract: A bipolar resistive switching device (RSM device, FIG. 35) comprises an electrically conductive bottom electrode (BE, FIG. 35); a stack of transition metal oxides layers (RSM, FIG. 35), a number of transition metal oxide layers (RSO, FIG. 35) being equal or greater than 2, the stack comprising: at least one MOx layer (RSOA, FIG. 35), at least one oxygen gettering layer NOy (RSOB, FIG. 35). The resistive switching device further comprises an electrically conductive top electrode (TE, FIG. 35).
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: August 9, 2016
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Davide Sacchetto, Shashi Kanth Bobba, Pierre-Emmanuel Julien Marc Gaillardon, Yusuf Leblebici, Giovanni De Micheli, Tugba Demirci
  • Patent number: 9406444
    Abstract: A system that incorporates teachings of the present disclosure may include, for example, a first solid electrode, a second electrode separated into subsections, and a dielectric medium separating the subsections from the first solid electrode, where the subsections of the second electrode include a first group of subsections and a second group of subsections, where the first group of subsections are connectable with a first terminal for receiving an input signal, and where the second group of subsections is connectable with a second terminal for providing an output signal. Other embodiments are disclosed.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: August 2, 2016
    Assignee: BLACKBERRY LIMITED
    Inventors: James Oakes, James Martin, Edward Provo Wallis Horne, William E. McKinzie
  • Patent number: 9391015
    Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: July 12, 2016
    Assignees: STMICROELECTRONICS S.A., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Simon Jeannot, Pascal Tannhof
  • Patent number: 9391016
    Abstract: The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Guo Shen, Wei-Min Tseng, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
  • Patent number: 9391176
    Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Ralf Richter, Peter Javorka
  • Patent number: 9386250
    Abstract: A solid state image pickup device is provided that includes a pixel array unit having a plurality of pixels and a signal processing circuit that has a capacitor operatively configured to process a respective signal output from each of the plurality of pixels. The capacitor is operatively configured as a stacked capacitor or a trench capacitor.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: July 5, 2016
    Assignee: SONY CORPORATION
    Inventors: Toshifumi Wakano, Keiji Mabuchi
  • Patent number: 9370103
    Abstract: An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: June 14, 2016
    Assignee: QUALCOMM Incorported
    Inventors: Changhan Hobie Yun, Chengjie Zuo, Jonghae Kim, Daeik Daniel Kim, Mario Francisco Velez
  • Patent number: 9368392
    Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Min Tseng, Shih-Guo Shen, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
  • Patent number: 9356118
    Abstract: A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting semiconductor substrate is described. The lateral semiconductor layers have different band gaps such that a two-dimensional electron gas can form in their semiconductor depletion layer. Upon application of a voltage between source electrode contact areas and drain electrode contact areas or source and drain, an electric current can flow through the lateral semiconductor depletion layer. Current intensity in a channel region between the source electrode contact areas and the drain electrode contact areas is controllable via gate electrode contact areas by means of a gate voltage.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Prechtl
  • Patent number: 9343662
    Abstract: A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Juan Boon Tan, Wanbing Yi, Danny Pak-Chum Shum, Yi Jiang
  • Patent number: 9331132
    Abstract: A multiple layer pixel architecture for an active matrix display is provided in which a common bus line is formed on a metal level which is separate from that on which the gate electrodes of the thin-film transistors (TFTS) are formed. A multilayer electronic structure adapted to solution deposition, the structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separeted by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, and wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: May 3, 2016
    Assignee: FLEXENABLE LIMITED
    Inventors: Kieran Reynolds, Catherine Ramsdale, Kevin Jacobs, William Reeves
  • Patent number: 9312221
    Abstract: A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate. A resistance of the variable resistor is based on a voltage applied to the gate structure, which adjusts a resistance of the channel and a capacitance of the variable capacitance device.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Patent number: 9305920
    Abstract: A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device further includes a dielectric layer over each high voltage well of the at least one high voltage well and a gate structure over the dielectric layer. The HV-MOM device further includes an inter-layer dielectric (ILD) layer over the substrate, the ILD layer surrounding the gate structure. The HV-MOM device further includes a first inter-metal dielectric (IMD) layer over the ILD layer and a first metal feature in the first IMD layer, wherein the first metal feature is part of a MOM capacitor.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: April 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung Chen, Shu Fang Fu, Chang-Sheng Liao
  • Patent number: 9305925
    Abstract: In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR1. The eDRAM further includes: a capacitive plug electrode coupled to the drain plug electrode; a bit line coupled to the source plug electrode; a stopper film covering the bit line; and a capacitive element that is formed over the stopper film and has a first electrode, a dielectric film, and a second electrode. The first electrode is coupled to the capacitive plug electrode, and the height of the capacitive plug electrode and that of the bit line are equal to each other.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Seigo Namioka
  • Patent number: 9305918
    Abstract: The present disclosure provides methods to fabricate a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang