Abstract: A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device.

Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.

Abstract: A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.

Abstract: An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.

Abstract: A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

Abstract: A magnetic memory device may include a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer arranged on a substrate. The tunnel barrier layer may include a crystal structure and may be arranged between the first ferromagnetic layer and the second ferromagnetic layer. At least the first ferromagnetic layer may include a first layer in contact with the tunnel barrier layer and a second layer in contact with the first layer, and an orientation of the first layer with respect to the tunnel barrier layer may be greater than an orientation of the second layer with respect to the tunnel barrier layer.

Abstract: A system that incorporates teachings of the present disclosure may include, for example, a solid-state selector having a vessel for carrying a liquid medium with one or more molecules surrounded by ions, a solid state conductive structure doped with impurities having one or more through-holes extending between two surfaces of the solid state conductive structure positioned within the liquid medium of the vessel, a voltage source coupled to the solid state conductive structure to selectively stimulate the ions surrounding the one or more molecules to pass through the one or more through-holes. Additional embodiments are disclosed.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.

Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.

Abstract: The present invention provides an organic light emitting device comprising a first electrode, a second electrode, and at least two organic material layers interposed therebetween, including a light emitting layer, wherein the organic material layers comprise at least one layer of a hole injecting layer, a hole transporting layer and a hole injecting and transporting layer, and at least one of the hole injecting layer, the hole transporting layer and the hole injecting and transporting layer comprises a material with a HOMO energy level of ?4 eV or less, and a material with a LUMO energy level of ?4 eV or less, and a process for preparing the same.

Abstract: The use of liquid metal contacts for devices based on thermotunneling has been investigated. Electric and thermal characteristics of low wetting contact Hg/Si, and high wetting contacts Hg/Cu were determined and compared. Tunneling I-V characteristics for Hg/Si were obtained, while for Hg/Cu, I-V characteristics were ohmic. The tunneling I-V characteristic is explained by the presence of a nanogap between the contact materials. Heat conductance of high wetting and low wetting contacts were compared, using calorimeter measurements. Heat conductance of high wetting contact was 3-4 times more than of low wetting contact. Both electric and thermal characteristics of liquid metal contact indicated that it could be used for thermotunneling devices. To reduce the work function and make liquid metal more suitable for room temperature cooling, Cs was dissolved in liquid Hg. Work function as low as 2.6 eV was obtained.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: A boron or boron containing dusting layer such as CoB or FeB is formed along one or both of top and bottom surfaces of a free layer at interfaces with a tunnel barrier layer and capping layer to improve thermal stability while maintaining other magnetic properties of a MTJ stack. Each dusting layer has a thickness from 0.2 to 20 Angstroms and may be used as deposited, or at temperatures up to 400° C. or higher, or following a subsequent anneal at 400° C. or higher. The free layer may be a single layer of CoFe, Co, CoFeB or CoFeNiB, or may include a non-magnetic insertion layer. The resulting MTJ is suitable for STT-MRAM memory elements or spintronic devices. Perpendicular magnetic anisotropy is maintained in the free layer at temperatures up to 400° C. or higher. Ku enhancement is achieved and the retention time of a memory cell for STT-MRAM designs is increased.

Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.

Abstract: A magnetoresistive element according to an embodiment includes: a first magnetic layer; a tunnel barrier layer on the first magnetic layer; a second magnetic layer placed on the tunnel barrier layer and containing CoFe; and a nonmagnetic layer placed on the second magnetic layer, and containing nitrogen and at least one element selected from the group consisting of B, Ta, Zr, Al, and Ce.

Abstract: Aspects of the invention provide a semiconductor tunneling device including voltage controlled negative resistance. In one embodiment, the semiconductor tunneling device includes: at least one pair of spaced apart terminals; an inter-level dielectric (ILD) layer between the at least one pair of spaced apart terminals; and a dielectric capping layer extending continuously over the at least one pair of spaced apart terminals and the ILD layer.

Abstract: A quantum computational (QC) device includes a multi-qubit (MQ) structure and another MQ structure coupled to the MQ structure. The MQ structure is arranged to provide an adiabatic quantum computation by application of an initial Hamiltonian operator. The other MQ structure is arranged to provide another adiabatic quantum computation by application of another Hamiltonian operator that is spatially different than the initial Hamiltonian operator.

Abstract: This invention concerns an electronic device for the control and readout of the electron or hole spin of a single dopant in silicon. The device comprises a silicon substrate in which there are one or more ohmic contact regions. An insulating region on top of the substrate. First and second barrier gates spaced apart to isolate a small region of charges to form an island of a Single Electron Transistor (SET). A third gate over-lying both the first and second barrier gates, but insulated from them, the third gate being able to generate a gate-induced charge layer (GICL) in the beneath it. A fourth gate in close proximity to a single dopant atom, the dopant atom being encapsulated in the substrate outside the region of the GICL but close enough to allow spin-dependent charge tunnelling between the dopant atom and the SET island under the control of gate potentials, mainly the fourth gate.

Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed to one side of the MTJ. The induction line is configured to induce a perpendicular magnetic field at the MTJ.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TPET, the drain region comprises p-doped silicon, while the source region comprises n-doped SiC.

Abstract: An example memory cell may have at least a tunneling region disposed between a conducting region and a metal region, wherein the tunneling region can have at least an active interface regio disposed between a first tunneling barrier and a second tunneling barrier. A high resistive film is formed in the interface region with migration of ions from both the metal and conducting regions responsive to a write current to program the memory cell to a selected resistive state.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector can include: a substrate in which a V-shaped groove having a predetermined angle is formed; a light-absorbing part formed in a floated structure above the V-shaped groove and to which light is incident; an oxide film formed between the light-absorbing part and the V-shaped groove and in which tunneling occurs; a source formed adjacent to the oxide film on a slope of one side of the V-shaped groove and separated from the light-absorbing part by the oxide film; a drain formed adjacent to the oxide film on a slope of the other side of the V-shaped groove and separated from the light-absorbing part by the oxide film; and a channel interposed between the source and the drain along the V-shaped groove to form flow of an electric current between the source and the drain.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.

Abstract: A semiconductor power switch and method is disclosed. In one Embodiment, the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the semiconductor structure between the source contact and the drain contact. The semiconductor structure has a plurality of nanowires which are connected in parallel and are arranged in such a manner that each nanowire forms an electrical connection between the source contact and the drain contact.

Abstract: One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material.

Abstract: A method for determining whether a quantum system comprising a superconducting qubit is occupying a first basis state or a second basis state once a measurement is performed is provided. The method, comprising: applying a signal having a frequency through a transmission line coupled to the superconducting qubit characterized by two distinct, separate, and stable states of differing resonance frequencies each corresponding to the occupation of the first or second basis state prior to measurement; and measuring at least one of an output power or phase at an output port of the transmission line, wherein the measured output power or phase is indicative of whether the superconducting qubit is occupying the first basis state or the second basis state.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: The present invention is directed to a semiconductor device that includes at least one p-n junction including a p-type material, an n-type material, and a depletion region. The at least one p-n junction is configured to generate bulk photocurrent in response to incident light. The at least one p-n junction is characterized by a conduction band energy level, a valence band energy level and a surface Fermi energy level. The surface Fermi energy level is pinned either near or above the conduction band energy level or near or below the valence band energy level. A unipolar barrier structure is disposed in a predetermined region within the at least one p-n junction.

Abstract: Embodiments provide a semiconductor light emitting device which comprises a light emitting structure comprising a plurality of compound semiconductor layers, an insulation layer on an outer surface of the light emitting structure, an ohmic layer under the light emitting structure and on an outer surface of the insulation layer, a first electrode layer on the light emitting structure, and a tunnel barrier layer between the first electrode layer and the ohmic layer.

Abstract: A method comprises applying a first electric field pulse to a nanowire comprising a channel and a charge trapping region configured to control conductivity of the channel, the first electric field pulse having a first polarity and a relatively large magnitude of integral of electric field during the pulse and, thereafter, applying at least one further electric field pulse to the nanowire, each further electric pulse having a second, opposite polarity and each respective further electric field pulse having a relatively small magnitude of integral of electric field during the pulse.

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Abstract: Two-terminal switching devices of MIM type having at least one electrode formed by a liquid phase processing method are provided for use in active matrix backplane applications; more specifically, MIM devices with symmetric current-voltage characteristics are applied for LCD active matrix backplane applications, and MIM devices with asymmetric current-voltage characteristics are applied for active matrix backplane implementation for electrophoretic displays (EPD) and rotating element displays. In particular, the combination of the bottom metal, metal-oxide insulator and solution-processible top conducting layer enables high throughput, roll-to-roll process for flexible displays.

Abstract: A system that incorporates teachings of the present disclosure may include, for example, a solid-state selector having a vessel for carrying a liquid medium with one or more molecules surrounded by ions, a solid state conductive structure doped with impurities having one or more through-holes extending between two surfaces of the solid state conductive structure positioned within the liquid medium of the vessel, a voltage source coupled to the solid state conductive structure to selectively stimulate the ions surrounding the one or more molecules to pass through the one or more through-holes. Additional embodiments are disclosed.

Abstract: An electron transport device, including at least one transport layer in which at least one periodic dislocation and/or defect array is produced, and a mechanism for guiding electrons in the transport layer.

Abstract: A diode having a reference voltage electrode, a variable voltage electrode, and a diode material between the electrodes. The diode material is formed of at least one high-K dielectric material and has an asymmetric energy barrier between the reference voltage electrode and the variable voltage electrode, with the energy barrier having a relatively maximum energy barrier level proximate the reference voltage electrode and a minimum energy barrier level proximate the variable voltage electrode.

Abstract: One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material.

Abstract: A microelectronic device is provided with at least one transistor or triode with Fowler-Nordheim tunneling current modulation, and supported on a substrate. The triode or the transistor includes at least one first block forming a cathode and at least one second block forming an anode. The first block and the second block are supported on the substrate, and are separated from each other by a channel insulating zone also supported on the substrate. A gate dielectric zone is supported on at least the channel insulating zone, and a gate is supported on the gate dielectric zone.

Abstract: Systems, articles, and methods are provided related to nanowire-based detectors, which can be used for light detection in, for example, single-photon detectors. In one aspect, a variety of detectors are provided, for example one including an electrically superconductive nanowire or nanowires constructed and arranged to interact with photons to produce a detectable signal. In another aspect, fabrication methods are provided, including techniques to precisely reproduce patterns in subsequently formed layers of material using a relatively small number of fabrication steps. By precisely reproducing patterns in multiple material layers, one can form electrically insulating materials and electrically conductive materials in shapes such that incoming photons are redirected toward a nearby electrically superconductive materials (e.g., electrically superconductive nanowire(s)). For example, one or more resonance structures (e.g.

Abstract: The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.

Abstract: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the ?=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two ?-quasiparticles. which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the ?=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a ?/8 gate may be effected.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

Abstract: A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode.

Abstract: A semiconductor device for sensing infrared radiation is provided. In an embodiment, the semiconductor device includes a sensor configuration which includes a light receiving portion for converting incident photons into heat and a sensing portion integrated with the light receiving portion and having a resistance varying according to the converted heat; and a sensing circuit which includes a common mode current providing portion and a current subtraction portion, wherein the common mode current providing portion outputs a common mode current related to a value of a current which is flowing in the sensing portion when there is no incident light and the current subtraction portion outputs subtraction currents for the common mode current and a sensing current related to a current output from the sensing portion.

Abstract: A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.

Abstract: Apparatus and methods for detecting evaporation conditions in an evaporator for evaporating metal onto semiconductor wafers, such as GaAs wafers, are disclosed. One such apparatus can include a crystal monitor sensor configured to detect metal vapor associated with a metal source prior to metal deposition onto a semiconductor wafer. This apparatus can also include a shutter configured to remain in a closed position when the crystal monitor sensor detects an undesired condition, so as to prevent metal deposition onto the semiconductor wafer. In some implementations, the undesired condition can be indicative of a composition of a metal source, a deposition rate of a metal source, impurities of a metal source, position of a metal source, position of an electron beam, and/or intensity of an electron beam.

Abstract: The invention relates to an interconnection network and an integrated circuit and a method for manufacturing the same. Furthermore, the invention relates to a method for signal transfer between semiconductor structures. The invention is characterized in that a signal of a first semiconductor structure is supplied to a transmitter, which generates from the signal a plasmon wave, and couples the latter into a waveguide. The plasmons fed through the waveguide are received by a receiver, converted to an electric signal and forwarded to a second semiconductor structure.