Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, and a source structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure extend in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. At least two of the plurality of source contacts are in contact with and conductively connected to one another.

Abstract: A semiconductor device includes a first stepped structure including a first portion and a second portion, a second stepped structure including a third portion on the second portion of the first stepped structure, a first supporting structure penetrating the first portion of the first stepped structure, and a second supporting structure penetrating the second portion of the first stepped structure and the third portion of the second stepped structure. The first supporting structure includes a sidewall having a substantially constant slope, and the second supporting structure includes a sidewall having an inflection point.

Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.

Abstract: According to one embodiment, a semiconductor memory device includes: first interconnect layers; a second interconnect layer separate from the first interconnect layers; a third interconnect layer separate from the first interconnect layers and adjacent to the second interconnect layer in a second direction; a first memory pillar which passes through the second interconnect layer; a second memory pillar which passes through the third interconnect layer. The second interconnect layer includes a first portion connected to a first contact plug. The third interconnect layer includes a second portion connected to a second contact plug. The first and second portions are arranged along a third direction which intersects the second direction.

Abstract: The present disclosure provides a method for fabricating split-gate non-volatile memory. The method comprises the following: 1) preparing a semiconductor substrate by forming at least one shallow trench isolation structure in the semiconductor substrate to isolate at least one active region in the semiconductor substrate; 2) forming at least one word line on the semiconductor substrate; 3) forming at least one source and at least one drain in the semiconductor substrate, and forming at least one floating gate on a sidewall of the word line on a side close to the source; 4) removing part of the word line by adopting an etching process; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming at least one metal bit line on the conductive plug.

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies.

Abstract: Embodiments of a method for forming three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is further formed by filling the channel hole with a channel-forming structure. The semiconductor channel may have a memory layer having a first memory portion surrounding a bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers above the substrate. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally along a serpentine path to separate the memory stack into a first area and a second area. The 3D memory device further includes first channel structures each extending vertically through the first area of the memory stack and including a drain at its upper end, and second channel structures each extending vertically through the second area of the memory stack and including a source at its upper end. The 3D memory device further includes semiconductor connections disposed vertically between the substrate and the memory stack.

Abstract: A semiconductor memory according to an embodiment includes a first conductor, a first insulator and memory pillars. The first conductor and the first insulator are alternately stacked along a first direction. The memory pillars penetrates through the stacked first conductor and first insulator. Each of the memory pillars include a semiconductor, a tunnel insulating film, a second insulator, and a block insulating film. The memory pillars include a first memory pillar. The stacked first insulator includes a first layer and a second layer that are adjacent to each other in the first direction. The first conductor between the first layer and the second layer includes a first conductive part, a second conductive part, and a first dissimilar conductive part.

Abstract: Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

Abstract: According to one embodiment, semiconductor memory device includes a first conductive layer, a plurality of second conductive layers stacked over the first conductive layer in a first direction, a memory pillar extending in the plurality of second conductive layers in the first direction, and a first layer extending from the first conductive layer through a portion of the plurality of second conductive layers in the first direction in contact with a the plurality of second conductive layers, the first layer including a first portion having a first cross section in the plane of second and third directions that are perpendicular to each other and to the first direction, and a second portion having a second cross section, different from the first cross section, in the plane of the second and third directions.

Abstract: A semiconductor storage device includes a first stacked body, a second stacked body, a first division film, a second division film, and a plurality of discrete films. The a first stacked body includes first electrode layers stacked in a first direction. The second stacked body, above the first stacked body, includes second electrode layers stacked in the first direction. The second semiconductor layer is electrically connected to the first semiconductor layer. The first division film, extending in the first direction through the first stacked body, divides the first stacked body in a second direction crossing the first direction. The second division film, extending in the first direction through the second stacked body, divides the second stacked body in the second direction. The discrete films, extending in the first direction through the second stacked body, are disposed above the first division film.

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

Abstract: The present disclosure provides a three-dimensional (3D) memory device and a method for forming the same. The 3D memory device can comprise a channel structure region including a plurality of channel structures; a first staircase structure in a first staircase region including a plurality of division block structures arranged along a first direction on a first side of the channel structure, and a second staircase structure in a second staircase region including a plurality of division block structures arranged along the first direction on a second side of the channel structure. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.

Abstract: An active matrix substrate according to an embodiment of the present invention includes: a substrate; a plurality of first TFTs supported by the substrate and provided in a non-displaying region; and a peripheral circuit including the plurality of first TFTs. Each first TFT includes: a first gate electrode provided on the substrate; a first gate insulating layer covering the first gate electrode; a first oxide semiconductor layer opposed to the first gate electrode via the first gate insulating layer; and a first source electrode and a first drain electrode connected to a source contact region and a drain contact region of the first oxide semiconductor layer. Each first TFT has a bottom contact structure. A first region of the first gate insulating layer that overlaps the channel region has a thickness which is smaller than a thickness of a second region of the first gate insulating layer that overlaps the source contact region and the drain contact region.

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a CMP stop layer is formed over the first ILD layer, a trench opening is formed by patterning the CMP stop layer and the first ILD layer, an underlying first process mark is formed by forming a first conductive layer in the trench opening, a lower dielectric layer is formed over the underlying first process mark, a middle dielectric layer is formed over the lower dielectric layer, an upper dielectric layer is formed over the middle dielectric layer, a planarization operation is performed on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark, and a second process mark by the lower dielectric layer is formed by removing the remaining part of the middle dielectric layer.

Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a sacrificial spacer over a substrate and forming a select gate along a side of the sacrificial spacer. An inter-gate dielectric is formed over the select gate and the sacrificial spacer. A memory gate layer is formed over the inter-gate dielectric and the sacrificial spacer. The memory gate layer is laterally separated from the sacrificial spacer by the select gate. The memory gate layer is etched to define a memory gate having a topmost point below a top of the sacrificial spacer.

Abstract: A memory device includes a channel element, a memory element, and an electrode element. The channel element has an open ring shape. A memory cell is defined in the memory element between the channel element and the electrode element.

Abstract: A semiconductor storage device of an embodiment includes a plurality of pillars extending in a predetermined direction, a plurality of first memory cells arrayed on a side surface on one side of each of the pillars along an extending direction of the pillars, a plurality of second memory cells arrayed on a side surface of on another side each of the pillars along the extending direction of the pillars, a plurality of first and second word lines arrayed in the extending direction of the pillars, and respectively connected to the first and second memory cells, and in a cell array in which the plurality of pillars is disposed, the plurality of pillars are periodically arrayed without interruption in a lead-out direction of the first word lines and the second word lines.

Abstract: According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Abstract: Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a plurality of memory strings each extending vertically above the peripheral device, a semiconductor layer disposed above and in contact with the plurality of memory strings, and a shielding layer disposed between the peripheral device and the plurality of memory strings. The shielding layer includes a conduction region configured to receive a grounding voltage during operation of the 3D memory device.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers.

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and additional insulating structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the additional insulating structures. A first trench is formed to partially vertically extend through the stack structure. The first trench comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the first trench. The dielectric structure comprises a substantially void-free section proximate the horizontal boundary of the first portion of the trench. Microelectronic devices and electronic systems are also described.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.

Abstract: A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.

Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.

Abstract: A nonvolatile memory device in which reliability is improved and a method for fabricating the same are provided. The nonvolatile memory device includes a mold structure which includes a first insulating pattern, a first gate electrode and a second insulating pattern sequentially stacked on a substrate, a semiconductor pattern which penetrates the mold structure, is connected to the substrate, and extends in a first direction, a first charge storage film extending in the first direction between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern, and a blocking insulation film between the first gate electrode and the first charge storage film, wherein a first length at which the first charge storage film extends in the first direction is longer than a second length at which the blocking insulation film extends in the first direction.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.

Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Abstract: A method is presented for forming a multi-level of interconnects underneath a complementary metal oxide semiconductor (CMOS) device. The method includes forming a stack including alternating layers of a semiconductor material and a first conductive material, patterning vias in the stack to define multiple stacks, depositing a first block material within each of the vias, forming a series of first block materials within a first via, forming a series of second block materials within a second via, the first and second vias being on opposed ends of a stack of the multiple stacks, and performing vertical metallization between the first block material and the series of first block materials in the first via, and between the first block material and the series of second block materials in the second via.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.

Abstract: Embodiments of a method for forming a three-dimensional (3D) memory device includes the following operations. First, a channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. A semiconductor channel is formed by filling the channel hole with a channel-forming structure. The plurality of first layers is removed. A plurality of conductor layers is formed from the plurality of second layers. Further, a gate-to-gate dielectric layer is formed between the adjacent conductor layers, the gate-to-gate dielectric layer including at least one sub-layer of silicon oxynitride.

Abstract: Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. Subsequently, and separate from the formation of the floating gate structures, at least a portion of the remaining nitride tier material is removed to produce control gate recesses, each adjacent a respective charge storage structure. A control gate is formed in each control gate recess, and the control gate is separated from the charge storage structure by a dielectric structure. In some examples, these dielectric structures are also formed separately from the charge storage structures.

Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process.

Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.

Abstract: An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.

Abstract: A structure of memory device is provided. The structure of memory device includes a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges. In addition, a second gate structure is disposed on the substrate. An insulating layer is in contact between the first gate structure and the second gate structure. An isolation structure integrated with the insulating layer is between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure. The isolation structure provides an isolation distance between the first gate structure and the second gate structure.