Non-homogeneous Composition Insulator Layer (e.g., Graded Composition Layer Or Layer With Inclusions) Patents (Class 257/325)
  • Patent number: 10607858
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 31, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10566446
    Abstract: Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yun-Yu Wang, Jochonia Nxumalo, Ahmad Katnani, Dimitrios Ioannou, Kenneth Bandy, Jeffrey Brown, Michael J. MacDonald
  • Patent number: 10431591
    Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Yushi Hu
  • Patent number: 10361214
    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
  • Patent number: 10283524
    Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Chet E. Carter, Collin Howder, John Mark Meldrim, Everett A. McTeer
  • Patent number: 10230022
    Abstract: A lighting apparatus is presented. The lighting apparatus includes a semiconductor light source, a color stable Mn4+ doped phosphor and a quantum dot material, each of the color stable Mn4+ doped phosphor and the quantum dot material being radiationally coupled to the semiconductor light source. A percentage intensity loss of the color stable Mn4+ doped phosphor after exposure to a light flux of at least 20 w/cm2 at a temperature of at least 50 degrees Celsius for at least 21 hours is ?4%. A backlight device including the lighting apparatus is also presented.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: March 12, 2019
    Assignee: General Electric Company
    Inventors: Anant Achyut Setlur, James Edward Murphy, Florencio Garcia, Srinivas Prasad Sista
  • Patent number: 10177043
    Abstract: A method for manufacturing multi-voltage devices is provided. The method includes forming a pair of logic gate stacks in a logic region of a semiconductor substrate and a pair of device gate stacks in a multi-voltage device region. The pair of logic gate stacks and the pair of device gate stacks include first dummy gate material. The pair of device gate stacks also includes a work function tuning layer. The method further includes depositing second dummy gate material over the pair of logic gate stacks. The first dummy gate material and the second dummy gate material from over a first logic gate stack of the pair of logic gate stacks are replaced with an n-type material. The first dummy gate material and the second dummy gate material from over a second logic gate stack of the pair of logic gate stacks are replaced with a p-type material.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Han Tsao, Chii-Ming Wu, Cheng-Yuan Tsai, Yi-Huan Chen
  • Patent number: 10170493
    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
  • Patent number: 10128258
    Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasm oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: November 13, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jeong Soo Byun, Krishnaswamy Ramkumar
  • Patent number: 9966372
    Abstract: A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a corresponding one of the trenches; a first semiconductor layer of a first conductivity type provided in a first range interposed between adjacent ones of the trenches; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; an interlayer insulation film provided on the upper surface of the semiconductor substrate and including a plurality of contact holes; a first conductor layer provided in each of the contact holes; and a surface electrode provided on the interlayer insulation film and connected to each of the first conductor layers.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: May 8, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoru Kameyama, Tadashi Misumi, Jun Okawara, Shinya Iwasaki
  • Patent number: 9899408
    Abstract: A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hwan Son, Young-Woo Park, Jae-Duk Lee
  • Patent number: 9865587
    Abstract: A semiconductor structure is provided that includes an electrostatic discharge (ESD) device integrated on the same semiconductor substrate as semiconductor fin field effect transistors (FinFETs). The ESD device includes a three-dimension (3D) wrap-around PN diode connected to the semiconductor substrate. The three-dimension (3D) wrap-around PN diode has an increased junction area and, in some applications, improved heat dissipation.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 9786674
    Abstract: Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu, Yuan-Tai Tseng
  • Patent number: 9773807
    Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
  • Patent number: 9666267
    Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Kangguo Cheng, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning
  • Patent number: 9640629
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a gate electrode. The gate electrode includes a first electrode formed on the substrate, the first electrode having a first conductive property, with a first insulating film between the first electrode and the substrate, and a second electrode formed on the substrate, the second electrode having a second conductive property different from the first conductive property, with a second insulating film between the second electrode and the substrate. The first electrode is formed in a rectangular shape having a hollow portion. A slit is formed in a side surface of the first electrode extending in a width direction of the gate electrode. The second electrode is formed in the slit and along the side surface of the first electrode that has the slit.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 2, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshitaka Miyata
  • Patent number: 9558939
    Abstract: A method for making a semiconductor device may include forming a plurality of spaced apart structures on a semiconductor substrate within a semiconductor processing chamber, with each structure including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Furthermore, the oxygen monolayers may be formed using N2O as an oxygen source.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 31, 2017
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert Stephenson, Nyles Cody
  • Patent number: 9553175
    Abstract: A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma nitridation process. The method includes forming, subsequent to the etching, a charge-trapping layer on the first oxide layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: January 24, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Helmut Puchner, Igor Polishchuk, Sagy Charel Levy
  • Patent number: 9543314
    Abstract: A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect to the control gate electrode is provided which improves its performance. A control gate electrode which configures a memory cell, and a metallic film which configures part of the memory gate electrode are formed by a so-called gate last process. Thus, the memory gate electrode is configured by a silicon film corresponding to a p-type semiconductor film being in contact with an ONO film, and the metallic film. Further, a contact plug is coupled to both of the silicon film and the metallic film which configure the memory gate electrode.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 10, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuyoshi Mihara
  • Patent number: 9496355
    Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Brenda D Kraus, Eugene P. Marsh
  • Patent number: 9257446
    Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 9, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Arigane, Daisuke Okada, Digh Hisamoto
  • Patent number: 9202817
    Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. At least one of a select gate and a main gate of the split gate memory device and a logic gate of the logic device are made of metal. The method for manufacturing the semiconductor device includes forming at least one split gate stack and at least one logic gate stack and respectively replacing at least one of a dummy gate layer and a main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and a metal logic gate.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductorr Manufacturing Co., Ltd.
    Inventors: Harry Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
  • Patent number: 9105739
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode is formed over a semiconductor substrate via an insulating film. The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film, a silicon nitride film over the first silicon oxide film, and a second silicon oxide film over the silicon nitride film. Metal elements exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1×1013 to 2×1014 atoms/cm2.
    Type: Grant
    Filed: March 2, 2013
    Date of Patent: August 11, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsunori Kaneoka, Takaaki Kawahara
  • Patent number: 9093320
    Abstract: Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 28, 2015
    Assignee: Renesas Electronic Corporation
    Inventor: Shoji Shukuri
  • Patent number: 9029937
    Abstract: A transistor in which the state of an interface between an oxide semiconductor layer and an insulating film in contact with the oxide semiconductor layer is favorable and a method for manufacturing the transistor are provided. Nitrogen is added to the vicinity of the interface between the oxide semiconductor layer and the insulating film (gate insulating layer) in contact with the oxide semiconductor layer so that the state of the interface of the oxide semiconductor layer becomes favorable. Specifically, the oxide semiconductor layer has a concentration gradient of nitrogen, and a region containing much nitrogen is provided at the interface with the gate insulating layer. A region having high crystallinity can be formed in the vicinity of the interface with the oxide semiconductor layer by addition of nitrogen, whereby the interface state can be stable.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9024365
    Abstract: A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 5, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Li-Fan Chen, Wing-Chor Chan, Jeng Gong
  • Publication number: 20150115349
    Abstract: Methods for fabricating memory devices having charged species, and methods for adjusting flatband voltages in such memory devices. In one such method, a dielectric material is formed adjacent to a semiconductor. A charged species is introduced into the dielectric material, wherein the charged species has an energy barrier in a range of greater than about 0.5 eV to about 3.0 eV. A control gate is formed adjacent to the dielectric material. A flatband voltage of the memory device can be adjusted by moving the charged species to different levels within the dielectric material, thus programming different states into the device.
    Type: Application
    Filed: January 2, 2015
    Publication date: April 30, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Roy Meade
  • Patent number: 9012975
    Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Publication number: 20150102400
    Abstract: Disclosed herein is a semiconductor device including a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion that is substantially perpendicular to the substrate. Further, disclosed herein, are methods associated with the fabrication of the aforementioned semiconductor device.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: Spansion LLC
    Inventors: Gong CHEN, Scott BELL
  • Patent number: 9006093
    Abstract: A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: April 14, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang, Jane A. Yater
  • Publication number: 20150097224
    Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: Spansion LLC
    Inventors: Lei XUE, Ching-Huang LU, Simon Siu-Sing CHAN
  • Patent number: 8987807
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shosuke Fujii, Kiwamu Sakuma, Jun Fujiki, Atsuhiro Kinoshita
  • Patent number: 8987806
    Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Matthew N. Rocklein, Rhett Brewer
  • Patent number: 8987804
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Toratani, Masayuki Tanaka, Kazuhiro Matsuo
  • Patent number: 8981461
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shosuke Fujii, Daisuke Hagishima, Kiwamu Sakuma
  • Patent number: 8975143
    Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: March 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Byoung W. Min
  • Patent number: 8969947
    Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
  • Publication number: 20150054059
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements comprising a substantially equal size within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first or second polymer species is then removed resulting with a pattern of micro-domains or the polymer matrix with a pattern of holes, which may be utilized as a hard-mask to form a substantially identical pattern of discrete storage elements through an etch, ion implant technique, or a combination thereof.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Cheng-Te Lee, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20150035045
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Misako MOROTA, Hideyuki NISHIZAWA, Masaya TERAI, Shigeki HATTORI, Koji ASAKAWA
  • Publication number: 20150035044
    Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
    Type: Application
    Filed: September 15, 2014
    Publication date: February 5, 2015
    Inventors: Tung-Sheng Chen, Shenqing Fang
  • Patent number: 8941171
    Abstract: Memory devices, methods for fabricating, and methods for adjusting flatband voltages are disclosed. In one such memory device, a pair of source/drain regions are formed in a semiconductor. A dielectric material is formed on the semiconductor between the pair of source/drain regions. A control gate is formed on the dielectric material. A charged species is introduced into the dielectric material. The charged species, e.g., mobile ions, has an energy barrier in a range of greater than about 0.5 eV to about 3.0 eV. A flatband voltage of the memory device can be adjusted by moving the charged species to different levels within the dielectric material, thus programming different states into the device.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: 8932929
    Abstract: The invention relates to a thin film transistor memory and its fabricating method. This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulating layer and the second layer metal nanocrystals grown by ALD method in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: January 13, 2015
    Assignee: Fudan University
    Inventors: Shijin Ding, Sun Chen, Xingmei Cui, Pengfei Wang, Wei Zhang
  • Patent number: 8933501
    Abstract: A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 13, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Raghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee
  • Publication number: 20150008501
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiwamu SAKUMA, Masahiro KIYOTOSHI
  • Publication number: 20150008508
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The device includes insulating patterns and conductive patterns stacked alternately, a channel layer formed through the insulating patterns and the conductive patterns, a tunnel insulating layer formed to surround sidewalls of the channel layer, and a charge storage layer formed to surround the tunnel insulating layer. An interfacial surface of the tunnel insulating layer in contact with the charge storage layer includes a thermal oxide layer.
    Type: Application
    Filed: October 16, 2013
    Publication date: January 8, 2015
    Applicant: SK hynix Inc.
    Inventor: Min Sung KO
  • Patent number: 8928064
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • Publication number: 20150001612
    Abstract: A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: CHEONG MIN HONG, SUNG-TAEG KANG, JANE A. YATER
  • Patent number: 8916923
    Abstract: According to one embodiment, in a nonvolatile semiconductor memory in which a charge store layer is formed on a tunnel insulating film formed on a channel region of a semiconductor substrate, a first nanoparticle layer containing first conductive nanoparticles is formed on the channel side, and a second nanoparticle layer containing a plurality of second conductive nanoparticles having an average particle size larger than the first conductive nanoparticles is formed on the charge store layer side. An average energy value ?E1 required for charging one electron in the first conductive nanoparticle is smaller than an average energy value ?E required for charging one electron in the second conductive nanoparticle, and a difference between ?E1 and ?E is larger than a heat fluctuation energy (kBT).
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuji Ohba
  • Patent number: 8916924
    Abstract: A method for manufacturing semiconductor device is disclosed. A substrate with a plurality of protruding strips formed vertically thereon is provided. A charging trapping layer is formed conformally on the protruding strips. A conductive layer is formed conformally on the charging trapping layer. A thin hard mask is conformally deposited on the conductive layer, wherein a plurality of trenches are formed between the thin hard mask on the protruding strips. A patterned photo resist is formed on the thin hard mask, wherein the patterned photo resist fills into the trenches. The thin hard mask is patterned according to the patterned photo resist to form a patterned hard mask layer and expose a portion of the conductive layer. The conductive layer is patterned for removing the exposed portion of the conductive layer to form a patterned conductive layer and expose a portion of the charging trapping layer.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 23, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Publication number: 20140367766
    Abstract: A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.
    Type: Application
    Filed: September 3, 2014
    Publication date: December 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshitake YAEGASHI