Vertical Channel Or Double Diffused Insulated Gate Field Effect Device Provided With Means To Protect Against Excess Voltage (e.g., Gate Protection Diode) Patents (Class 257/328)
  • Patent number: 11183572
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Keng-Ying Liao, Huai-jen Tung
  • Patent number: 11184001
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 23, 2021
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Patent number: 11177354
    Abstract: A method of manufacturing a silicon carbide device includes: forming a trench in a process surface of a silicon carbide substrate that has a body layer forming second pn junctions with a drift layer structure, wherein the body layer is between the process surface and the drift layer structure and wherein the trench exposes the drift layer structure; implanting dopants through a bottom of the trench to form a shielding region that forms a first pn junction with the drift layer structure; forming dielectric spacers on sidewalls of the trench; and forming a buried portion of an auxiliary electrode in a bottom section of the trench, the buried portion adjoining the shielding region.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 16, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder, Roland Rupp
  • Patent number: 11177254
    Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: November 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Sanjay Natarajan
  • Patent number: 11171216
    Abstract: According to an embodiment, a semiconductor device includes a first semiconductor layer, a first switching element, a second switching element, and a conductor. The conductor is provided at least in part on the first semiconductor layer and located between the first switching element and the second switching element in a first direction.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 9, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hidetoshi Asahara, Akihiro Tanaka, Toru Shono
  • Patent number: 11158735
    Abstract: A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type which separates the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source and body regions and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in a separate trench. The drift region has a generally linearly graded first doping profile which increases from the body region toward a bottom of the trench that includes the field electrode, and a graded second doping profile that increases at a greater rate than the first doping profile from an end of the first doping profile toward the drain region.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, David Laforet, Cedric Ouvrard
  • Patent number: 11158705
    Abstract: A method includes forming active regions of plurality of transistor cells in an inner region of a semiconductor body, each transistor cell includes a drift region of a first doping type and a compensation region of a second doping type, and forming a field stop region in an edge region of the semiconductor body. Forming the drift and compensation regions includes: forming a plurality of semiconductor layers; in each of the semiconductor layers, before forming a next layer, forming a plurality of first trenches and implanting dopant atoms of the first and/or second doping type into sidewalls of the plurality of first trenches. Forming the field stop region includes: in each semiconductor layer of a selection of the plurality of semiconductor layers, forming at least one second trench and implanting first and/or second type dopant atoms at least into one surface of the at least one second trench.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventor: Hans Weber
  • Patent number: 11158650
    Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 26, 2021
    Assignee: Applied Materials, Inc.
    Inventors: ChangSeok Kang, Tomohiko Kitajima
  • Patent number: 11121085
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for trench walls including widened portions and/or conductive structures including constricted portions. The trench walls may include multiple widened portions spaced apart along a length of the trench wall in some examples. Similarly, in some examples, the conductive structures may include multiple constricted portions spaced apart along a length of the conductive structure. In some examples, the dimensions of the widened portions and/or the spacing between the widened portions may be based on properties of the trench wall.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hirokazu Matsumoto, Ryota Suzuki, Mitsuki Koda, Makoto Sato
  • Patent number: 11114572
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type embedded in the semiconductor layer, a first trench and a second trench formed in the semiconductor layer such that the first trench and the second trench penetrate the second semiconductor layer, a first insulating film formed on at least a side surface of the first trench, a second insulating film formed on at least a side surface of the second trench, a first sinker layer of the second conductivity type formed in a first portion of the semiconductor layer, a second sinker layer of the second conductivity type formed in the first portion of the semiconductor layer, a diode impurity region of the first conductivity type which is formed on the first surface of the semiconductor layer and forms a Zener diode by pn junction between the first sinker layer and the diode impurity region, a first wiring electrically connected to the diode impurity region, and a second wiring
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: September 7, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Yasushi Hamazawa
  • Patent number: 11107911
    Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 31, 2021
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Shuhei Mitani, Yasuhiro Ebihara, Yusuke Yamashita, Tadashi Misumi
  • Patent number: 11107914
    Abstract: An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 31, 2021
    Inventor: Shuming Xu
  • Patent number: 11101384
    Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 24, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zong-Han Lin, Yi-Han Ye
  • Patent number: 11094809
    Abstract: A power module which includes a power semiconductor module chip, a driver chip and a charge storage element. The power semiconductor module chip is configured by forming an IGBT having a trench gate structure including a dummy trench gate, and a freewheeling diode for returning excess carrier of the emitter of the IGBT to the collector of the IGBT, in the same chip. The drive chip is used for driving the IGBT on/off. The power module is configured by packaging the power semiconductor module chip and the drive chip. The charge storage element that is connected between the gate and emitter of a dummy IGBT which can be pseudo-formed in order that the dummy trench gate be used in screening examinations.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 17, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigeki Sato
  • Patent number: 11088273
    Abstract: The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: August 10, 2021
    Assignee: NEXPERIA B.V.
    Inventors: Yan Lai, Mark Gajda, Barry Wynne, Phil Rutter
  • Patent number: 11084713
    Abstract: An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eason Hsieh, Fei-Lung Lai, Kuei-Sung Chang
  • Patent number: 11088254
    Abstract: The present disclosure provides a semiconductor device including a recessed access device (RAD) transistor and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a gate electrode, and a plurality of impurity regions. The substrate includes a buried layer. The gate electrode is disposed in the substrate and penetrates through the buried layer. The plurality of impurity regions are disposed in the substrate and on either side of the gate electrode.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 10, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Hsien Chou, Chen-Hsien Huang
  • Patent number: 11080455
    Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen, Sen-Bor Jan, Meng-Wei Chiang
  • Patent number: 11056585
    Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 6, 2021
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz
  • Patent number: 11043586
    Abstract: A semiconductor device according to an embodiment includes: a SiC layer having a first plane and a second plane facing the first plane, the SiC layer including a first trench on a first plane side, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region located in this order from the second plane to the first plane, a p-type fourth SiC region between the first SiC region and the first trench, a fifth SiC region between the first SiC region and the first plane, and a sixth SiC region between the fourth SiC region and the fifth SiC region, and the sixth SiC region having an n-type impurity concentration higher than an n-type impurity concentration of the first SiC region; a gate electrode in the first trench; a first electrode on the first plane side; and a second electrode on a second plane side.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 22, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinya Kyogoku, Ryosuke Iijima, Shinichi Kimoto, Katsuhisa Tanaka
  • Patent number: 11043585
    Abstract: Reliability of a semiconductor device is improved. The semiconductor device including a first MISFET group of a plurality of first MISFETs and a second MISFET group of a plurality of second MISFETs has a plurality of trenches each formed in a semiconductor layer and formed of an upper trench part and a lower trench part, and a plurality of gate electrodes formed inside the plurality of trenches. A thinner gate insulator is formed to the upper trench part and a thicker field insulator is formed to the lower trench part. In a trench at the outermost position in the first MISFET group and a trench at the outermost position in the second MISFET group, the gate insulator is not formed in the upper trench part, but the field insulator is formed in the upper trench part and the lower trench part.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: June 22, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Wataru Sumida
  • Patent number: 11024718
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Patent number: 11011529
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11004945
    Abstract: A semiconductor device includes: a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; rows of spicular-shaped field plate structures formed in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; stripe-shaped gate structures formed in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and a current spread region of the first conductivity type formed below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures. The current spread region is configured to increase channel current distribution in the semiconductor mesas.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Michael Hutzler
  • Patent number: 10991823
    Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10962585
    Abstract: A testing environment includes a first measuring unit connected to a gate of a MOSFET device and a second measuring unit connected to a drain of the MOSFET device. The testing environment is particularly useful for testing gate charge for MOSFET devices. In a first phase, the gate of the device is driven with electrical current while the drain is driven with a constant voltage. As the MOSFET device turns on, the second measuring unit switches from providing the constant voltage to providing a constant current to the drain of the MOSFET, while measuring the drain voltage. The switching of modes is automatic and occurs without user intervention. After the MOSFET device has been driven to VgsMax by the gate current, all of the relevant data is stored, which may be analyzed and presented to a user in a User Interface or presented in other manner.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 30, 2021
    Assignee: Keithley Instruments, LLC
    Inventors: Alexander N. Pronin, Mary Anne Tupta
  • Patent number: 10938382
    Abstract: An electronic circuit according to one aspect of the present technology includes an MOS circuit portion and a stabilizing element portion. The MOS circuit portion includes a deep well. The stabilizing element portion includes a first element portion arranged between a power supply source and the deep well, and stabilizes a potential of the deep well.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 2, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Osamu Ozawa, Takahiro Naito, Tatsuo Kuroiwa, Kenichi Tayu
  • Patent number: 10938384
    Abstract: A pulse modulator comprises a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground. One pulse modulator comprises a plurality of stages connected as an induction adder. Each stage includes a plurality of cells and at least some of the cells each include a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground to control the discharge of a capacitor. In one embodiment the solid state power switch is a power MOSFET.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: March 2, 2021
    Assignee: TELEDYNE UK LIMITED
    Inventor: Paul Anthony James Garner
  • Patent number: 10931276
    Abstract: An apparatus comprising an insulated gate bipolar transistor; and a super-junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor wherein the super-junction metal-oxide semiconductor field effect transistor are structurally coupled and wherein the super-junction metal-oxide semiconductor field effect transistor is configured to switch to an ‘on’ state from an ‘off’ state and an ‘off’ state from an ‘on’ state.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 23, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Bum-Seok Suh, Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan
  • Patent number: 10923592
    Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 16, 2021
    Assignee: pSemi Corporation
    Inventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
  • Patent number: 10910361
    Abstract: Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element (50) includes a first MOS transistor (Tr1), a second MOS transistor (Tr2), and a temperature detecting element (TD) that are provided on a semiconductor substrate (SB). The first MOS transistor (Tr1) includes an n-type source region (8), an n-type first semiconductor region (21) arranged away from the source region (8) and a p-type well region (31) arranged between the source region (8) and the first semiconductor region (21). The second MOS transistor (Tr2) includes an n-type source region (8) an n-type second semiconductor region (22) arranged away from the source region (8), and a p-type well region (31) arranged between the source region (8) and the second semiconductor region (22). The first semiconductor region (21) is connected to the second semiconductor region (22).
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 2, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeyoshi Nishimura, Isamu Sugai
  • Patent number: 10903201
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate including a high-frequency-block group and a low-power-block group; high-frequency-type logic standard cells located on the high-frequency-block group, and having a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power; low-power-type logic standard cells located on the low-power-block group, and having a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power. The high-frequency-type cell height is higher than the low-power-type cell height. The high-frequency-type operating frequency is greater than the low-power-type operating frequency. The high-frequency-type power is greater than the low-power-type power. The high-frequency-type logic standard cells include high-frequency-type fins, and the low-power-type logic standard cells include low-power-type fins.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 26, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventors: Xin Gui Zhang, Yao Qi Dong
  • Patent number: 10896961
    Abstract: A semiconductor device is provided comprising an active portion and a terminating structure. The semiconductor device is provided comprising the active portion provided in the semiconductor substrate and a terminating structure provided at a termination of the front surface side of the semiconductor substrate and that mitigates an electric field of the termination. In the electric field distribution of the front surface side of the terminating structure, during rated voltage application, an electric field at the end portion of the active portion side may be smaller than a maximum value of an electric field distribution of the front surface side. In addition, the electric field distribution of the terminating structure may have a maximum peak of the electric field on the edge side opposite to the active portion with respect to a center of the terminating structure.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 19, 2021
    Inventors: Daisuke Ozaki, Ryouichi Kawano
  • Patent number: 10892342
    Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 12, 2021
    Inventors: Wonkeun Chung, Jae-Jung Kim, Jinkyu Jang, Sangyong Kim, Hoonjoo Na, Dongsoo Lee, Sangjin Hyun
  • Patent number: 10886397
    Abstract: A semiconductor device has an active region through which current flows and a termination structure region. At a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. At a surface of the first semiconductor layer, a lower parallel pn structure is provided. At a surface of the lower parallel pn structure, an upper parallel pn structure is provided in the termination structure region and a first semiconductor region of a second conductivity type is provided in the active region. A width of an upper second column is wider than a width of a lower second column. An interval between the upper second columns is wider than an interval between the lower second columns. A thickness of the upper second column is thicker than a thickness of the first semiconductor region.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryo Maeta
  • Patent number: 10879692
    Abstract: There is a need to provide a semiconductor device and an electronic control system including the same while the semiconductor device is capable of continuing normal operation even when a negative surge voltage is applied. According to an embodiment, a driver IC includes an output transistor, a driver control circuit, a negative potential clamp circuit, and an ESD protection circuit. The output transistor is provided between a battery voltage terminal and an output terminal coupled to a load. The driver control circuit switches on-off state of the output transistor by controlling a gate voltage of the output transistor with reference to a voltage of the output terminal. The negative potential clamp circuit turns on the output transistor regardless of control from the control circuit when a negative voltage lower than a predetermined voltage is applied to the output terminal.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuaki Kubo, Koichiro Hashimoto
  • Patent number: 10867931
    Abstract: Disclosed herein is a MOS transistor embedded substrate that includes first and second MOS transistors each having a source electrode formed on one surface and a drain electrode formed on other surface, and an insulation resin layer in which the first and second MOS transistors are embedded such that the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor face a same direction and that the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor face a same direction.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 15, 2020
    Assignee: TDK CORPORATION
    Inventors: Hironori Chiba, Toshiyuki Abe
  • Patent number: 10868173
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10847648
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, a gate electrode, first, and second conductive parts. The first semiconductor region includes a first region and a second region. The second semiconductor region is provided on the first region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The gate electrode opposes the second semiconductor region in a second direction. The first conductive part is provided on the second region and is provided in a plurality in a third direction. The first conductive parts are arranged with the gate electrode in the second direction. The second conductive part is provided on the second region, and arranged with the gate electrode and the first conductive parts in the third direction.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 24, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Saya Shimomura, Kenya Kobayashi
  • Patent number: 10840148
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate, forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped. In the method, a bottom spacer layer is formed on the first and second bottom source/drain regions, and the bottom spacer layer is removed from the second bottom source/drain region. A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region. The method also includes forming a gate conductor on the high-k dielectric layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Ruilong Xie, Chanro Park
  • Patent number: 10832915
    Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10825926
    Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10818673
    Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hong Li, Ramaswamy Ishwar Venkatanarayanan, Sanh D. Tang, Erica L. Poelstra
  • Patent number: 10804391
    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 13, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INTERNATIONAL BUSINESS NIACHINES CORPORATION
    Inventors: Tae Yong Kwon, Kang Ill Seo, Oh Seong Kwon, Ki Sik Choi
  • Patent number: 10797170
    Abstract: A semiconductor device according to an exemplary embodiment of the present invention includes an n? type epitaxial layer disposed on a first surface of a substrate; a p type region disposed on the n? type epitaxial layer, an n+ type region disposed on the p type region, a gate disposed on the n? type epitaxial layer, an oxidation film disposed on the gate, a source electrode disposed on the oxidation film and the n+ type region, and a drain electrode disposed on a second surface of the substrate. The gate includes a PN junction portion.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: October 6, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: NackYong Joo
  • Patent number: 10790282
    Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Jung Choi, Dong-Hyun Roh, Sung-Soo Kim, Gyu-Hwan Ahn, Sang-Jin Hyun
  • Patent number: 10784171
    Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna
  • Patent number: 10777421
    Abstract: Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. Microelectronic devices including first and second fins that are laterally offset by a fin pitch to define a first field there between are also described. In embodiments the microelectronic devices include a conformal oxide layer and a conformal nitride layer on at least a portion of the first and second fins, where the conformal nitride layer is on at least a portion of the conformal oxide layer and a sacrificial oxide material is disposed within the first field.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Jason A. Farmer, Gopinath Trichy, Justin S. Sandford, Daniel B. Bergstrom
  • Patent number: 10763344
    Abstract: A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 1, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: RE48259
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 13, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kouta Tomita, Noboru Matsuda, Hideyuki Ura