Vertical Channel Or Double Diffused Insulated Gate Field Effect Device Provided With Means To Protect Against Excess Voltage (e.g., Gate Protection Diode) Patents (Class 257/328)
  • Patent number: 10847648
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, a gate electrode, first, and second conductive parts. The first semiconductor region includes a first region and a second region. The second semiconductor region is provided on the first region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The gate electrode opposes the second semiconductor region in a second direction. The first conductive part is provided on the second region and is provided in a plurality in a third direction. The first conductive parts are arranged with the gate electrode in the second direction. The second conductive part is provided on the second region, and arranged with the gate electrode and the first conductive parts in the third direction.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 24, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Saya Shimomura, Kenya Kobayashi
  • Patent number: 10840148
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate, forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped. In the method, a bottom spacer layer is formed on the first and second bottom source/drain regions, and the bottom spacer layer is removed from the second bottom source/drain region. A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region. The method also includes forming a gate conductor on the high-k dielectric layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Ruilong Xie, Chanro Park
  • Patent number: 10832915
    Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10825926
    Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10818673
    Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hong Li, Ramaswamy Ishwar Venkatanarayanan, Sanh D. Tang, Erica L. Poelstra
  • Patent number: 10804391
    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 13, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INTERNATIONAL BUSINESS NIACHINES CORPORATION
    Inventors: Tae Yong Kwon, Kang Ill Seo, Oh Seong Kwon, Ki Sik Choi
  • Patent number: 10797170
    Abstract: A semiconductor device according to an exemplary embodiment of the present invention includes an n? type epitaxial layer disposed on a first surface of a substrate; a p type region disposed on the n? type epitaxial layer, an n+ type region disposed on the p type region, a gate disposed on the n? type epitaxial layer, an oxidation film disposed on the gate, a source electrode disposed on the oxidation film and the n+ type region, and a drain electrode disposed on a second surface of the substrate. The gate includes a PN junction portion.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: October 6, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: NackYong Joo
  • Patent number: 10790282
    Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Jung Choi, Dong-Hyun Roh, Sung-Soo Kim, Gyu-Hwan Ahn, Sang-Jin Hyun
  • Patent number: 10784171
    Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna
  • Patent number: 10777421
    Abstract: Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. Microelectronic devices including first and second fins that are laterally offset by a fin pitch to define a first field there between are also described. In embodiments the microelectronic devices include a conformal oxide layer and a conformal nitride layer on at least a portion of the first and second fins, where the conformal nitride layer is on at least a portion of the conformal oxide layer and a sacrificial oxide material is disposed within the first field.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Jason A. Farmer, Gopinath Trichy, Justin S. Sandford, Daniel B. Bergstrom
  • Patent number: 10763344
    Abstract: A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 1, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10748780
    Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and on which a base layer is formed is prepared, a trench is provided in the base layer, a silicon carbide layer is epitaxially formed on a surface of the base layer while filling the trench with the silicon carbide layer, the sacrificial layer is planarized by reflow after forming the sacrificial layer, and the silicon carbide layer is etched back together with the planarized sacrificial layer by dry etching under an etching condition in which an etching selectivity of the silicon carbide layer to the sacrificial layer is 1.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 18, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shigeyuki Takagi, Masaki Shimomura, Yuichi Takeuchi, Katsumi Suzuki, Sachiko Aoi
  • Patent number: 10734498
    Abstract: A four-terminal GaN transistor and methods of manufacture, the transistor having source and drain regions and preferably two T-shaped gate electrodes, wherein a stem of one of the two T-shaped gate electrodes is more closely located to the source region than it is to a stem of the other one of the two T-shaped gate electrodes and wherein the stem of the other one of the two T-shaped gate electrodes is more closely located to the drain region than it is to the stem of said one of the two T-shaped gate electrodes. The the gate closer to the source region is a T-gate, and the proximity of the two gates is less than 500 nm from each other. The spacing between the stem of the RF gate and source region and the stem of the DC gate and drain region are preferably defined by self-aligned fabrication techniques. The four-terminal GaN transistor is capable of operation in the W-band (75 to 100 GHz).
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 4, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Jeong-Sun Moon, Yan Tang
  • Patent number: 10727348
    Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Hoon Kim, Bon-Young Koo, Nam-Kyu Kim, Woo-Bin Song, Byeong-Chan Lee, Su-Jin Jung
  • Patent number: 10727331
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10712208
    Abstract: A semiconductor die includes a single power transistor or power diode, a temperature sense diode formed close enough to the single power transistor or power diode to measure an accurate temperature. The temperature sense diode comprises first and second diodes or strings of diodes. A separate integrated circuit is operable to measure first and second voltage drops of both the first and second diodes or strings of diodes using same magnitude currents, and estimate the temperature of the single power transistor or power diode based on the difference between the first and second forward voltage drop measurements. An overall pn junction area of the first diode or string of first diodes is different from an overall pn junction area of the second diode or string of second diodes.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Kiep, Holger Ruething, Frank Wolter
  • Patent number: 10707155
    Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 7, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hajime Okuda, Yoshinori Fukuda
  • Patent number: 10700193
    Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyun Yoo, Ui-hui Kwon, Da-won Jeong, Jae-ho Kim, Jun-hyeok Kim, Kang-hyun Baek, Kyu-ok Lee
  • Patent number: 10692772
    Abstract: Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xuefeng Liu, Heng Wu, Peng Xu
  • Patent number: 10692972
    Abstract: A field effect transistor semiconductor device having a compact device footprint for use in automotive and hot swap applications. The device includes a plurality of field effect transistor cells with the plurality of transistor cells having at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell arranged on a substrate. The field effect transistor semiconductor device is configured and arranged to operate the at least one high threshold voltage transistor cell during linear mode operation, and operate both the low threshold voltage transistor cell and the high threshold voltage transistor cell during resistive mode operation. Further provided is a method of operating field effect transistor semiconductor device including a plurality of field effect transistor cells that includes at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: June 23, 2020
    Assignee: Nexperia B.V.
    Inventors: Adam Richard Brown, Jim Brett Parkin, Phil Rutter, Steven Waterhouse, Saurabh Pandey
  • Patent number: 10692871
    Abstract: Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10679998
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10679687
    Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 10680082
    Abstract: Method and structure of forming a vertical FET. The method includes depositing a bottom source-drain layer over a substrate; depositing a first heterostructure layer over the bottom source-drain layer; depositing a channel layer over the first heterostructure layer; depositing a second heterostructure layer over the channel layer; forming a first fin having a hard mask; recessing the first and the second heterostructure layers to narrow them; filling gaps with an inner spacer; laterally trimming the channel layer to a narrower width; depositing a bottom outer spacer over the bottom source-drain layer; depositing a high-k layer on the bottom outer spacer, the first fin, and the hard mask; and depositing a metal gate layer over the high-k and top outer spacer to produce the vertical FET. Forming another structure by recessing the metal gate layer below the second inner spacer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tenko Yamashita, Chen Zhang
  • Patent number: 10672902
    Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 2, 2020
    Assignee: NXP USA, Inc.
    Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
  • Patent number: 10665715
    Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praveen Joseph, Indira Seshadri, Ekmini A. De Silva, Stuart A. Sieg
  • Patent number: 10658360
    Abstract: On a front surface side of an n? semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n+ emitter region are the IGBT emitter region and the p base layers not having the n+ emitter region are the FWD anode region. A lateral width of an n+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n+ cathode region is 50 ?m or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 19, 2020
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Souichi Yoshida, Masaki Tamura, Kenji Kouno, Hiromitsu Tanabe
  • Patent number: 10651277
    Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Natsuo Yamaguchi, Satoshi Eguchi
  • Patent number: 10643941
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate provided in a chip-scale package (CSP). The device also includes a plurality of contacts provided on a major surface of the substrate. The device further includes an electrically floating metal layer forming an ohmic contact on a backside of the semiconductor substrate. The device is operable to conduct a current that passes through the substrate from a first of said plurality of contacts to a second of said plurality of contacts via the metal layer on the backside.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 5, 2020
    Assignee: Nexperia B.V.
    Inventors: Zhihao Pan, Friedrich Hahn, Steffen Holland, Olaf Pfennigstorf, Jochen Wynants, Hans-Martin Ritter
  • Patent number: 10644102
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a combination of shielded trench gate structure and a superjunction structure within an epitaxial layer including alternating n-doped and p-doped columns in an a drift region. In one example the gate trenches are formed in and over n-doped columns that have an extra charge region near and adjacent to the lower portion of the corresponding gate trench. The extra charge is balanced due to the shield electrodes in the gate trenches.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 5, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Karthik Padmanabhan, Lingpeng Guan, Madhur Bobde, Jian Wang, Lei Zhang
  • Patent number: 10615264
    Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Wonkeun Chung, Jae-Jung Kim, Jinkyu Jang, Sangyong Kim, Hoonjoo Na, Dongsoo Lee, Sangjin Hyun
  • Patent number: 10608681
    Abstract: A transmission device according to an embodiment of the present disclosure includes three output terminals that are arranged in one line and three sets of inductor elements and ESD protection elements that are provided for the respective output terminals. The three output terminals are respectively coupled to three transmission paths. The three sets of the inductor elements and the ESD protection elements are arranged in a non-orthogonal direction with respect to a direction in which the three output terminals are arranged. The transmission device further includes a driver circuit that outputs three actuation signals to the respective three output terminals through the respective three sets of the inductor elements and the ESD protection elements.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: March 31, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Tatsuya Sugioka
  • Patent number: 10607987
    Abstract: A BIPOLAR-CMOS-DMOS (BCD) semiconductor device and manufacturing method, which can integrate a Junction Field-Effect Transistor (JFET), two classes of Vertical Double-diffusion Metal Oxide Semiconductor (VDMOS), a Lateral Insulated-Gate Bipolar Transistor (LIGBT) and seven kinds of Laterally Diffused Metal Oxide Semiconductor (LDMOS), a low-voltage Negative channel Metal Oxide Semiconductor (NMOS), a low-voltage Positive channel Metal Oxide Semiconductor (PMOS), a low-voltage Negative-Positive-Negative (NPN) transistor and a low-voltage Positive-Negative-Positive (PNP) transistor, and a diode in the same chip. Bipolar devices in the analog circuit, power components in the switch circuit, Complementary Metal Oxide Semiconductor (CMOS) devices in the logic circuit and other kinds of lateral and vertical components are integrated. This present invention saves costs at the same time greatly improve chip integration.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 31, 2020
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Ming Qiao, Song Pu, Bo Zhang
  • Patent number: 10608077
    Abstract: A semiconductor device includes a substrate of a first conductivity type with relatively low impurity concentration; a first region of a second conductivity type with relatively low impurity concentration, =located in the substrate; a second region of the first conductivity type with relatively high impurity concentration, located in the substrate; first and second conductors, located on the first region and separated from each other by an isolator layer; and a third conductor, separated from the first and second conductors by the isolator layer, and located on the second region. The first conductor provides a drain terminal. The second conductor provides a source terminal. The third conductor provides a gate terminal.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 31, 2020
    Assignee: Mosway Technologies Limited
    Inventors: Chi Keung Tang, Peter On Bon Chan
  • Patent number: 10600810
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
  • Patent number: 10601413
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 24, 2020
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Patent number: 10593791
    Abstract: A semiconductor structure with current flow path direction controlling is provided, which comprises a substrate and an epitaxial layer having a first conductivity type on the substrate. A first doped region is on the substrate and the first doped region has the first or a second conductivity type. A second doped region is enclosed by the epitaxial layer and has the second conductivity type. A third doped region is located in the epitaxial layer and between the first and second doping regions, and the third doped region has the second conductivity type. A fourth doped region is enclosed by the third doped region and has the first conductivity type. A fifth doped region is enclosed by the first doped region and the conductivity type is opposite to that of the first doped region.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 17, 2020
    Inventor: Chii-Wen Jiang
  • Patent number: 10593782
    Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 17, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Cheng Chi, Fee Li Lie, Chi-Chun Liu, Ruilong Xie
  • Patent number: 10593665
    Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 17, 2020
    Assignee: Raytheon Company
    Inventors: John P. Bettencourt, Raghuveer Mallavarpu
  • Patent number: 10593692
    Abstract: A NOR-type three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a substrate, and laterally alternating sequences of respective active region pillars and respective memory stack structures. Each laterally alternating sequence is electrically isolated from the electrically conductive layers by a respective blocking dielectric layer at each level of the electrically conductive layers. Each memory stack structures include a memory film and a semiconductor channel material portion that vertically extend through the vertically alternating stack. The active region pillars include an alternating sequence of source pillar and drain pillars.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 17, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hanan Borukhov
  • Patent number: 10580861
    Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 3, 2020
    Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.
    Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
  • Patent number: 10580873
    Abstract: In an embodiment, a power semiconductor device includes: a semiconductor body for conducting a load current between first and second load terminals; source and channel regions and a drift volume in the semiconductor body; a semiconductor zone in the semiconductor body and coupling the drift volume to the second load terminal, a first transition established between the semiconductor zone and the drift volume; a control electrode insulated from the semiconductor body and the load terminals and configured to control a path of the load current in the channel region; and a trench extending into the drift volume along an extension direction and including a field electrode. A cross-sectional area of the field electrode is smaller than a cross-sectional area of the control electrode in a plane parallel to the extension direction.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Patent number: 10573731
    Abstract: A vertical semiconductor field-effect transistor includes a semiconductor body having a front side, and a field electrode trench extending from the front side into the semiconductor body. The field electrode trench includes a field electrode and a field dielectric arranged between the field electrode and the semiconductor body. The vertical semiconductor field-effect transistor further includes a gate electrode trench arranged next to the field electrode trench, extending from the front side into the semiconductor body, and having two electrodes which are separated from each other and the semiconductor body. A front side metallization is arranged on the front side and in contact with the field electrode and at most one of the two electrodes.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: February 25, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Li Juin Yip, Cesar Augusto Braz, Olivier Guillemant, David Laforet, Cedric Ouvrard
  • Patent number: 10566359
    Abstract: A pixel cell includes a photodiode disposed in a semiconductor material to accumulate image charge in response to incident light and a global shutter gate transistor coupled to the photodiode to selectively deplete the image charge from the photodiode. A storage transistor is disposed in the semiconductor material to store the image charge. An isolation structure is disposed in the semiconductor material proximate to the storage transistor to isolate a sidewall of the storage transistor from stray light and stray charge. The isolation structure is filled with tungsten and is coupled to receive a variable bias signal to control a bias of the isolation structure. The variable bias signal is set to a first bias value during a transfer of the image charge to the storage transistor. The variable bias signal is set to a second bias value during a transfer of the image charge from the storage transistor.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 18, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventor: Kevin Ka Kei Leung
  • Patent number: 10559660
    Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minhyun Lee, Haeryong Kim, Hyeonjin Shin, Seunggeol Nam, Seongjun Park
  • Patent number: 10541327
    Abstract: A semiconductor device includes a trench structure extending into a semiconductor body from a first surface. The trench structure has a shield electrode, a dielectric structure and a diode structure. The diode structure is arranged at least partly between the first surface and a first part of the dielectric structure. The shield electrode is arranged between the first part of the dielectric structure and a bottom of the trench structure. The shield electrode and the semiconductor body are electrically isolated by the dielectric structure. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Franz Hirler
  • Patent number: 10541331
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shogo Mochizuki, Junli Wang
  • Patent number: 10535755
    Abstract: A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10535652
    Abstract: A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: RE48259
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 13, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kouta Tomita, Noboru Matsuda, Hideyuki Ura