Vertical Channel Or Double Diffused Insulated Gate Field Effect Device Provided With Means To Protect Against Excess Voltage (e.g., Gate Protection Diode) Patents (Class 257/328)
  • Patent number: 10396216
    Abstract: In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 27, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yi Su, Ashok Challa, Tirthajyoti Sarkar, Min Kyung Ko
  • Patent number: 10395972
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: August 27, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Da Soon Lee, Hyung Suk Choi, Jeong Gyu Park, Gil Ho Lee, Hyun Tae Jung, Meng An Jung, Woo Sig Min, Pil Seung Kang
  • Patent number: 10396067
    Abstract: A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor body includes a load current component having a load current transistor area and a sensor component having a sensor transistor area. The load current transistor area and the sensor transistor area share a same transistor unit construction. The load current transistor area includes first and second transistor area parts, and the sensor transistor area includes a third transistor area part. The first and the third transistor area parts differ from the second transistor area part between the first and the third transistor area parts by a load current transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and second transistor area parts by the load current transistor area element being absent in the second transistor area part.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Stefan Decker, Robert Illing, Michael Nelhiebel
  • Patent number: 10388795
    Abstract: A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 10388726
    Abstract: Systems and methods herein are directed towards semiconductor devices and methods of manufacture thereof, including the formation of a plurality of passive trenches that act as a single passive trench and may be connected to gate electrodes and/or emitters in various embodiments.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Meng-Chia Lee, Ralph N. Wall
  • Patent number: 10388791
    Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Hoon Kim, Bon-Young Koo, Nam-Kyu Kim, Woo-Bin Song, Byeong-Chan Lee, Su-Jin Jung
  • Patent number: 10381451
    Abstract: A semiconductor device includes a pillar-shaped semiconductor layer formed on a substrate; a first insulator surrounding the pillar-shaped semiconductor layer; a first gate surrounding the first insulator and made of a metal having a first work function; a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, the second gate being located below the first gate; a third gate surrounding the first insulator and made of a metal having the first work function, the third gate being located below the second gate; and a fourth gate surrounding the first insulator and made of a metal having the second work function different from the first work function, the fourth gate being located below the third gate. The first gate, the second gate, the third gate, and the fourth gate are electrically connected together.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: August 13, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10381244
    Abstract: The power module includes: a first metallic circuit pattern, a semiconductor device disposed on the first metallic circuit pattern; a leadframe electrically connected to the semiconductor device; and a stress buffering layer disposed on an upper surface of the semiconductor device, and capable of buffering a CTE difference between the semiconductor device and the leadframe. The leadframe is connected to the semiconductor device via the stress buffering layer, a CTE of the stress buffering layer is equal to or less than a CTE of the leadframe, and a cross-sectional shape of the stress buffering layer is L-shape. There is provided: the power module capable of realizing miniaturization and large current capacity, and reducing cost thereof by using leadframe structure, and capable of reducing a variation in welding and improving a yield without damaging a semiconductor device; and a fabrication method for such a power module.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 13, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Katsuhiko Yoshihara, Masao Saito
  • Patent number: 10374106
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDARIES INC.
    Inventor: Ajey P. Jacob
  • Patent number: 10374076
    Abstract: In a general aspect, a power semiconductor device can include a semiconductor region having an active region and a termination region. The device can also include a plurality of trench shield electrodes each having a first portion disposed in the active region and a second portion disposed in the termination region. One or more of the trench shield electrodes can have a second portion that extends a first distance into the termination region, while one or more other trench shield electrodes can have a second portion that extends a second distance into the termination region, the second distance being less than the first distance. The trench shield electrode(s) having the second portion that extends the second distance into the termination region can be interleaved with the trench shield electrode(s) having the second portion that extends the first distance into the termination region.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Xiaoli Wu, Joseph Yedinak
  • Patent number: 10374078
    Abstract: A semiconductor device includes a plurality of striped-shaped trenches extending into a semiconductor substrate. At least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches. A gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches. Trench insulation material is located in each trench of the first group of trenches. A thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Britta Wutte
  • Patent number: 10373921
    Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 10374081
    Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of this element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region, and in contact with the gate insulation layer on a lower side of the body region. The bottom region includes a low concentration region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench; and a high concentration region in contact with the gate insulation layer in a second range of the bottom surface adjacent to the first range.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: August 6, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Sachiko Aoi, Yasushi Urakami
  • Patent number: 10366994
    Abstract: Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10367091
    Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of the element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench, and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region. The bottom region includes a first bottom region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench and extending from the bottom surface to a first position; and a second bottom region in contact with the gate insulation layer in a second range adjacent to the first range and extending from the bottom surface to a second position lower than the first position.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: July 30, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Sachiko Aoi, Yasushi Urakami
  • Patent number: 10355116
    Abstract: A power semiconductor device includes: a semiconductor body coupled to a first load terminal and a second load terminal, and includes: a first doped region of a second conductivity type electrically connected to the first load terminal; a recombination zone arranged at least within the first doped region; an emitter region of the second conductivity type electrically connected to the second load terminal; and a drift region of a first conductivity type arranged between the first doped region and the emitter region. The drift region and the first doped region enable the power semiconductor device to operate in: a conducting state during which a load current between the load terminals is conducted along a forward direction; in a forward blocking state during which a forward voltage applied between the load terminals is blocked; and in a reverse blocking state during which a reverse voltage applied between the terminals is blocked.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Bina, Thomas Basler, Matteo Dainese, Hans-Joachim Schulze
  • Patent number: 10355104
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu, Hsien-Ching Lo, Joseph F. Shepard, Jr., Shesh Mani Pandey
  • Patent number: 10347756
    Abstract: An embodiment of the invention shows a high-voltage MOS field-effect transistor connected in series with a Schottky diode. When the Schottky diode is forwardly biased, the high-voltage MOSFET can act as a switch and sustain a high drain-to-source voltage. When the Schottky diode is reversely biased, the Schottky diode can protect the integrate circuit where the high-voltage MOSFET is formed, because the integrate circuit might otherwise burn out due to an exceedingly-large reverse current.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 9, 2019
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Kuo-Chin Chiu, Cheng-Sheng Kao
  • Patent number: 10347735
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 9, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keishirou Kumada, Yuichi Hashizume, Yasuyuki Hoshi
  • Patent number: 10340266
    Abstract: Methods of forming a high voltage ESD GGNMOS using embedded gradual PN junction in the source region and the resulting devices are provided. Embodiments include a device having a substrate including a device region with an ESD protection circuit; a gate over the device region; a source region in the device region having a N+ implant and a P+ implant laterally separated on a first side of the gate; and a drain region in the device region on a second side of the gate, opposite the first.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yohann Frederic Michel Solaro, Chai Ean Gill, Tsung-Che Tsai
  • Patent number: 10332993
    Abstract: A semiconductor device with a simplified structure including an energization control element and reverse coupling protection element, and a manufacturing method therefor. Its semiconductor substrate has deep and shallow trenches in its first surface. A first n-type impurity region lies in its second surface in contact with the deep trench bottom. A p-type impurity region includes: a p-type base region to make a pn junction with the first n-type region and in contact with the shallow trench bottom; and a back gate region joined to the p-type base region, lying in the first surface. A second n-type impurity region makes a pn junction with the p-type impurity region, lying in the first surface in contact with the shallow trench side face. An n+ source region makes a pn junction with the p-type region, lying in the first surface in contact with the side faces of deep and shallow trenches.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhisa Mori
  • Patent number: 10332992
    Abstract: A semiconductor device according to one or more embodiments may include: a drain region; a drift region positioned above the drain region; a base region positioned on the drift region; a trench positioned to abut the base region and the drift region; an insulating in the trench; a counter electrode embedded in the insulating film; a gate electrode positioned above the counter electrode and that is embedded in the insulating film; and a source region that abuts the base region and the trench, wherein a thickness of the insulating film between the gate electrode and an interface between the drift region and the base region is larger than a thickness of the insulating film between the gate electrode and an interface between the source region and the base region.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: June 25, 2019
    Assignees: SANKEN ELECTRIC CO., LTD., Polar Semiconductor, LLC.
    Inventor: Taro Kondo
  • Patent number: 10326023
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Chien-Chang Su, Wang-Chun Huang, Yasutoshi Okuno
  • Patent number: 10326019
    Abstract: A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Robert H. Dennard, Bruce B. Doris, Terence B. Hook
  • Patent number: 10319848
    Abstract: A transistor includes a semiconductor body; a first gate electrode formed on a first portion of the semiconductor body and a second gate electrode formed on a second portion of the semiconductor body. A drain region is formed on a first side of the first gate electrode and a first source region is formed on a second side of the first gate electrode. The drain region is formed on a first side of the second gate electrode and a second source region is formed on a second side of the second gate electrode. A trench is formed in the semiconductor body and positioned in the drain region. A doped sidewall region is formed in the semiconductor body along the sidewall of the trench outside of the trench. The doped sidewall region is in electrical contact with the drain region and forms a vertical drain current path for the transistor.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 11, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Patent number: 10319854
    Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 11, 2019
    Assignee: pSemi Corporation
    Inventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
  • Patent number: 10319712
    Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Baiocchi
  • Patent number: 10312151
    Abstract: Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10304946
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea, Tahir Ghani
  • Patent number: 10304829
    Abstract: A device includes a vertical transistor and a lateral transistor on a substrate, wherein the vertical transistor comprises a first gate in a first trench, a second gate in a second trench, a source and a drain, wherein the source and the drain are on opposite sides of the first trench and the lateral transistor and the drain are on opposite sides of the second trench.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10297684
    Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 21, 2019
    Assignee: NXP USA, Inc.
    Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
  • Patent number: 10290732
    Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 14, 2019
    Assignee: Monolith Semiconductor Inc.
    Inventors: Kevin Matocha, Kiran Chatty, Sujit Banerjee
  • Patent number: 10290703
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 14, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 10290704
    Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 14, 2019
    Assignee: HITACHI, LTD.
    Inventors: Naoki Tega, Naoki Watanabe, Shintaroh Sato
  • Patent number: 10276573
    Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: April 30, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10276670
    Abstract: A semiconductor device includes an array of needle-shaped trenches extending into a semiconductor substrate. The semiconductor device further includes a gate trench grid extending into the semiconductor substrate. A gate electrode of a transistor structure is located within the gate trench grid. A gate wiring structure of the transistor structure is connected to the gate electrode of the transistor structure. A field electrode located within at least one needle-shaped trench of the array of needle-shaped trenches is connected to the gate wiring structure of the transistor structure.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Li Juin Yip
  • Patent number: 10269936
    Abstract: A method for forming a semiconductor device includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process, reshaping the first recess to form a reshaped first recess using a second etching process, wherein the second etching process etches upper portions of the fin adjacent the top of the recess more than the second etching process etches lower portions of the fin adjacent the bottom of the recess, and epitaxially growing a source/drain region in the reshaped first recess. Reshaping the first recess includes performing an oxide etch process, wherein the oxide etch process forms a porous material layer within the recess.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Rung Hsu
  • Patent number: 10269954
    Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yogendra Yadav, Chi-Chih Chen, Ruey-Hsin Liu, Chih-Wen Yao
  • Patent number: 10269953
    Abstract: A semiconductor device includes a gate structure extending from a first surface into a semiconductor portion and having a metal gate electrode and a gate dielectric separating the metal gate electrode from the semiconductor portion. An interlayer dielectric separates a first load electrode from the semiconductor portion, and includes a screen oxide layer thinner than the gate dielectric. A body zone and a source zone are formed in the semiconductor portion and directly adjoin the gate structure.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 23, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Cedric Ouvrard
  • Patent number: 10262993
    Abstract: A semiconductor device includes a first transistor structure including a first transistor body region of a first conductivity type located within a semiconductor substrate. At least part of the first transistor body region is located between a first source/drain region of the first transistor structure and a second source/drain region of the first transistor structure. The semiconductor device includes a second transistor structure including a second transistor body region of a second conductivity type located within the semiconductor substrate. At least part of the second transistor body region is located between a first source/drain region of the second transistor structure and a second source/drain region of the second transistor structure. At least part of the second source/drain region of the second transistor structure is located between a doping region comprising the second source/drain region of the first transistor structure and the second transistor body region.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: April 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Marten Müller, Hans-Günter Eckel
  • Patent number: 10263105
    Abstract: In an embodiment, on an n?type SiC layer on an n+-type SiC semiconductor substrate and a p+ layer selectively formed on the n?type SiC layer, a p base layer is formed on which, a p+ contact layer is selectively formed. From a surface, an n counter layer penetrates the p base layer to the n?type SiC layer. A gate electrode layer is disposed via a gate insulating film, on an exposed surface of the p base layer between the p+ contact layer and the n counter layer; and a source electrode contacts the p+ contact layer and the p base layer. In a back surface, a drain electrode is disposed. A portion of the p+ layers are joined at a region of a drain electrode side of the n counter layer, by a joining unit and a p+ layer contacts a drain electrode side of the p+ layer.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: April 16, 2019
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Noriyuki Iwamuro, Shinsuke Harada
  • Patent number: 10263099
    Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 16, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES.INC
    Inventors: Cheng Chi, Fee Li Lie, Chi-Chun Liu, Ruilong Xie
  • Patent number: 10256331
    Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N? epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 9, 2019
    Assignee: Pakal Technologies, Inc.
    Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo, Vladimir Rodov
  • Patent number: 10249612
    Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor body includes a load current component having a load current transistor area and a sensor component including a sensor transistor area. The sensor transistor area has first and third transistor area parts differing from a second transistor area part between the first and third transistor area parts by a sensor transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and third transistor area parts by the sensor transistor area element being absent in the second transistor area part.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Stefan Decker, Robert Illing, Michael Nelhiebel
  • Patent number: 10243041
    Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10229994
    Abstract: A semiconductor device of an embodiment includes an SiC layer having a first and a second plane, an n-type first SiC region in the SiC layer, p-type second SiC regions between the first SiC region and the first plane, n-type third SiC regions between the second SiC regions and the first plane, a gate electrode provided between two p-type second SiC regions, a gate insulating film provided between the gate electrode and the second SiC regions, a metal layer provided between two p-type second SiC regions, and having a work function of 6.5 eV or more, and a first electrode electrically connected to the metal layer, and a second electrode, the SiC layer provided between the first electrode and the second electrode, and a part of the first SiC region is disposed between the gate insulating film and the metal layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 10224266
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 10217863
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Junli Wang
  • Patent number: 10204993
    Abstract: A power semiconductor device includes: a semiconductor body for conducting a load current between first and second load terminals; source and channel regions and a drift volume in the semiconductor body; a semiconductor zone in the semiconductor body and coupling the drift volume to the second load terminal, a first transition established between the semiconductor zone and the drift volume; a control electrode insulated from the semiconductor body and the load terminals and configured to control a path of the load current in the channel region; and a trench extending into the drift volume along an extension direction and including a field electrode. An ohmic resistance of the field electrode is greater than an ohmic resistance of the control electrode. A distance between the field electrode and the first transition is at least 70% of the total extension of the drift volume in the extension direction.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Patent number: RE47390
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a semiconductor region, a first and second electrodes. The semiconductor region is provided on the semiconductor substrate via an insulating film. The semiconductor region includes a protection diode. An overvoltage causes breakdown of the protection diode. A PN junction of the protection diode is exposed at an end face of the semiconductor region. A first and second electrodes are provided distally to the exposed end face of the PN junction. The first and second electrodes are connected to the semiconductor region to provide a current to the protection diode.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 14, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tetsuro Nozu