Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin layer on a bottom source/drain layer, and forming one or more fin templates on the vertical fin layer. The method further includes forming a vertical fin below each of the one or more fin templates. The method further includes reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.

Abstract: A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a stack structure in a cell array region of the device. The vertical channel structure can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure. A vertical dummy structure can vertically penetrate through a staircase structure that is defined by the upper structure and the lower structure in a connection region of the device, and the vertical dummy structure can have a side wall with a planar profile at the level where the upper structure meets the lower structure.

Abstract: A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain (201) having a first conduction type; and a first conduction type region (214) disposed on a front face of the drain; the JFET region further includes: a JFET source (208) having a first conduction type; a first well (202) having a second conduction type; a metal electrode (212) formed on the JFET source (208), which is in contact with the JFET source (208); a JFET metal gate (213) disposed on the first well (202) at both sides of the JFET source (208); and a first clamping region (210) located below the JFET metal gate (213) and within the first well (202).

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.

Abstract: A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type; and a first conduction type region disposed on a front surface of the drain (201); the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).

Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

Abstract: A method includes forming a source region in a semiconductor substrate, in which the source region has a first type dopant. A channel region is formed in the semiconductor substrate and next to the source region. A drain region is formed in the semiconductor substrate, in which the drain region has a second type dopant different from the first type dopant. A heavily doped region is formed between the source region and the channel region, in which the heavily doped region has the first type dopant, and a dopant concentration of the first type dopant in the heavily doped region is higher than a dopant concentration of the first type dopant in the source region. A gate structure is formed over the channel region. A first low-k spacer is formed extending downwardly along a first sidewall of the gate structure to a top surface of the heavily doped region.

Abstract: A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

Abstract: A pixel including a workpiece having a protrusion and a bulk, wherein the protrusion extends from an upper surface of the bulk. The pixel further includes a floating diffusion node in the protrusion. The pixel further includes a photosensitive device in the bulk. The pixel further includes an isolation well surrounding the photosensitive device.

Abstract: Reference marks for forming a staircase structure are disposed along slit areas of a 3D memory structure, and slits of the 3D memory structure are formed on the slit areas. In a staircase area, the reference marks are formed by etching the topmost one of stacked layers, having a pair of a dielectric layer and a sacrificial layer, in a stacked structure.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Abstract: Regions including SiO2 layers, Si3N4 layers, and SiO2 layers, and C layers and SiO2 layers, whose two ends in Y-Y? direction are located on the SiO2 layers and two ends in X-X? direction are coincident with the rectangular SiO2 layers, are formed on an i-layer. The i-layer is etched using the SiO2 layers as masks to form Si pillar bases, and the C layers and the SiO2 layers are removed. Thereafter, the SiO2 layers are formed into a circular shape by isotropic etching using the Si3N4 layers as masks, and Si pillars are formed on the Si pillar bases using the circular SiO2 layers as masks.

Abstract: A semiconductor device according to the present invention includes a semiconductor chip having a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface, a conductive substrate onto which the semiconductor chip is die-bonded, a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate, and a resin package that seals at least the semiconductor chip and the conductive spacer.

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Abstract: A power module includes a first die pad, a first switching element, a second die pad, a second switching element, an integrated circuit element, an encapsulation resin, and a lead frame assembly. The encapsulation resin encapsulates the first switching element, the second switching element, and the integrated circuit element. The lead frame assembly includes an outer lead and an inner lead. The lead frame assembly includes a first lead frame and a second lead frame. The first lead frame includes a first inner lead connected to the first die pad and a first outer lead connected to the first inner lead. The second lead frame includes a second inner lead connected to the second die pad and a second outer lead connected to the second inner lead.

Abstract: A power device includes two gate stripes formed on an upper surface of the device, a source stripe perimeter comprising the total available shared perimeter between the two gate stripes and a corresponding source stripe, and a segmented source formed between the two gate stripes, wherein an edge length of the segmented source covers between 5% to 95% of the source stripe perimeter.

Abstract: A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom source/drain regions are formed adjacent lower portions of each of the fins, and a sacrificial layer is formed in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions. In the method, gate structures are formed on the bottom source/drain regions and sacrificial layer, and portions of the gate structures are removed to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region. The method further includes depositing a germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region, and converting the germanium oxide layer to a plurality of silicide/germanide layers.

Abstract: A system may include a charge pump configured to boost an input voltage of the charge pump to an output voltage greater than the input voltage, a current mode control loop for current mode control of a power amplifier powered by the output voltage of the charge pump, and a controller configured to, in a current-limiting mode of the controller, control an output power of the charge pump to ensure that an input current of the charge pump is maintained below a current limit, control the power amplifier by placing the power amplifier into a high-impedance mode during the current-limiting mode, and control state variables of a loop filter of the current mode control loop during the current-limiting mode.

Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.

Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.

Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.

Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.

Abstract: A dual gate transistor circuit, a pixel circuit, and a gate drive circuit are provided. The dual gate transistor circuit includes a dual gate transistor, a first diode, and a second diode. The dual gate transistor has a first gate and a second gate, and the first gate receives a drive signal. The first diode is connected in series between the first gate and the second gate according to a first-polarity direction. The second diode is connected in series between the first gate and the second gate according to a second-polarity direction. The first-polarity direction is opposite to the second-polarity direction.

Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

Abstract: VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.

Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Abstract: A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a silicon carbide portion. A shielding region between a drift zone and the trench gate structures along a vertical direction orthogonal to the first surface forms an auxiliary pn junction with the drift zone. Channel regions and the trench gate structures are successively arranged along a first horizontal direction. The channel regions are arranged between a source region and a current spread region along a second horizontal direction orthogonal to the first horizontal direction. Portions of mesa sections between neighboring trench gate structures fully deplete at a gate voltage within an absolute maximum rating of the semiconductor device.

Abstract: Nonvolatile memory devices and methods of fabricating the nonvolatile memory devices are provided. The nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.

Abstract: A semiconductor device includes: an n? type layer disposed on a first surface of a substrate; an n+ type region disposed on the n? type layer; a trench disposed on the n? type layer; a p type region disposed adjacent to a side surface of the trench and extending to a part under a lower surface of the trench; an auxiliary n+ type region disposed under the lower surface of the trench and disposed in the p type region; an auxiliary electrode disposed at the lower surface of the trench; a gate electrode separated from the auxiliary electrode and disposed on the lower surface of the trench; a source electrode disposed on the n+ type region; and a drain electrode disposed at a second surface of the substrate.

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.

Abstract: A semiconductor device includes a first transistor and a second transistor in a semiconductor substrate. The first transistor includes a first drain contact electrically connected to a first drain region, the first drain contact including a first drain contact portion and a second drain contact portion. The first drain contact portion includes a drain conductive material in direct contact with the first drain region. The second transistor includes a second source contact electrically connected to a second source region. The second source contact includes a first source contact portion and a second source contact portion. The first source contact portion includes a source conductive material in direct contact with the second source region.

Abstract: Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: Methods of fabrication and semiconductor structures includes vertical transport field effect transistors (VTFETs) including a top source/drain extension formed with a sacrificial doped layer. The sacrificial doped layer provides the doping source to form the extension and protects the top of the fin during fabrication so as to prevent thinning, among other advantages.

Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Abstract: A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed.

Abstract: A method of forming a vertical field effect transistor device is provided. The method includes forming one or more fin stacks on a substrate, wherein the fin stacks include a lower junction plate, a vertical fin on the top surface of the lower junction plate, and an upper junction plate on the top surface of the vertical fin. The method further includes removing a portion of the lower junction plate and upper junction plate to form recessed spaces, and forming an inner spacer in the recessed spaces. The method further includes forming a sacrificial layer on the exposed surfaces of the vertical fin and the substrate. The method further includes forming a protective liner on the sacrificial layer and inner spacers, and removing the portion of the sacrificial layer on the surface of the substrate to leave a hanging portion of the protective liner extending below the inner spacer.

Abstract: A method for producing a pillar-shaped semiconductor device includes, forming a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar on a substrate. A gate insulating layer and gate conductor layer are formed surrounding each of the pillars and impurity regions are formed in each pillar. The gate conductor layer is selectively processed to form gate conductors around the pillars and to interconnect the gate conductors.

Abstract: A method for forming a field-effect semiconductor device includes providing a wafer having a substantially compensated semiconductor layer extending to an upper side and including a semiconductor material which is co-doped with n-type dopants and p-type dopants. A peripheral area laterally surrounding an active area are defined in the wafer. Trenches in the active area are filled with a substantially intrinsic semiconductor material. More p-type dopants than n-type dopants are diffused from the compensated semiconductor layer into the intrinsic semiconductor material to form a plurality of p-type compensation regions in the trenches which are separated from each other by respective n-type drift portions. P-type dopants are introduced at least into a semiconductor zone of the peripheral area, so that the semiconductor zone and a dielectric layer on the upper side form an interface. A horizontal extension of the interface is larger than a vertical extension of the trenches.