Gate Electrode Self-aligned With Groove Patents (Class 257/332)
  • Patent number: 11145758
    Abstract: A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Robert H. Dennard, Bruce B. Doris, Terence B. Hook
  • Patent number: 11127823
    Abstract: A split gate structure is disclosed. The split gate structure includes a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench. An upper surface of the characteristic oxide has a height difference less than 1500 ? between a higher center portion and a lower periphery portion. The split gate structure effectively improves the breakdown performance and the IGSS performance. A power MOS device having the split gate structure and a manufacturing method of the split gate structure are also provided.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 21, 2021
    Assignee: HeJian Technology (Suzhou) Co., Ltd.
    Inventors: Yuan Cheng Zheng, Xin Huan Shi
  • Patent number: 11088272
    Abstract: A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 10, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Takui Sakaguchi, Masatoshi Aketa, Yuki Nakano
  • Patent number: 11056393
    Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
  • Patent number: 10910313
    Abstract: An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rwik Sengupta, Mark Rodder, Joon Goo Hong, Titash Rakshit
  • Patent number: 10868169
    Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: December 15, 2020
    Assignee: Cree, Inc.
    Inventors: Vipindas Pala, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour, Edward Robert Van Brunt
  • Patent number: 10770356
    Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
  • Patent number: 10741639
    Abstract: A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Loubet, Robin Hsin Kuo Chao, Julien Frougier, Ruilong Xie
  • Patent number: 10680069
    Abstract: In accordance with an embodiment, a circuit includes a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, a source coupled to a first power source node configured to be coupled to a first capacitor.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 9, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Haeberlen, Gerald Deboy
  • Patent number: 10535764
    Abstract: Fabricating a semiconductor device includes: forming a first gate trench and a second gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the first gate trench to form a first gate and depositing gate material in the second gate trench to form a second gate; forming a body; forming a source; forming an active region contact trench that extends through the source and the body, and a gate contact trench within the second gate; forming an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; and disposing a first electrode within the active region contact trench and a second electrode within the gate contact trench.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 14, 2020
    Assignee: Alpha and Omega Semiconductor Limited
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Patent number: 10354925
    Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface, first trenches and second trenches extending from the first surface into the semiconductor body, at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches, and at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches. The first trenches extend from the first surface into the semiconductor body deeper than a channel zone of the lateral IGFET and confine the channel zone.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Werner Schwetlick
  • Patent number: 10325908
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a source contact extending to the body region formed in a source contact trench next to the gate trench. The lightly doped source region is extended deeper in the body region than the heavily doped source region. The lightly doped source region is adjacent to the source contact trench. A ballast resistor is formed at the lightly doped source region between the heavily doped source region and the body region and a Schottky diode is formed at a contact between the source contact and the lightly doped source region.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 18, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Sik Lui, Madhur Bobde, Ji Pan
  • Patent number: 10312364
    Abstract: A semiconductor device includes a first dielectric layer on a substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, a 2D material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer, a gate dielectric layer on the 2D material layer, and a gate electrode on the gate dielectric layer.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Wen Hung
  • Patent number: 10217737
    Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is configured as a two terminal device.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: February 26, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Chun-Li Liu, Woochul Jeon, Jason Mcdonald
  • Patent number: 10181400
    Abstract: A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 15, 2019
    Assignee: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Patent number: 10109614
    Abstract: An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Thomas Eugene Grebs, Simon John Molloy
  • Patent number: 10037999
    Abstract: A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Sung-eui Kim, Hoon Jeong
  • Patent number: 9997596
    Abstract: A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 12, 2018
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Yang-Kyu Choi, Jun-Young Park
  • Patent number: 9947763
    Abstract: A method including depositing a gap fill material on top of a conformal dummy gate oxide above and in between a plurality of fins, forming one or more openings between the plurality of fins and the gap fill material by selectively removing a portion of the conformal dummy gate oxide, and forming a gate within the one or more openings, and above the plurality of fins and the gap fill material.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Charles W. Koburger, III
  • Patent number: 9941357
    Abstract: A power MOSFET includes a substrate, a semiconductor layer, a first gate, a second gate, a thermal oxide layer, a first CVD oxide layer, and a gate oxide layer. The semiconductor layer is formed on the substrate and has at least one trench. The first gate is located inside the trench. The second gate is located inside the trench on the first gate, wherein the second gate has a first portion and a second portion, and the second portion is located between the semiconductor layer and the first portion. The thermal oxide layer is located between the first gate and the semiconductor layer. The first CVD oxide layer is located between the first gate and the second gate. The gate oxide layer is generally located between the second gate and the semiconductor layer.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 10, 2018
    Assignee: Excelliance MOS Corporation
    Inventor: Chu-Kuang Liu
  • Patent number: 9768169
    Abstract: Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gun You, Sug-Hyun Sung
  • Patent number: 9685503
    Abstract: A semiconductor device includes a first conductivity type semiconductor layer that includes a wide bandgap semiconductor and a surface. A trench, including a side wall and a bottom wall, is formed in the semiconductor layer surface, and a Schottky electrode is connected to the surface. Opposite edge portions of the bottom wall of the trench each include a radius of curvature, R, satisfying the expression 0.01 L<R<10 L, where L represents the straight-line distance in a width direction of the trench between the opposite edge portions.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: June 20, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Masatoshi Aketa
  • Patent number: 9614073
    Abstract: A semiconductor device that has a source region, a channel region, and a drain region disposed in order from a surface of the semiconductor device in a thickness direction of a semiconductor substrate. The semiconductor device includes a gate insulating film having an extended portion that covers the surface of the semiconductor substrate outside of a gate trench and a top surface of a polysilicon gate. A connection gate trench branches from the gate trench, and joins a contact gate trench which is wider than the gate trench and the connection gate trench. The polysilicon gate is embedded in the connection gate trench and the contact gate, and extends from the gate trench to the contact gate trench through the connection gate trench. The gate contact groove is formed in the polysilicon gate within the contact gate trench.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: April 4, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Kenichi Yoshimochi
  • Patent number: 9559198
    Abstract: A semiconductor device comprises a first contact layer, a first drift layer adjacent the first contact layer, a buried body layer adjacent the first drift layer and a second contact layer. A first vertical trench and a second vertical trench are provided, the first and second vertical trenches being spaced with respect to each other and extending from the second contact layer to substantially beyond the buried body layer. A second drift layer is also provided and sandwiched between the buried body layer and the second contact layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: January 31, 2017
    Assignee: NXP USA, Inc.
    Inventors: Evgueniy Stefanov, Edouard de Fresart, Philippe Dupuy
  • Patent number: 9508590
    Abstract: In some embodiments, a method of manufacturing a device includes providing a first device with an isolation area, an active area next to the isolation area, a metal gate above the isolation area and the active area, and a dielectric layer above the metal gate. The method also includes forming a first opening within a conductive layer of the metal gate, and a second opening within the dielectric layer. The first opening and the second opening are connected, and are of a first shape. The method further includes expanding the first opening to form a third opening of a second shape within the conductive layer of the metal gate and beneath the dielectric layer, forming a first contact part by filling the third opening, and forming a second contact part by filling the second opening, the first contact part being connected to the second contact part.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
  • Patent number: 9466723
    Abstract: A method includes forming a placeholder source/drain contact structure above a semiconductor material. A conformal deposition process is performed to form a liner layer above the placeholder contact structure. A dielectric layer is formed above the liner layer. A first planarization process is performed to remove material of the dielectric layer and expose a first top surface of the liner layer above the placeholder contact structure. A first cap layer is formed above the dielectric layer. A second planarization process is performed to remove material of the first cap layer and the liner layer to expose a second top surface of the placeholder contact structure. The placeholder contact structure is removed to define a source/drain contact recess in the dielectric layer. The sidewalls of the dielectric layer in the source/drain contact recess are covered by the liner layer. A conductive material is formed in the contact recess.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Haigou Huang, Qiang Fang, Jin Ping Liu, Huang Liu
  • Patent number: 9450088
    Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: September 20, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yeeheng Lee, Hong Chang, Jongoh Kim, Sik Lui, Hamza Yilmaz, Madhur Bobde, Daniel Calafut, John Chen
  • Patent number: 9397193
    Abstract: A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 19, 2016
    Assignee: SK Hynix Inc.
    Inventor: Joon Seop Sim
  • Patent number: 9349657
    Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: May 24, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung Wang, Hsien-Chin Lin, Yuan-Ching Peng, Chia-Pin Lin, Fan-Yi Hsu, Ya-Jou Hsieh
  • Patent number: 9281393
    Abstract: A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 8, 2016
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Rongyao Ma, Tiesheng Li, Donald Disney, Lei Zhang
  • Patent number: 9252210
    Abstract: A semiconductor device capable of decreasing a reverse leakage current and a forward voltage is provided. In the semiconductor device, an anode electrode undergoes Schottky junction by being connected to a surface of an SiC epitaxial layer that has the surface, a back surface, and trapezoidal trenches formed on the side of the surface each having side walls and a bottom wall. Furthermore, an edge portion of the bottom wall of each of the trapezoidal trenches is formed to be in the shape bent towards the outside of the trapezoidal trench in the manner that a radius of curvature R satisfies 0.01 L<R<10 L (1) (in the expression (1), L represents the straight-line distance between the edge portions opposite to each other in a width direction of the trench).
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 2, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Masatoshi Aketa
  • Patent number: 9246000
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: January 26, 2016
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 9171917
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: October 27, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Sik Lui, Anup Bhalla
  • Patent number: 9105579
    Abstract: A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: August 11, 2015
    Assignee: Avogy, Inc.
    Inventors: Patrick James Lazlo Hyland, Brian Joel Alvarez, Donald R. Disney
  • Patent number: 9076805
    Abstract: A semiconductor device a field of transistor cells integrated in a semiconductor body. A number of the transistor cells forming a power transistor and at least one of the transistor cells forming a sense transistor. A first source electrode is arranged on the semiconductor body electrically connected to the transistor cell(s) of the sense transistor but electrically isolated from the transistor cells of the power transistor. A second source electrode is arranged on the semiconductor body and covers the transistor cells of both the power transistor and the sense transistor, and at least partially covering the first source electrode in such a manner that the second source electrode is electrically connected only to the transistor cells of the power transistor but electrically isolated from the transistor cells of the sense transistor.
    Type: Grant
    Filed: July 14, 2012
    Date of Patent: July 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Steffen Thiele, Andreas Meiser, Markus Zundel
  • Patent number: 9048302
    Abstract: A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess; a gate electrode formed on the insulating layer at the recess; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess in between and electrically connected to the semiconductor operating layer. The recess includes a side wall inclined relative to the semiconductor operating layer.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: June 2, 2015
    Assignee: THE FURUKAWA ELECTRIC CO., LTD
    Inventors: Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama, Takehiko Nomura, Seikoh Yoshida, Masayuki Iwami, Jiang Li
  • Patent number: 9041008
    Abstract: A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nakabayashi, Takashi Shinohe, Atsuko Yamashita
  • Patent number: 9029930
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 9029941
    Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Markus Zundel, Christoph Kadow
  • Patent number: 9000514
    Abstract: Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 7, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yeeheng Lee, Sung-Shan Tai, Hong Chang, John Chen
  • Patent number: 8994123
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Gold Standard Simulations Ltd.
    Inventors: Asen Asenov, Gareth Roy
  • Patent number: 8994100
    Abstract: The present invention provides a semiconductor device designed to prevent an electric field from being concentrated in the vicinity of a groove portion. The semiconductor includes a semiconductor layer, a source region, a drain region, a source offset region, a drain offset region, a groove portion, a gate insulating film, a gate electrode, and an embedded region. The groove portion is provided in at least a position between the source offset region and the drain offset region in the semiconductor layer in a plan view, in a direction from the source offset region to the drain offset region in a plan view. The gate insulating film covers a side and a bottom of the groove portion. The gate electrode is provided only within the groove portion in a plan view, and contacts the gate insulating film.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 31, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Matsumoto
  • Patent number: 8994101
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Jongoh Kim, John Chen
  • Patent number: 8987811
    Abstract: According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hak-soo Yu, Chulwoo Park, Hyun-Woo Chung, Sua Kim, Hyunho Choi, Hongsun Hwang
  • Patent number: 8987902
    Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 24, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Syota Miki
  • Publication number: 20150076593
    Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 8981471
    Abstract: In a MOSFET, the lead parts of gate lead wiring that lead out a gate electrode on the periphery of a substrate constitute a non-operative region. If the gate lead wiring is disposed along the four edges of a chip, the area of the non-operative region increases. In the present invention, gate lead wiring and a conductor, which is connected to the gate lead wiring and a protection diode, are disposed in a non-curved, linear configuration along one edge of a chip. In addition, a first gate electrode layer that extends superimposed on the gate lead wiring and the conductor, and connects the gate lead wiring and the conductor to the protection diode, has no more than one curved part. Furthermore, the protection diode is disposed adjacent to the conductor or the gate lead wiring, and a portion of the protection diode is disposed near a gate pad.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Haruyoshi Yagi, Manabu Yajima
  • Patent number: 8969933
    Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Zhengwen Li, Dechao Guo, Randolph F. Knarr, Chengwen Pei, Gan Wang, Yanfeng Wang, Keith Kwong Hon Wong, Jian Yu, Jun Yuan
  • Patent number: 8969956
    Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Balaji Padmanabhan
  • Patent number: RE45449
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth