Gate Electrode Self-aligned With Groove Patents (Class 257/332)
  • Patent number: 8455319
    Abstract: A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: June 4, 2013
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung Han Lee, Chung-Yuan Lee, Hsien-Wen Liu
  • Patent number: 8455944
    Abstract: A semiconductor device includes, on a semiconductor substrate, an active region surrounded by an STI region, a gate trench formed in one direction transverse to the active region, a gate insulating film formed on a side surface of the gate trench, an insulating film formed on a bottom of the gate trench and thicker than the gate insulating film, and a gate electrode having at least a part of the gate electrode formed in the gate trench. Portions of the semiconductor substrate present in the active region and located on both sides of the gate trench in an extension direction of the gate trench function as a source region and a drain region, respectively. A portion of the semiconductor substrate located between the side surface of the active region (the side of the STI region) and the side surface of the gate trench functions as a channel region.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: June 4, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroshi Kujirai
  • Patent number: 8455320
    Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: June 4, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 8450797
    Abstract: To realize forming a trench MOSFET in which a depth of a P-body is changed on the same surface as a CMOS by employing steps with good controllability and without greatly increasing the number of manufacturing steps, provided is a trench MOSFET including an extended body region (10), which is a part of a P-body region (4) and is provided in a vicinity of a deep trench (5) with a distance, the extended body region (10) being diffused deeper than the P-body region (4).
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 28, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Naoto Saitoh
  • Patent number: 8445956
    Abstract: A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: May 21, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Walter Rieger, Markus Zundel
  • Publication number: 20130119464
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Application
    Filed: December 13, 2012
    Publication date: May 16, 2013
    Applicant: SK HYNIX INC.
    Inventor: SK HYNIX INC.
  • Patent number: 8441069
    Abstract: A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: May 14, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8441067
    Abstract: The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: May 14, 2013
    Assignee: Sinopower Semiconductor Inc.
    Inventor: Wei-Chieh Lin
  • Patent number: 8435851
    Abstract: A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Publication number: 20130105891
    Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.
    Type: Application
    Filed: June 26, 2012
    Publication date: May 2, 2013
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8431989
    Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: April 30, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Sik K. Lui
  • Patent number: 8431982
    Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoungsoo Kim, Yoonkyung Choi, Eun Young Lee, Sungil Jo
  • Patent number: 8426910
    Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8426276
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8421149
    Abstract: A fabrication method of trench power semiconductor structure with high switching speed is provided. An epitaxial layer with a first conductivity type is formed on a substrate. Then, gate structures are formed in the epitaxial layer. A shallow doped region with the first conductivity type is formed in the surface layer of the epitaxial layer. After that, a shielding structure is formed on the shallow doped region. Then, wells with a second conductivity type are formed in the epitaxial layer by using the shielding structure as an implantation mask. Finally, a source doped region with the first conductivity type is formed on the surface of the well. The doping concentration of the shallow doped layer is smaller than that of the source doped region and the well. The doping concentration of the shallow doped layer is larger than that of the epitaxial layer.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 16, 2013
    Assignee: Great Power Semiconductor Corp.
    Inventors: Yuan-Shun Chang, Kao-Way Tu
  • Patent number: 8421106
    Abstract: A light emitting device includes a light emitting structure formed from an active layer located between two semiconductor layers. An insulator extends through the active layer and at least partially through the semiconductor layers, and the light emitting structure is located between a first electrode and a second electrode layer. The first electrode and insulator overlap one another and may have the same or different widths.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: April 16, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sung Min Hwang
  • Patent number: 8415740
    Abstract: Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: April 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Atsushi Kaneko
  • Patent number: 8415739
    Abstract: A semiconductor component that includes an edge termination structure and a method of manufacturing the semiconductor component. A semiconductor material has a semiconductor device region and an edge termination region. One or more device trenches may be formed in the semiconductor device region and one or more termination trenches is formed in the edge termination region. A source electrode is formed in a portion of a termination trench adjacent its floor and a floating electrode termination structure is formed in the portion of the termination trench adjacent its mouth. A second termination trench may be formed in the edge termination region and a non-floating electrode may be formed in the second termination trench. Alternatively, the second termination trench may be omitted and a trench-less non-floating electrode may be formed in the edge termination region.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: April 9, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Zia Hossain
  • Patent number: 8410489
    Abstract: A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a silicon carbide semiconductor substrate 10 of a first conductivity type, a semiconductor layer 20 of the first conductivity type, a body region 30 of a second conductivity type, a source region 40 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, a source electrode 45, a gate insulating film 60, a gate electrode 65 and a drain electrode 70. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: April 2, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuhiro Adachi, Osamu Kusumoto, Masao Uchida, Koichi Hashimoto, Shun Kazama
  • Patent number: 8410616
    Abstract: A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4) having the same shape as the aperture (3a), with the sidewall (4a) of the step portion (4) exposed through the aperture (3a). The aperture (3a) is spin-coated with a shrink agent, reacted at a first temperature, and developed to shrink the aperture (3a). To control the shrinkage with high accuracy, in the first round of reaction, the aperture is shrunk by, for example, about half of the desired shrinkage. The aperture (3a) is further spin-coated with a shrink agent, reacted at a second temperature, and developed to shrink the aperture (3a). In this embodiment, the second-round shrink process will result in the desired aperture length. The second temperature is adjusted based on the shrinkage in the first round.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Ken Sawada
  • Patent number: 8410554
    Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8410546
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase
  • Patent number: 8405145
    Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: March 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
  • Patent number: 8399921
    Abstract: The manufacturing method includes the steps of: providing a semiconductor base of a first conduction type; forming a first epitaxial layer with a plurality of epitaxial pillars of therein on a first surface of the semiconductor base, wherein the epitaxial pillars have a conduction type opposite to the first epitaxial layer; forming a plurality of first shallow trenches and a plurality of second shallow trenches alternately on the epitaxial pillars and the first epitaxial layer, wherein the first shallow trench has a width greater than the width of the second shallow trench and the first shallow trench is extended downward to the epitaxial pillar; and forming a plurality of gate regions in the first shallow trenches respectively; forming a plurality of source regions on both sides of the first shallow trench; and forming a source metal conducting wire to connect the source regions.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: March 19, 2013
    Assignee: Niko Semiconductor Co., Ltd.
    Inventor: Kao-Way Tu
  • Patent number: 8395186
    Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8395198
    Abstract: A semiconductor device includes: a cell gate trench with a bottom face and first/second side faces; a field-shield gate trench narrower than the cell gate trench; a first upper diffusion layer between the cell gate trench and the field-shield gate trench; a second upper diffusion layer on the opposite side of the cell gate trench from the first upper diffusion layer; a third upper diffusion layer on the opposite side of the field-shield gate trench from the first upper diffusion layer; a lower diffusion layer on the bottom face of the cell gate trench; first and second storage elements electrically connected to the first and second upper diffusion layers, respectively; a bit line electrically connected to the lower diffusion layer; a word line covering first and second side faces via a gate insulating film; and a field-shield gate electrode in the field-shield gate trench via a gate insulating film.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: March 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Uchiyama
  • Patent number: 8390061
    Abstract: A semiconductor device has a well region formed of a first conductivity type semiconductor at a predetermined depth from a surface of a substrate, trenches formed in the well region, and a gate insulating film formed on surfaces of concave and convex portions of the trenches. A first gate electrode is embedded inside the trenches, and a second gate electrode is formed on the substrate in contact with the first gate electrode in regions of the concave and convex portions excluding vicinities of both ends of the trenches. Source and drain regions of a second conductivity type are formed from a part of a surface of the semiconductor so as to extend deeper in a side surface of the concave portion of each trench than in the surface of the convex portion of each trench and shallower than the depth of the well region.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 5, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Tomomitsu Risaki
  • Publication number: 20130049108
    Abstract: A MOSFET includes a semiconductor substrate having a top surface, a body region of a first conductivity type in the semiconductor substrate, and a double diffused drain (DDD) region having a top surface lower than a bottom surface of the body region. The DDD region is of a second conductivity type opposite the first conductivity type. The MOSFET further includes a gate oxide, and a gate electrode separated from the body region by the gate oxide. A portion of the gate oxide and a portion of the gate electrode are below the top surface of the body region.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Chih Chen, Kun-Hsuan Tien, Ruey-Hsin Liu
  • Patent number: 8384152
    Abstract: A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench on the surface layer portion of the body layer, a gate insulating film formed on the bottom surface and the side surface of the gate trench, and a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the upper surface of the first conductivity type layer are flush with each other.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: February 26, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshikazu Nakagawa, Naoki Izumi, Masaki Nagata
  • Patent number: 8384150
    Abstract: A semiconductor device of the present invention includes vertical double diffused MOS transistor. A gate electrode of the vertical double diffused MOS transistor is disposed within a trench formed on a semiconductor substrate and projects from a surface of the semiconductor substrate. On a side surface of the gate electrode, a side wall is formed. On the surface of the semiconductor substrate and a surface of the gate electrode, a metal silicide film is formed.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: February 26, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Michihiko Mifuji, Ryuta Maruyama, Masaki Hino
  • Patent number: 8378416
    Abstract: MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: February 19, 2013
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 8372716
    Abstract: In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: February 12, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Peter J. Zdebel
  • Patent number: 8368128
    Abstract: An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on insulator type. The substrate is covered by a layer of dielectric material and a gate material. The counter-electrode contact is located in the pattern of the gate electrode. The gate material is etched to define the gate electrode, the source contact and drain contacts and the counter-electrode contact. A part of the support substrate is released through the pattern of the counter-electrode contact area. An electrically conductive material is deposited on the free part of the support substrate to form the counter-electrode contact.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 5, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Claire Fenouillet-Béranger, Olivier Thomas, Philippe Coronel, Stéphane Denorme
  • Patent number: 8362548
    Abstract: In one embodiment, a contact structure for a semiconductor device having a trench shield electrode includes a gate electrode contact portion and a shield electrode contact portion within a trench structure. Contact is made to the gate electrode and the shield electrode within or inside of the trench structure. A thick passivating layer surrounds the shield electrode in the contact portion.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Peter A. Burke, Gordon M. Grivna, Prasad Venkatraman
  • Patent number: 8357972
    Abstract: A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: January 22, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Yi-Chun Shih
  • Patent number: 8357973
    Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: January 22, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K Lui, François Hébert, Anup Bhalla
  • Patent number: 8354712
    Abstract: A body contact layer 18 is formed on the side of a recessed structure 17 as well as in the bottom of the recessed structure 17, so that a contact area between the body contact layer 18 and a well layer 12 is increased and the amount of dopant implanted to the body contact layer 18 is suppressed.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: January 15, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuhiro Hamada, Katsuyoshi Jokyu
  • Patent number: 8350321
    Abstract: The present invention discloses a transistor having the saddle fin structure. The saddle fin transistor of the present invention has a structure in which a landing plug contact region, particularly, a landing plug contact region on an isolation layer is elevated such that the landing plug contact SAC (Self Aligned Contact) fail can be prevented.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: January 8, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyu tae Kim
  • Patent number: 8349687
    Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
  • Patent number: 8329539
    Abstract: In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Ha, Kong-Soo Lee, Sung-Sam Lee, Sang-Hyun Lee, Min-Young Shim
  • Patent number: 8324056
    Abstract: A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8310002
    Abstract: A semiconductor device includes a semiconductor substrate, a first diffusion region, a gate insulating film, a gate electrode, a second diffusion region and a contact plug. The semiconductor substrate includes a base and at least a pillar. The first diffusion region is disposed in the base. The gate insulating film covers a side surface of the pillar. The gate electrode is separated from the pillar by the gate insulating film. The second diffusion region is disposed in an upper portion of the pillar. The contact plug is connected to the second diffusion region. The contact plug is connected to the entirety of the top surface of the pillar.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 8310004
    Abstract: A trench gate transistor whose gate changes depth intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The first offset region and the second offset region are shallower where they contact the device isolation film than is the device isolation film in those areas. The first and second offset regions nevertheless extend below the bottom of the trench.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Kawaguchi
  • Patent number: 8304833
    Abstract: The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: November 6, 2012
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant
  • Patent number: 8299494
    Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: October 30, 2012
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 8299560
    Abstract: An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: October 30, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna, Peter J. Zdebel
  • Patent number: 8294209
    Abstract: A semiconductor memory device includes a plurality of active pillars protruding from a semiconductor substrate, a first gate electrode disposed on at least one sidewall of the active pillar, a first gate insulating layer being disposed between the active pillar and the first gate electrode, a second gate electrode disposed on at least one sidewall of the active pillar over the first gate electrode, a second gate insulating layer being disposed between the active pillar and the second gate electrode, first and second body regions in the active pillar adjacent to respective first and second respective electrodes, and first through third source/drain regions in the active pillar arranged alternately with the first and second body regions.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanghun Jeon, Jongwook Lee, Jong-Hyuk Kang, Heungkyu Park
  • Patent number: 8294238
    Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Takayuki Toba, Yoshiko Kato, Kenji Gomikawa, Haruhiko Koyama
  • Patent number: 8278705
    Abstract: A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: October 2, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Nathan Kraft
  • Patent number: 8278708
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: October 2, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi