In Integrated Circuit Structure Patents (Class 257/337)
  • Patent number: 11024622
    Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien
  • Patent number: 11018257
    Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 25, 2021
    Inventors: Yu-San Chien, Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 10985253
    Abstract: The present invention relates, for example, to a semiconductor structure containing multiple parallel channels in which several parallel conductive channels are formed within the semiconductor structure. Electric contact or electrostatic control over all these channels is done by three-dimensional electrode structures. The multiple channel structure with three-dimensional electrodes can be applied to semiconductors devices such as field effect transistors, diodes, and other similar electronic or quantum-effect devices. This structure is practical for materials where multiple parallel conduction channels can be formed, such as in III-V semiconductors. Ill-Nitride semiconductors with such structures are described which can lead to increased power density, reduced on-resistance and improved device performance, in addition to reducing dynamic on-resistance, and improving the stability of their threshold voltage and reliability.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 20, 2021
    Assignee: ECOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE (EPFL)
    Inventors: Elison de Nazareth Matioli, Jun Ma
  • Patent number: 10978559
    Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sheldon Douglas Haynie, Alexei Sadovnikov
  • Patent number: 10957653
    Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
  • Patent number: 10886237
    Abstract: The semiconductor device including a substrate comprising a chip region and a guard-ring region which surrounds a side surface of the chip region, an isolation layer configured to define an active region within the guard-ring region, a first doping layer in the active region and doped with first impurities having a first doping concentration, a second doping layer on the first doping layer and in the active region, the second doping layer doped with second impurities having a same conductivity type as the first impurities of the first doping layer, the second impurities having a second doping concentration, the second doping concentration being greater than the first doping concentration, a first gate electrode on the second doping layer, and a first wire layer on the first gate electrode may be provided.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung Soo Kim
  • Patent number: 10885254
    Abstract: A method of manufacturing an integrated circuit includes manufacturing a first set of conductive features by a first mask, positioning a set of gates in a second direction, manufacturing a second set of conductive features by a second mask, and electrically coupling a first portion of the set of gates to a second portion of the set of gates. The first and second set of conductive features is in a first direction and a first layer. The set of gates is in a second layer. The first portion of the set of gates corresponds to a gate terminal of a first n-type transistor, the second portion of the set of gates corresponds to a gate terminal of a first p-type transistor, the first n-type transistor being part of a first transmission gate, and the first p-type transistor being part of a second transmission gate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien
  • Patent number: 10879387
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
  • Patent number: 10861946
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
  • Patent number: 10847544
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Patent number: 10840246
    Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10837986
    Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
  • Patent number: 10833018
    Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 10825900
    Abstract: A semiconductor switch device and a method of making the same. The device includes a semiconductor substrate having a major surface. The device also includes a first semiconductor region located in the substrate beneath the major surface. The device includes an elongate gate located on the major surface. The device also includes a source region and a drain region located in the first semiconductor region adjacent respective first and second elongate edges of the gate. The device also includes electrical contacts for the source and drain regions. The contacts include at least two contacts located on either the source region or the drain region, which are spaced apart along a direction substantially parallel the elongate edges of the gate. The device further includes an isolation region located between the at least two contacts. The isolation region extends through the source/drain region from the major surface to the first semiconductor region.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Mahmoud Shehab Mohammad Al-Sa'di, Petrus Hubertus Cornelis Magnee, Ihor Brunets, Jan Willem Slotboom, Tony Vanhoucke
  • Patent number: 10644000
    Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
  • Patent number: 10643957
    Abstract: Embodiments of packaged semiconductor devices and methods of making thereof are provided herein, which include a semiconductor die having a plurality of pads on an active side; a dummy die having a plurality of openings that extend from a first major surface to a second major surface opposite the first major surface, wherein the plurality of openings are aligned with the plurality of pads; and a silicone-based glue attaching the dummy die to the active side of the semiconductor die, wherein a plurality of bondable surfaces of the semiconductor die are exposed through the plurality of openings of the dummy die.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 5, 2020
    Assignee: NXP B.V.
    Inventors: Antonius Hendrikus Jozef Kamphuis, Amar Ashok Mavinkurve, Jetse De Witte, Andrei-Alexandru Damian
  • Patent number: 10600908
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a semiconductor substrate, and includes: a gate, a source, a drain, and at least one plug plate electrode. The plug plate electrode is in direct contact with the gate, and is electrically connected to the gate. The plug plate electrode extends downwards from the bottom of the gate to the semiconductor substrate, through a current vertical height of a conductive current when the high voltage is ON. The plug plate electrode is between the source and the drain in a lateral direction. The plug plate electrode includes a dielectric layer and a conductive layer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: March 24, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10593664
    Abstract: A semiconductor substrate has a main surface, a rear surface, an active device region, and an inactive region adjacent the active device region. Doped source, body, drift and drain regions, and electrically conductive gate and field electrodes are disposed in the active device region. The gate electrode is configured to control an electrical connection between the source and drain regions. The field electrode is adjacent to the drift region. An intermetal dielectric layer is disposed on the main surface, an electrically conductive source pad is formed in a first metallization layer that is formed on the intermetal dielectric layer. A resistor is connected between the source pad and the field electrode. The resistor includes an electrically conductive resistance section that is disposed in a resistor trench. The resistor trench is formed within the inactive region and is electrically isolated from every active device within the active device region.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 17, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Hugo Burke, Kapil Kelkar, Ling Ma
  • Patent number: 10586730
    Abstract: An electronic device includes an isolated region surrounded by an isolation ring over a semiconductor substrate. A well of a first conductivity type is located within the isolated region. A source region and a drain region of a second conductivity type are located over the well. A local-oxidation-of-silicon (LOCOS) layer is located on the well between the source and the drain, between the source and the isolation ring, and between the drain and the isolation ring. A gate electrode located between the source and the drain on said LOCOS layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ming-Yeh Chuang
  • Patent number: 10522617
    Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: December 31, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Mark M. Doherty
  • Patent number: 10468523
    Abstract: A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p+ source region and a p+ drain region. A p? drift region is located below the isolation trench and connected to the p+ drain region. A gate electrode fills the recessed portion. An n-type impurity region is located below the p? drift region and directly below the recessed portion.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroki Fujii, Takahiro Mori
  • Patent number: 10461182
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
  • Patent number: 10439059
    Abstract: A transistor includes a first gate-controlled region having a first threshold voltage and a second gate-controlled region in parallel with the first gate-controlled region. The second gate-controlled region has a second threshold voltage different form the first threshold voltage.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 8, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Tomas Apostol Palacios, Sameer Jayanta-Joglekar, Ujwal Radhakrishna
  • Patent number: 10411004
    Abstract: Semiconductor device and methods for making the devices includes a buried layer of a first conductivity in a substrate in which a distance between two adjacent ends can be selected to achieve a desired breakdown voltage. A deep well having a first doping concentration of a second conductivity type is implanted in an epitaxial layer above the two adjacent ends of the buried layer. A patterned doped region is formed in the deep well and extending into the epitaxial layer above and separated a distance from the two adjacent ends of the buried lay. The patterned doped region has a second doping concentration of the second conductivity type that is greater than the first doping concentration.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 10, 2019
    Assignee: NXP USA, Inc.
    Inventors: Evgueniy Nikolov Stefanov, Patrice Besse, Jean Philippe Laine
  • Patent number: 10411067
    Abstract: Techniques are disclosed for forming a monolithic integrated circuit semiconductor structure that includes a radio frequency (RF) frontend portion and may further include a CMOS portion. The RF frontend portion includes componentry implemented with column III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and compounds thereof, and the CMOS portion includes CMOS logic componentry implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). Either of the CMOS or RF frontend portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of III-N transistors and/or RF filters, along with column IV CMOS devices on a single substrate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10411115
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 10, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Dae-Sub Jung, Lei Fang, Guang Li Yang, De Yan Chen
  • Patent number: 10396065
    Abstract: A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 10290705
    Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: May 14, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Feng Huang, Guangtao Han, Guipeng Sun, Feng Lin, Longjie Zhao, Huatang Lin, Bing Zhao
  • Patent number: 10283622
    Abstract: A high voltage (HV) transistor is integrated on a silicon-on-insulator (SOI) substrate. The HV transistor is disposed in a HV device region disposed on a bulk substrate of the SOI substrate. The HV device region includes a top field oxide which includes at least a part of a buried oxide (BOX) of the SOI substrate. A HV gate is disposed in HV region overlapping the HV top field oxide and includes first and second HV gate sidewalls. A drain is disposed on the bulk substrate and displaced from the first HV gate sidewall by the HV top field oxide. A source is disposed on the bulk substrate adjacent to the side of the second HV gate sidewall.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Guowei Zhang
  • Patent number: 10269707
    Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Jeffrey B. Johnson, Edward J. Nowak
  • Patent number: 10263005
    Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Keisuke Tsukamoto, Tatsuyoshi Mihara
  • Patent number: 10263072
    Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 16, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Mark M. Doherty
  • Patent number: 10256340
    Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate having a first conductivity type, and a first doping region having a second conductivity type therein. An epitaxial layer is on the semiconductor substrate. A body region having the first conductivity type is in the epitaxial layer on the first doping region. A second doping region and a third doping region that have the second conductivity type are respectively in the epitaxial layer on both opposite sides of the body region, so as to adjoin the body region. Source and drain regions are respectively in the body region and the second doping region. A field insulating layer is in the second doping region between the source and drain regions. A gate structure is on the epitaxial layer to cover a portion of the field insulating layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yu-Lung Chin, Shin-Cheng Lin, Wen-Hsin Lin, Cheng-Tsung Wu
  • Patent number: 10199494
    Abstract: The present disclosure provides a laterally diffused metal-oxide-semiconductor (LDMOS) device. The LDMOS device includes a plurality of fin structures formed on a substrate including a first device region, a second device region, and an isolation region sandwiched between the two regions. An opening is formed in the fin structures in the isolation region. The LDMOS device further includes an isolation layer formed in the opening and covering the sidewall of the opening formed by a portion of each fin structure in the first device region. The isolation layer exposes top surfaces of the plurality of fin structures. Moreover, the LDMOS device also includes a gate structure formed across each fin structure in the first device region. The gate structure covers a portion of the sidewall and the top surfaces of the fin structure formed in the first device region and also covers the top surface of the isolation layer.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 5, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10192885
    Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 29, 2019
    Assignee: NXP USA, Inc.
    Inventors: Chi-Min Yuan, David R. Tipple
  • Patent number: 10163684
    Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 25, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Bruce Doris, Hong He, Qing Liu
  • Patent number: 10157794
    Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Puneet H. Suvarna, Steven Bentley, Mark V. Raymond, Peter M. Zeitzoff
  • Patent number: 10103248
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
  • Patent number: 10084039
    Abstract: A semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second conductivity type doped region and bounded below by another second conductivity semiconductor region. Trench isolation regions extend through the second conductivity doped region and the first conductivity floating buried doped region into the semiconductor region. Functional devices are disposed within the second conductivity type doped region. The first conductivity type floating buried doped region is configured as a self-biased region that laterally extends between adjacent trench isolation regions.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: September 25, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Johan Camiel Julia Janssens
  • Patent number: 10079178
    Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming a bottom layer, a middle layer and an upper layer over a substrate, developing the upper layer to form an upper pattern with a first opening exposing the middle layer and a sidewall of the upper pattern. The upper pattern has a top surface. The method further includes conformally forming a protective layer over the upper pattern and the exposed middle layer, anisotropically etching the protective layer to leave a portion of the protective layer over the sidewall of the upper pattern and expose the middle layer, etching the middle layer not covered by the upper pattern and the portion of the protective layer to form a middle pattern with a second opening exposing the bottom layer, and etching the bottom layer though the second opening of the middle pattern.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: September 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Po-Ju Chen, Yi-Wei Chiu, Fang-Yi Wu, Chih-Hao Chen, Wen-Yen Chen
  • Patent number: 10068900
    Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion, wherein a height (hS) of the semiconductor portion of the HV dummy pattern is smaller than a height (hHV-g) of a HV gate electrode of one of the HV gate structures.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin Yang, Chao-Sheng Cheng
  • Patent number: 10056374
    Abstract: A switching device may be provided with: a semiconductor substrate; a trench provided in an upper surface of the semiconductor substrate; a gate insulating layer covering an inner surface of the trench; and a gate electrode located in the trench. The semiconductor substrate includes: a first semiconductor region being in contact with the gate insulating layer; a body region being in contact with the gate insulating layer under the first semiconductor region; a second semiconductor region being in contact with the gate insulating layer under the body region; a bottom region being in contact with the gate insulating layer at a bottom surface of the trench; and a connection region being in contact with the gate insulating layer at a lateral surface of the trench and connecting the body region and the bottom region. The connection region is thicker than the bottom region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 21, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Yasushi Urakami, Sachiko Aoi
  • Patent number: 9991192
    Abstract: Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: June 5, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Patent number: 9985017
    Abstract: Semiconductor device with a semiconductor body that includes a clamping structure including a pn junction diode and a Schottky junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the pn junction diode is greater than 100 V and a breakdown voltage of the Schottky junction diode is greater than 10 V.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Stephan Voss, Roman Baburske, Thomas Basler, Thomas Kimmer, Hans-Joachim Schulze
  • Patent number: 9979180
    Abstract: According to an example, a device is suggested, said device comprising a switching element, an integrated sensor providing a signal and an electronic fuse that is arranged to determine a fuse condition based on the signal and based on at least one fuse characteristic and to trigger a fuse event in case the fuse condition is met.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Markus Bader, Goran Keser
  • Patent number: 9917163
    Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9905556
    Abstract: To suppress the reverse breakdown voltage decrease while separating a main body region from a current detecting region. To provide a semiconductor device comprising a semiconductor substrate, a main body region having one or more operation cells formed inside the semiconductor substrate, a current detecting region having one or more current detecting cells formed inside the semiconductor substrate, an intermediate region formed between the main body region and the current detecting region and inside the semiconductor substrate, an upper surface side electrode formed above at least part of the main body region, a current detecting electrode that is formed above at least part of the current detecting region and is separate from the upper surface side electrode, and an additional electrode that is formed above at least part of the intermediate region and is connected to either the upper surface side electrode or the current detecting electrode.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 9899509
    Abstract: An embodiment of a semiconductor device comprises a trench transistor cell array in a semiconductor body. The semiconductor device further comprises an edge termination region of the trench transistor cell array. At least two first auxiliary trench structures extend into the semiconductor body from a first side and are consecutively arranged along a lateral direction. The edge termination region is arranged, along the lateral direction, between the trench transistor cell array and the at least two first auxiliary trench structures. First auxiliary electrodes in the at least two first auxiliary trench structures are electrically connected together and electrically decoupled from electrodes in trenches of the trench transistor cell array.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: February 20, 2018
    Assignee: Infineon Technologies AG
    Inventor: Markus Zundel
  • Patent number: 9871510
    Abstract: A cascode switch circuit includes a normally-on device cascode coupled to a normally-of device between first and second terminals of the cascode switch circuit. A leakage clamp circuit is coupled between first and second terminals of the normally-off device. The leakage clamp circuit is coupled to clamp a voltage at an intermediate terminal between the normally-on device and the normally-off device at a threshold voltage level. The leakage clamp circuit is further coupled to clamp a voltage between the second terminal of the normally-on device and the control terminal of the normally-on device at the threshold voltage level to keep the normally-on device off when the normally-on device and the normally-off device are off.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: January 16, 2018
    Assignee: Power Integrations, Inc.
    Inventors: Hartley Horwitz, Sorin Georgescu, Kuo-Chang Robert Yang
  • Patent number: 9818821
    Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: November 14, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Mark M. Doherty