Plural Sections Connected In Parallel (e.g., Power Mosfet) Patents (Class 257/341)
  • Patent number: 10403758
    Abstract: A vertical MOS transistor includes a substrate having therein a first source/drain region and a first ILD layer. A nanowire is disposed in the first ILD layer. A lower end of the nanowire is in direct contact with the first source/drain region, and an upper end of the nanowire is coupled with a second source/drain region. The second source/drain region includes a conductive layer. A gate electrode is disposed in the first ILD layer. The gate electrode surrounds the nanowire. A contact hole is disposed in the first ILD layer. The contact hole exposes a portion of the first source/drain region. A contact plug is disposed in the contact hole. A second ILD layer covers the first ILD layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Wen Hung
  • Patent number: 10388801
    Abstract: A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mihir Mudholkar, Mohammed T. Quddus, Ikhoon Shin, Scott M. Donaldson
  • Patent number: 10381447
    Abstract: A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 13, 2019
    Assignee: NXP B.V.
    Inventors: Lukas Frederik Tiemeijer, Viet Thanh Dinh, Valerie Marthe Girault
  • Patent number: 10374079
    Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 6, 2019
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirotaka Saikaku, Jun Sakakibara, Shoji Mizuno, Yuichi Takeuchi
  • Patent number: 10373945
    Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 6, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Zheng Bian
  • Patent number: 10361267
    Abstract: A semiconductor device includes a compound semiconductor substrate including a gate region and an active region, a trench provided in a range between the gate region and the active region, a gate insulating film disposed in the trench, a source electrode, and a drain electrode. The gate region includes a first gate region of a p-type being in contact with the gate insulating film, a second gate region of the p-type having a p-type impurity concentration lower than a p-type impurity concentration of the first gate region, a third gate region of an n-type, and a fourth gate region of the p-type. The active region includes a source region of the n-type being in contact with the gate insulating film, a body region of the p-type facing the second gate region via the gate insulating film, and a drain region of the n-type.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 23, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takashi Okawa
  • Patent number: 10355122
    Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Satoshi Eguchi, Shigeaki Saito, Daisuke Taniguchi, Natsuo Yamaguchi
  • Patent number: 10340373
    Abstract: The present invention relates to the technical field of the power semiconductor device relates to a reverse conducting insulated gate bipolar transistor (RC-IGBT). The RC-IGBT comprises a P-type region, an N-type emitter region, a P-type body contact region, a dielectric trench, a collector region, and an electrical filed cutting-off region. The beneficial effect of the present invention is that, when compared with traditional RC-IGBT, the IGBT of the present invention can eliminate negative resistance effect and effectively improve the performance of forward and reverse conduction.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 2, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Xiaorong Luo, Gaoqiang Deng, Kun Zhou, Qing Liu, Linhua Huang, Tao Sun, Bo Zhang
  • Patent number: 10332828
    Abstract: Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 25, 2019
    Assignees: AGILE POWER SWITCH 3D—INTEGRATION APSI3D, IRT SAINT EXUPERY (AESE)
    Inventors: Jacques Pierre Henri Favre, Jean-Michel Francis Reynes, Raphaël Riva, Bernard José Charles Du Trieu De Terdonck
  • Patent number: 10276654
    Abstract: A semiconductor device including a substrate, an active portion and a well region both formed in the substrate on a first surface side thereof, and a low-resistivity layer formed in the substrate on a second surface side thereof. A first parallel pn structure is formed in the substrate between the active portion and the low-resistivity layer, the first parallel pn structure having a first region and a second region that are repeatedly alternated at a first repetition pitch. A second parallel pn structure is formed in the substrate between the well region and the low-resistivity layer, the second parallel pn structure having a third region and a fourth region that are repeatedly alternated at a second repetition pitch that is smaller than the first repetition pitch, the well region and the second parallel pn structure being isolated from each other.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Toshiaki Sakata
  • Patent number: 10262988
    Abstract: An electrostatic discharge protection device and a method of making the same. The device includes a device area located on a semiconductor substrate. The device also includes an array of coextensive, laterally spaced fingers located within the device area. Each finger includes an elongate source and an elongate drain separated by an elongate gate. The fingers are electrically connected in parallel for conducting an electrostatic discharge current during an electrostatic discharge event. The device further includes a plurality of body contact regions. A layout of the body contact regions is graded such that a greater number of the body contact regions, larger body contact regions, or both are located towards a periphery of the device area than towards a central part of the device area. The layout of the body contact regions may encourage triggering of the electrostatic discharge protection device within the central part of the device area.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: April 16, 2019
    Assignee: Nexperia B.V.
    Inventors: Gijs Jan De Raad, Suzana Domingues, Harrie Martinus Maria Horstink
  • Patent number: 10236342
    Abstract: An electronic device can include a termination structure that includes a substrate, a semiconductor layer, and a first trench. The substrate includes a semiconductor material of a first conductivity type. The semiconductor layer has a second conductivity type opposite the first conductivity type and overlies the substrate and has a primary surface. The first trench extends through a majority of a thickness of the semiconductor layer. In an embodiment, a body extension region of the second conductivity type is adjacent to the primary surface and spaced apart from the first trench. In another embodiment, a doped region of the first conductivity type is adjacent to the primary surface and abuts the first trench. In a further embodiment, the termination structure can include a second trench extending through a majority of the thickness of the semiconductor layer and a doped region is spaced apart from the first and second trenches.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 19, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gary H. Loechelt
  • Patent number: 10236352
    Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having a first side; forming a trench in the semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to the first side of the semiconductor substrate; forming an insulation structure including at least a first insulation layer and a second insulation layer on the sidewall and the bottom of the trench; forming a lower conductive structure in the lower portion of the trench; removing the second insulation layer in an upper portion of the trench while leaving the second insulation layer at least partially in a lower portion of the trench; and forming an upper conductive structure in the upper portion of the trench.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Robert Haase, Martin Vielemeyer
  • Patent number: 10236374
    Abstract: In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p? type drift layer comprised of the area in which the p type impurity is introduced, as well as an n? type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Kinya Ohtani, Yasuhiro Nishimura
  • Patent number: 10224424
    Abstract: A semiconductor module comprises a semiconductor chip comprising a semiconductor switch having a collector, emitter and gate, a collector terminal connected to the collector, gate terminal connected to the gate, an emitter terminal connected to the emitter via an emitter conductor path having an emitter inductance, an auxiliary emitter terminal connected to the emitter, a first conductor path connected to the emitter, and a second conductor path connected to the emitter having a different mutually inductive coupling with the emitter conductor path as the first conductor path. The first conductor path and the second conductor path are connectable to the auxiliary emitter terminal and/or the first conductor path is connected to the auxiliary emitter terminal and the second conductor path is connected to a second auxiliary emitter terminal.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: March 5, 2019
    Assignee: ABB Schweiz AG
    Inventors: Samuel Hartmann, Didier Cottet, Slavo Kicin
  • Patent number: 10217856
    Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 26, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Toshio Nakajima
  • Patent number: 10217636
    Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Victorina Poenariu, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Gerald Reinwald, Roland Rupp, Gerald Unegg
  • Patent number: 10186575
    Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: January 22, 2019
    Assignees: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuyuki Kawada, Shiyang Ji, Ryoji Kosugi, Hidenori Koketsu, Kazuhiro Mochizuki
  • Patent number: 10177045
    Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 8, 2019
    Assignee: Newport Fab, LLC
    Inventors: Edward J. Preisler, Marco Racanelli, Paul D. Hurwitz
  • Patent number: 10164084
    Abstract: A semiconductor device includes: an n+-type drain region made of a wide-bandgap semiconductor material; an n-type epitaxial layer provided on the top surface of the drain region; an n-type first semiconductor region provided at an upper portion of the epitaxial layer and having a higher impurity concentration than the epitaxial layer; an n-type second semiconductor region provided on the first semiconductor region and having a higher impurity concentration than the first semiconductor region; p-type base regions surrounding to include an upper portion in the middle of the second semiconductor region; n-type source regions provided at upper portions of the base regions to form a channel; and a gate electrode which controls a surface potentials of the channels.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: December 25, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Akimasa Kinoshita
  • Patent number: 10158345
    Abstract: Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 18, 2018
    Assignee: pSemi Corporation
    Inventors: Ronald Eugene Reedy, Dan William Nobbe, Tero Tapio Ranta, Cheryl V. Liss, David Kovac
  • Patent number: 10147791
    Abstract: A semiconductor device includes an n+-type source region having an impurity concentration higher than that of an n-type source region, formed in a surface layer of a p-type SiC layer and a p-type base region, farther on an outer side than the n-type source region, and contacting the n-type source region; an n-type region and an n+-type region having an impurity concentration higher than that of the n?-type SiC layer, formed in a portion of the n?-type SiC layer between p-type base regions and p-type SiC layers; and a second n-type region under the p-type base region and of a size smaller than that of the p-type base region, whereby low on-resistance and precision of the threshold voltage Vth are enhanced, increasing quality and enabling improved resistance to dielectric breakdown of the gate insulating film and resistance to breakdown.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Harada, Yasuyuki Hoshi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10134658
    Abstract: High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 20, 2018
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Aram Mkhitarian, Vincent Ngo
  • Patent number: 10128353
    Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 13, 2018
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 10121880
    Abstract: The present disclosure provides fin field-effect transistors and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a first region and a second region; forming first fins in the first region and second fins in the second region; forming a liner oxide layer on side surfaces of the first fins, the second fins and a surface of the substrate; forming an insulating barrier layer on the liner oxide layer in the first region; forming a precursor material layer on the insulating barrier layer in the first region and on the liner oxide layer in the second region; performing a curing annealing process to convert the precursor material into an insulation layer; and removing a top portion of the insulation layer to form an isolating layer and removing portions of the liner oxide layer, the insulating barrier layer, the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: November 6, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Gang Mao
  • Patent number: 10116298
    Abstract: An apparatus including a main transistor-based switch having a first end node and a second end node and an ON-state linearization network that is coupled between the first end node and the second end node of the main transistor-based switch is disclosed. The ON-state linearization network is configured to receive a monitored signal that corresponds to a signal across the first end node and the second end node and cancel at least a portion of non-linear distortion generated by the main transistor-based switch when the main transistor-based switch is in an ON-state based on the monitored signal. A control signal applied to a control input of the ON-state linearization network causes the ON-state linearization network to activate when the main transistor-based switch is in the ON-state and to deactivate the ON-state linearization network when the main transistor-based switch is an OFF-state.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 30, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Marcus Granger-Jones, Dirk Robert Walter Leipold, Jinsung Choi
  • Patent number: 10109489
    Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 23, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Patent number: 10103258
    Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Guru Mathur
  • Patent number: 10090297
    Abstract: A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n? drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: October 2, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10074744
    Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: September 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
  • Patent number: 10069002
    Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 4, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, Chun-Li Liu
  • Patent number: 10062768
    Abstract: Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: August 28, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Youn Sung Choi, Ukjin Roh, Shashank Ekbote
  • Patent number: 10056452
    Abstract: A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 21, 2018
    Assignees: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
    Inventors: Zehong Li, Wenlong Song, Xunyi Song, Hongming Gu, Youbiao Zou, Jinping Zhang, Bo Zhang
  • Patent number: 10038088
    Abstract: Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 31, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10026734
    Abstract: A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: July 17, 2018
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Brendan Toner, Tsui Ping Chu, Foo Sen Liew
  • Patent number: 10020390
    Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 10, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
  • Patent number: 10014267
    Abstract: A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a second region different from the first region, and a third region between the first and the second region, a first redistribution layer on a top surface of the semiconductor chip, the first redistribution layer configured to electrically connect a first electrode pad of the semiconductor chip to a first solder ball and overlap the first region of the gate structure, a second redistribution layer on the top surface of the semiconductor chip, the second redistribution layer configured to electrically connect a second electrode pad of the semiconductor chip to a second solder ball and overlap the second region of the gate structure such that the third region is exposed, and an insulating layer on the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: July 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sang Cho, Sang-Woo Pae, Hyun-Suk Chun, Young-Seok Jung
  • Patent number: 9997359
    Abstract: A semiconductor device includes a semiconductor body and a rear side insertion structure. The semiconductor body has a first surface at a front side and a second surface parallel to the first surface at a rear side, an active area and an edge termination area separating the active area from an outer surface of the semiconductor body. The outer surface connects the first and second surfaces, and element structures in the active area are predominantly formed closer to the first surface than to the second surface. The rear side insertion structure extends from the second surface into the semiconductor body in the edge termination area.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Anton Mauder, Erich Griebl
  • Patent number: 9991350
    Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 5, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hong Yang, Seetharaman Sridhar, Yufei Xiong, Yunlong Liu, Zachary K. Lee, Peng Hu
  • Patent number: 9991376
    Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 5, 2018
    Assignee: Monolith Semiconductor Inc.
    Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
  • Patent number: 9985019
    Abstract: A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region. A first well is in the substrate. The first well substantially contacts a side of the first light doping region and does not extend under the first light doping region. The conductive type of the first well is opposite that of the first light doping region. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region is disposed in the first well and the first light doping region at two sides of the first gate stack. The conductive type of the first heavy doping region is opposite that of the first light doping region.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 29, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Jun-Wei Chen
  • Patent number: 9978832
    Abstract: A vertical superjunction edge termination structure for the drift region of wide bandgap semiconductor devices that provides a low resistance and high off voltage allowing the breakdown voltage of the superjunction drift region to be raised.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: May 22, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventor: Christopher Adrian Martino
  • Patent number: 9960588
    Abstract: Devices and methods are provided which comprise detecting an irregular condition at a control terminal of a power switch device.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans-Peter Kreuter, Christian Djelassi, Bernhard Schaffer
  • Patent number: 9960237
    Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: May 1, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
  • Patent number: 9945886
    Abstract: An electrical current detection device is provided with a shunt resistor that includes a first conducting part, a second conducting part, a center conducting part disposed between the first conducting part and the second conducting part, a first resistor disposed between the first conducting part and the center conducting part, and a second resistor disposed between the second conducting part and the center conducting part, the second resistor having a greater resistance value than the first resistor. The electrical current detection device is further provided with: a signal output unit; an estimation unit that estimates a first estimated current value from the first detection signal, and estimates a second estimated current value from the second detection signal; and an determination unit that compares the first estimated current value and the second estimated current value, and determines the abnormality of the shunt resistor.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: April 17, 2018
    Assignee: SANYO ELECTRIC CO., LTD.
    Inventors: Masaki Yugou, Kimihiko Furukawa
  • Patent number: 9947647
    Abstract: A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 17, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Mark Gerard Roberto, David Mulford Shaddock, Joe Walter Kirstein
  • Patent number: 9947574
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a first conductive layer provided on the first insulating film, a second insulating film provided on the semiconductor layer and the first conductive layer, a second conductive layer provided on the second insulating film, a first contact portion connecting the semiconductor layer and the second conductive layer, and a second contact portion connecting the first conductive layer and the second conductive layer. A distance between the semiconductor layer and an upper portion of the second insulating film adjacent to the second contact portion is greater than a distance between the semiconductor layer and an upper portion of the second insulating film adjacent to the first contact portion. The second contact portion has a larger width than the first contact portion.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 17, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukie Nishikawa, Motoya Kishida
  • Patent number: 9929232
    Abstract: An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film. At least a remaining portion of the surface of the doped regions is covered by an absorbing film and the doped regions are heated through the absorbing film, enabling an impurity region of the second conductivity type to be formed having two or more of the doped regions that have a same impurity concentration and differing carrier concentrations.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomonori Katano, Fumikazu Imai
  • Patent number: 9905555
    Abstract: An SJ-MOSFET and IGBT are provided in a single semiconductor chip. Furthermore, a balance is made between a carrier amount of n-type columns and a carrier amount of p-type columns, to encourage formation of a depletion layer in when a reverse voltage is applied in the SJ-MOSFET section. Provided is a includes a semiconductor substrate, a super junction structure formed on a front surface side of the semiconductor substrate, and a field stop layer formed at a position overlapping with the super junction structure on a back surface side of the semiconductor substrate, in a manner to not contact an end of the super junction structure on the back surface side.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tatsuya Naito, Masahito Otsuki
  • Patent number: 9887695
    Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 6, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Alexander Dribinsky, Tae Youn Kim, Dylan J. Kelly, Christopher N. Brindle