Plural Sections Connected In Parallel (e.g., Power Mosfet) Patents (Class 257/341)
  • Patent number: 11569379
    Abstract: In the semiconductor device, a high-concentration diffusion layer and a low-concentration diffusion layer are disposed around a drain diffusion layer of an ESD protection element. The high-concentration diffusion layer is separated from a gate electrode, and a medium concentration LDD diffusion layer is disposed in a separation gap. Variations in characteristics are suppressed by reducing thermal treatment on the high-concentration diffusion layer and a medium concentration diffusion layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: January 31, 2023
    Assignee: ABLIC Inc.
    Inventor: Masahiro Hatakenaka
  • Patent number: 11545488
    Abstract: An integrated circuit includes; a substrate including a single active region, a first active resistor formed on the substrate, and a transistor including a first junction area in the single active region. The first active resistor and the transistor are electrically connected through the first junction area. The first active resistor is formed between a first node and a second node included in the first junction area. The first node is connected to a first contact, and the second node is connected to a second contact.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Bum Kim, Sunghoon Kim, Daeseok Byeon
  • Patent number: 11538936
    Abstract: A semiconductor device includes: an n?-type epitaxial layer having an element main surface; a p?-type body region, an n+-type source region, and n+-type drain regions; and a gate electrode including a second opening and first openings formed in a portion separated from the second opening toward the drain regions, wherein the body region selectively has a second portion exposed to the first openings of the gate electrode, and wherein the semiconductor device further includes a p+-type body contact region formed in the portion of the body region exposed to the first openings and having an impurity concentration higher than an impurity concentration of the body region.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 27, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Yusuke Shimizu
  • Patent number: 11538904
    Abstract: Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 27, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Yuto Osawa, Toshio Nakajima, Shuta Kojima
  • Patent number: 11521926
    Abstract: The present disclosure relates to a semiconductor device structure with a serpentine conductive feature and a method for forming the semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed over the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed over the first mask layer. The first mask layer and the second mask layer are made of different materials. The semiconductor device structure further includes a conductive feature penetrating through the first mask layer and the second mask layer to connect to the conductive pad. The conductive feature has a serpentine pattern in a top view.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 11521894
    Abstract: Contact designs for semiconductor FET devices are provided. In one aspect, a contact structure includes: a metal line(s); a first ILD surrounding the metal line(s), wherein a top surface of the first ILD is recessed below a top surface of the metal line(s); a liner disposed on the first ILD and on portions of the metal line(s); a top contact(s) disposed over, and in direct contact with, the metal line(s), wherein an upper portion of the top contact(s) has a width W1 and a height H1, wherein a lower portion of the top contact(s) has a width W2 and a height H2, and wherein W1<W2 and H1>H2; and a second ILD disposed over the liner and surrounding the top contact(s). A semiconductor FET device and methods for fabrication thereof are also provided.
    Type: Grant
    Filed: July 18, 2020
    Date of Patent: December 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Ekmini Anuja De Silva, Eric Miller
  • Patent number: 11508844
    Abstract: A semiconductor device (300) comprising: a doped semiconductor substrate (302); an epitaxial layer (304), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region disposed on top of the epitaxial layer; and a contact diffusion (350) disposed on top of the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 22, 2022
    Assignee: Nexperia B.V.
    Inventors: Soenke Habenicht, Steffen Holland
  • Patent number: 11495675
    Abstract: The present disclosure provides a manufacture method of an LDMOS. The manufacture method includes: forming a drift region in a substrate; forming a gate structure on the substrate, the gate structure defining a source region and a drain region which are separated from each other, and the gate structure including a gate oxide layer and a gate conductor layer which are successively stacked on the substrate; forming a first doped region in the source region, wherein the first doped region is surrounded by the drift region; forming a first barrier layer with a first opening on the source region and in connect with sidewall of the gate structure; forming a first implantation region in the source region through self-aligned implantation on the basis of the first opening of the first barrier layer; and forming a second implantation region and a third implantation region respectively.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: November 8, 2022
    Assignee: JOULWATT TECHNOLOGY CO., LTD.
    Inventor: Guangtao Han
  • Patent number: 11495666
    Abstract: According to one embodiment, a semiconductor device includes first, second, third semiconductor members, a first conductive member, a connection member, and an insulating member. The first electrode includes first, second, and third electrode regions. A direction from the first toward second electrode is along a first direction. The second electrode includes fourth, fifth, and sixth electrode regions. The first semiconductor member includes first, second, third, fourth, and fifth partial regions. The second semiconductor member includes first and second semiconductor regions. The third semiconductor member includes third and fourth semiconductor regions. The third electrode is provided between the third partial region and the sixth electrode region in the first direction. The connection member is electrically connected to the first conductive member and the second electrode. The insulating member includes first, second, third, fourth, and fifth portions.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: November 8, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiro Gangi, Yusuke Kobayashi, Tomoaki Inokuchi, Tatsunori Sakano
  • Patent number: 11486613
    Abstract: A power converter includes a first substrate on which a module including a switching element is mounted, a second substrate on which a smoothing capacitor is mounted, and a terminal block connecting the first substrate and the second substrate, with the first and second substrates located to face each other. The terminal block includes a current path over which at least one of current flowing from the module to the smoothing capacitor and current flowing from the smoothing capacitor to the module flows.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: November 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenta Yuasa, Yoshihiro Taniguchi, Yoshikazu Nozuki
  • Patent number: 11476192
    Abstract: A semiconductor device includes: a first gate line and a second gate line extending only along a first direction, a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line, a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line, and first contact plugs on the first gate line. Preferably, the first direction is perpendicular to the second direction and the first gate line and the second gate line are directly connected to the fifth gate line and the sixth gate line.
    Type: Grant
    Filed: January 5, 2020
    Date of Patent: October 18, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 11462620
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a gate structure extending from a first surface into the semiconductor substrate, a plurality of needle-shaped first field plate structures extending from the first surface into the semiconductor substrate, body regions of a second conductivity type, and source regions of a first conductivity type formed between the body regions and the first surface. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: October 4, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cédric Ouvrard, Li Juin Yip
  • Patent number: 11450734
    Abstract: A semiconductor device includes an edge terminal structure portion provided between the active portion and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate, in which the edge terminal structure portion has a first high concentration region of the first conductivity type which has a donor concentration higher than a doping concentration of the bulk donor in a region between the upper surface and a lower surface of the semiconductor substrate, an upper surface of the first high concentration region is located on an upper surface side of the semiconductor substrate, and a lower surface of the first high concentration region is located on a lower surface side of the semiconductor substrate.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: September 20, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motoyoshi Kubouchi, Kosuke Yoshida, Soichi Yoshida, Koh Yoshikawa, Nao Suganuma
  • Patent number: 11444156
    Abstract: Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 13, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hayato Okamoto, Ze Chen
  • Patent number: 11437466
    Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Liang-Yu Su, Hung-Chih Tsai, Ruey-Hsin Liu, Ming-Ta Lei, Chang-Tai Yang, Te-Yin Hsia, Yu-Chang Jong, Nan-Ying Yang
  • Patent number: 11417687
    Abstract: A high-definition display device is provided. A display device with low power consumption is provided. A highly reliable display device is provided. The display device includes a first transistor and a display element electrically connected to the first transistor. The first transistor includes a first oxide, a second oxide, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor and the second conductor are positioned over the first oxide to be apart from each other. The first insulator is positioned over the first conductor and the second conductor and includes an opening. The opening overlaps with a portion between the first conductor and the second conductor. The third conductor is positioned in the opening. The second insulator is positioned between the third conductor, and the first oxide, the first conductor, the second conductor, and the first insulator.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 16, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koji Kusunoki, Yoshiaki Oikawa, Kensuke Yoshizumi
  • Patent number: 11411495
    Abstract: Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a split-gate structure. For example, an Integrated Circuit (IC) may include a MOS including a body; a source; a drain; and a split-gate structure including a control gate and at least one voltage-controlled Field-Plate (FP), the control gate is between the source and the voltage-controlled FP, the voltage-controlled FP is between the control gate and the drain, the control gate configured to switch the MOS transistor between an on state and an off state according to a switching voltage; and a voltage controller configured to apply a variable control voltage to the voltage-controlled FP, the variable control voltage based on at least one control parameter, the at least one control parameter including at least one of a load current driven by the MOS transistor or a switching frequency of the switching voltage.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 9, 2022
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventor: Erez Sarig
  • Patent number: 11404546
    Abstract: The disclosure discloses an LDMOSFET device. The second side of a polysilicon gate is extended to the surface of a drift region field oxide and forms a first field plate. A second field plate dielectric layer and a second field plate are formed between the second side of the polysilicon gate and the second side of the drift region field oxide. The second field plate is formed by a metal silicide formed on the surface of the self-aligned block dielectric layer. The first field plate and the second field plate are connected together through a metal layer and are connected to a gate formed by the metal layer. The disclosure further discloses a method for making the LDMOSFET device. The disclosure can optimize the relationship between BV and Rsp of the device.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 2, 2022
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Zhaozhao Xu
  • Patent number: 11393899
    Abstract: High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure and at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active area of the semiconductor substrate at a side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. A bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: July 19, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Chao Sun
  • Patent number: 11367674
    Abstract: High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 21, 2022
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Aram Mkhitarian, Vincent Ngo
  • Patent number: 11349000
    Abstract: An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 31, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Shintaroh Sato, Akio Shima, Ryo Kuwana, Isao Hara
  • Patent number: 11316042
    Abstract: A superjunction device comprising a drain contact, a substrate layer above the drain contact, an epitaxial layer above the substrate layer, a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device, a trench with a sloped angle formed by use of a hard mask layer. The trench is filled with an insulating material. A first vertical column is formed adjacent to the trench. A second vertical column is formed adjacent to the first vertical column. A source contact is coupled to the first vertical column and the second vertical column. A P-body region is coupled to the source contact. A gate oxide is formed above the source contact and the epitaxial layer, and a gate formed above the gate oxide.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 26, 2022
    Assignee: POWER INTEGRATIONS, INC.
    Inventors: Alexei Ankoudinov, Sorin S. Georgescu
  • Patent number: 11302789
    Abstract: A semiconductor structure and a formation method thereof are provided. The semiconductor structure includes: a semiconductor substrate having a source region or drain region therein. The source region or drain region has a groove. The semiconductor structure can include a metal silicide layer arranged on a surface of a sidewall of the groove and an insulating layer arranged on a bottom surface of the groove. The edge of the insulating layer is in contact with a bottom surface of the metal silicide layer on the sidewall of the groove; and a conducting layer filled in the groove and arranged on the metal silicide layer and the insulating layer. The semiconductor structure of the present disclosure can prevent electric current from leaking into the semiconductor substrate at the bottom of the source/drain region.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: April 12, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Patent number: 11276757
    Abstract: A silicon carbide semiconductor device includes an insulated-gate electrode structure that is formed inside a gate trench that goes through a base region and reaches a upper portion of a current transport layer to control a primary current flowing through the base region; a current suppression layer of the second conductivity type embedded within an upper portion of the current transport layer; a control electrode isolation insulating film filled into a control electrode isolation trench that goes through the base region and reaches an upper portion of the current suppression layer; and a control electrode pad disposed on the control electrode isolation insulating film, wherein an upper portion of the current suppression layer abuts a sidewall of the control electrode isolation insulating film, and a lower portion of the current suppression layer covers at least bottom corners of the control electrode isolation insulating film.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11257946
    Abstract: A method of forming a power semiconductor device includes: arranging a control electrode at least partially on or inside a semiconductor body; forming elevated source regions in the semiconductor body by: implanting first conductivity type dopants into the semiconductor body; forming a recess mask layer covering at least areas of intended source regions; and removing portions of the semiconductor body uncovered by the recess mask layer to form the elevated source regions and recessed body regions at least partially between the source regions. A dielectric layer is formed on the semiconductor body. A contact hole mask layer is formed on the dielectric layer. Portions of the dielectric layer uncovered by the contact hole mask layer are removed to form a contact hole which is filled at least partially with a conductive material to establish an electrical contact with at least a portion of the elevated source and recessed body regions.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: February 22, 2022
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Erich Griebl, Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer
  • Patent number: 11239350
    Abstract: A semiconductor device including a first conductivity type substrate, a first conductivity type carrier store layer formed on an upper surface side of the substrate, a second conductivity type channel dope layer formed on the carrier store layer, a first conductivity type emitter layer formed on the channel dope layer, a gate electrode in contact with the emitter layer, the channel dope layer and the carrier store layer via a gate insulating film, and a second conductivity type collector layer formed on a lower surface side of the substrate, wherein the gate insulating film has a first part in contact with the emitter layer and the channel dope layer, a second part in contact with the carrier store layer, and a third part in contact with the substrate, and at least a part of the second part is thicker than the first part and the third part.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: February 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tetsuo Takahashi
  • Patent number: 11233163
    Abstract: In one embodiment, a photo detection element includes a first region of a first conductivity type, a second region of a second conductivity type, a third region of the first conductivity type provided between the second region and the first region, and a plurality of structure bodies of the first conductivity type which are provided between the first region and the third region separately in a second direction crossing with a first direction from the third region toward the second region.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 25, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuki Nobusa, Ikuo Fujiwara, Kazuhiro Suzuki
  • Patent number: 11233157
    Abstract: A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 25, 2022
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
  • Patent number: 11222151
    Abstract: A SEB resistance evaluation method includes: disposing an excitation source within a model of a semiconductor device; and determining an energy of the excitation source at which the semiconductor device exhibits thermal runaway, while varying a voltage applied to the model of the semiconductor device and the energy of the excitation source.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: January 11, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsumi Uryu, Tadaharu Minato, Takahiro Nakatani
  • Patent number: 11217689
    Abstract: In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: January 4, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Dean E. Probst, Peter A. Burke, Prasad Venkatraman
  • Patent number: 11211483
    Abstract: A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
  • Patent number: 11189689
    Abstract: A superjunction layer includes first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are provided respectively on the second pillars to reach the first pillars and are of the second conductivity type. First impurity regions are provided respectively on the first wells and are of the first conductivity type. Second wells are provided respectively on the first pillars, spaced from the second pillars in a section of an active region that is perpendicular to a semiconductor layer, and are of the second conductivity type. Second impurity regions are provided respectively on the second wells and are of the first conductivity type.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 30, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masayuki Furuhashi, Nobuo Fujiwara, Naoyuki Kawabata
  • Patent number: 11171135
    Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyojin Kim, Jihye Lee, Sangmoon Lee, Seung Hun Lee
  • Patent number: 11164797
    Abstract: A method of manufacturing a semiconductor integrated circuit, includes: forming a first well region having a second conductivity type in an upper portion of a support layer having a first conductivity type; forming an oxide film on the first well region by a thermal oxidation method to decrease a concentration of impurities at an top surface of top surface side of the first well region; removing the oxide film; forming a second well region having the first conductivity type in an upper portion of the first well region; and merging a semiconductor element having a main electrode region having the second conductivity type in the second well region.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: November 2, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Toyoda
  • Patent number: 11139292
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Patent number: 11133379
    Abstract: A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: September 28, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jae-gil Lee, Jin-myung Kim, Kwang-won Lee, Kyoung-deok Kim, Ho-cheol Jang
  • Patent number: 11121211
    Abstract: A lateral superjunction includes a substrate layer, a selective epitaxy layer deposited on the substrate layer, a trench formed into the selective epitaxy layer to expose a portion of the substrate layer, a first layer of semiconductor deposited in the trench, a second layer of semiconductor deposited adjacent to the first layer, and a first end layer of semiconductor deposited adjacent to the first layer of semiconductor and a second end layer of semiconductor deposited adjacent to the second layer of semiconductor.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 14, 2021
    Assignee: The Texas A&M University System
    Inventors: Michael Everett Babb, Harlan Rusty Harris
  • Patent number: 11101372
    Abstract: Power semiconductor devices can often be expensive to produce and/or expensive to operate (i.e. inefficient). The present structure seeks to overcome these problems by providing a double-sided vertical power transistor structure that poses a unipolar path and a second parallel bipolar path.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: August 24, 2021
    Inventor: John Wood
  • Patent number: 11094779
    Abstract: An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 17, 2021
    Assignee: Infineon Technologies AG
    Inventors: Philip Christoph Brandt, Andre Rainer Stegner, Francisco Javier Santos Rodriguez, Frank Dieter Pfirsch, Hans-Joachim Schulze, Manfred Pfaffenlehner, Thomas Auer
  • Patent number: 11075264
    Abstract: Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/?1.5° of a crystallographic axis of the silicon carbide material forming the drift region.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 27, 2021
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Alexander V. Suvorov, Vipindas Pala, Daniel J. Lichtenwalner, Qingchun Zhang
  • Patent number: 11070127
    Abstract: A semiconductor device that compensates for imbalance between a plurality of semiconductor elements connected in parallel by negative feedback to achieve current balance utilizing reversed temperature characteristics without providing any dedicated element just for cancelling temperature characteristics. A gate driving circuit turns ON a power semiconductor element by applying a voltage elevated by a charge pump (CP) circuit to a gate through a resistor connected between the CP circuit and the gate. The power semiconductor element is turned OFF by control circuit that gives a control signal to turn ON a MOS switch in the gate driving circuit and discharges the gate through a diode.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: July 20, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Morio Iwamizu
  • Patent number: 11056581
    Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 6, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna, Meng-Chia Lee, Ralph N. Wall
  • Patent number: 10998398
    Abstract: A semiconductor device includes a plurality of broad buffer layers provided in a drift layer. Each of the plurality of the broad buffer layers has an impurity concentration exceeding that of a portion of the drift layer excluding the broad buffer layers, and has a mountain-shaped impurity concentration distribution in which a local maximum value is less than the impurity concentration of an anode layer and a cathode layer. The plurality of broad buffer layers are disposed at different depths from a first main surface of the drift layer, respectively, the number of broad buffer layers close to the first main surface from the intermediate position of the drift layer is at least one, and number of broad buffer layers close to a second main surface of the drift layer from the intermediate position of the drift layer is at least two. The broad buffer layer includes a hydrogen-related donor.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: May 4, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Michio Nemoto, Takashi Yoshimura
  • Patent number: 10991812
    Abstract: Disclosed is a transistor device. The transistor device includes: in a semiconductor body, a drift region, a body region adjoining the drift region, and a source region separated from the drift region by the body region; a gate electrode dielectrically insulated from the body region by a gate dielectric; a source electrode electrically connected to the source region; at least one field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a rectifier element coupled between the source electrode and the field electrode. The field electrode and the field electrode dielectric are arranged in a first trench that extends from a first surface of the semiconductor body into the semiconductor body. The rectifier element is integrated in the first trench in a rectifier region that is adjacent at least one of the source region and the body region.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 27, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Robert Haase, Gerhard Noebauer, Martin Poelzl
  • Patent number: 10978387
    Abstract: A semiconductor device includes: first, second, and third tiers formed on a substrate, wherein the first tier is formed over the substrate, the second tier is formed over the first tier, and the third tier is formed over the second tier, wherein the second tier comprises a first interconnection line that is configured to transmit a signal, and wherein a portion of the first tier disposed directly under the first interconnection line of the second tier lacks any interconnection lines and a portion of the third tier disposed directly above the first interconnection line of the second tier lacks any interconnection lines.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Cheng, Tien-Chien Huang
  • Patent number: 10965281
    Abstract: An electronic circuit provided with a III/V semiconductor domain, and a method of operating such a circuit is presented. In particular, the present application relates to electronic circuit based on a Gallium Nitride (GaN) semiconductor. GaN components must be controlled in a way that ensures proper operation over a wide variation of GaN parameters. There is a circuit comprising a first domain coupled to a second domain, the first domain being based on a III/V semiconductor; wherein the first domain comprises a first component and a second component. The second component being representative of an electrical characteristic of the first component. The second domain contains a sensor adapted to sense an electrical quantity of the second component and an input generator coupled to the sensor. The input generator is adapted to provide at least one input, based on the electrical quantity, to the first domain.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 30, 2021
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Christoph Nagl, Nebojsa Jelaca, Horst Knoedgen
  • Patent number: 10957792
    Abstract: A semiconductor device includes a body region of a second conductivity type, a body contact region of the second conductivity type formed in the body region and having a higher average doping concentration than the body region, a source region of a first conductivity type opposite the second conductivity type formed in the body region adjacent the body contact region, a drift zone of the first conductivity type spaced apart from the source region by a section of the body region which forms a channel region of the semiconductor device, and a gate electrode configured to control the channel region. The body contact region extends under a majority of the source region in a direction towards the channel region and has a doping concentration of at least 1e18 cm?3 under the majority of the source region. Additional semiconductor device embodiments and methods of manufacture are described.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Chi Dong Nguyen, Andreas Rupp
  • Patent number: 10957788
    Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Hölzl, Henning Kraack, Gabor Mezoesi, Hans-Joachim Schulze, Waqas Mumtaz Syed
  • Patent number: 10930775
    Abstract: A silicon carbide semiconductor device has a rectangle-shaped active region in which a main current flows, and a termination region surrounding the active region in a plan view. The device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type on the front surface of the substrate, a second semiconductor layer of a second conductivity type, at a surface at the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer, the second semiconductor region disposed from a periphery of the active region to reach the termination region, and extending along each of directions of four sides of the active region. At the four sides of the active region, a cross-sectional structure of each layer and each region of the device is identical to one another.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Hoshi, Yuichi Hashizume, Keishirou Kumada
  • Patent number: RE48450
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii