Plural Sections Connected In Parallel (e.g., Power Mosfet) Patents (Class 257/341)
  • Patent number: 10770583
    Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: September 8, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kengo Omori
  • Patent number: 10770380
    Abstract: A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 8, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Akihiro Kimura, Takeshi Sunaga, Shouji Yasunaga, Akihiro Koga
  • Patent number: 10753964
    Abstract: An integrated circuit device for controlling and sensing electrical current is provided. The integrated circuit device comprises a main transistor device, configured for controlling a main current, and a plurality of sensing transistor devices, configured for controlling a combined sensing current. The main transistor device and the plurality of sensing transistor devices are connected to a common gate node. The on-state resistance of the main transistor device is lower than a combined on-state resistance of the plurality of sensing transistor devices. The sensing transistor devices are distributed throughout at least a section of the integrated circuit to reduce an influence of at least one local property of the integrated circuit device on the combined sensing current.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 25, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Philippe Deval
  • Patent number: 10746890
    Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Furen Lin, Frank Baiocchi, Haian Lin, Yunlong Liu, Lark Liu, Wei Song, ZiQiang Zhao
  • Patent number: 10727326
    Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Meng-Chia Lee, Ralph N. Wall, Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna
  • Patent number: 10707312
    Abstract: According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate, a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies, a gate adjacent to the base layer with a gate insulating film therebetween, a source layer connected to the base layer, and a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 7, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Matsuba, Hung Hung, Tatsuya Nishiwaki, Kikuo Aida, Kohei Oasa
  • Patent number: 10692998
    Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 23, 2020
    Assignee: Cree, Inc.
    Inventors: Khaled Fayed, Simon Wood
  • Patent number: 10679984
    Abstract: A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes: a unipolar component at least including an epitaxial layer; a transition layer connected to the epitaxial layer; and a bypass component connected to the transition layer; the unipolar component and the bypass component are connected in parallel and the transition layer is configured between the unipolar component and the bypass component.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Hiroshi Shikauchi, Satoru Washiya, Yuki Tanaka, Ning Wei
  • Patent number: 10658497
    Abstract: A method for forming semiconductor device includes providing a semiconductor substrate having an initial surface oxygen concentration in a surface region of less than 6×1017 cm?3, forming an epitaxial layer on a first side of the semiconductor substrate, and implanting dopants into the epitaxial layer. An optional thermal anneal is carried out prior to forming the epitaxial layer and/or a thermal treatment is carried out after implanting dopants.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 19, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Hölzl, Henning Kraack, Gabor Mezoesi, Hans-Joachim Schulze, Waqas Mumtaz Syed
  • Patent number: 10651124
    Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 12, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Yenting Wen, George Chang
  • Patent number: 10629725
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoyuki Ohse
  • Patent number: 10615273
    Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 7, 2020
    Assignee: Cree, Inc.
    Inventors: Yueying Liu, Saptharishi Sriram, Scott Sheppard
  • Patent number: 10593781
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 17, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Yan Chen, Yan Chun Ma, Dae-Sub Jung
  • Patent number: 10586791
    Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: March 10, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Qingjie Ma, Wei Xu, Jingwei Xu, Yang Wang
  • Patent number: 10580951
    Abstract: A package structure for a backlight module includes a flexible base film, a plurality of pads, a light-emitting component, a patterned circuit layer. The flexible base film includes a plurality of conductive vias, a first surface, and a second surface opposite to the first surface. The conductive vias connect the first surface and the second surface. In addition, a material of the flexible base film includes polyimide and white fillings. The pads are disposed on the first surface. The conductive vias are connected to the pads. The light-emitting component is disposed on the pads and electrically connected to the pads. The patterned circuit layer is disposed on the second surface and electrically connected to the conductive vias.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 3, 2020
    Assignee: UNIFLEX Technology Inc.
    Inventors: Yi-Chun Liu, Ying-Hsing Chen, Bo-Hua Chen, Yuan-Chih Lee
  • Patent number: 10580884
    Abstract: Methods and designs are provided for a vertical power semiconductor switch having an IGBT-with-built-in-diode bottom-side structure combined with a SJMOS topside structure in such a way as to provide fast switching with low switching losses (MOSFET), low on-resistance at low currents (SJMOS), low on-resistance at high currents (IGBT), and high current-density capability (IGBT).
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 3, 2020
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Zhijun Qu
  • Patent number: 10573584
    Abstract: A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 25, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Akihiro Kimura, Takeshi Sunaga, Shouji Yasunaga, Akihiro Koga
  • Patent number: 10573594
    Abstract: A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a Doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. The isolation feature can take the form of a structure that is constructed of a conductive material coupled to ground and which separates the elements of the amplifier. The isolation feature can be included in a variety of semiconductor packages, including air cavity packages and overmolded packages. Through the use of the isolation feature provided by embodiments of the present invention a significant improvement in signal isolation between amplifier elements is realized, thereby improving performance of the dual-path amplifier.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: February 25, 2020
    Assignee: NXP USA, Inc.
    Inventors: Peter H. Aaen, David J. Dougherty, Manuel F. Romero, Lakshminarayan Viswanathan
  • Patent number: 10559682
    Abstract: To provide a semiconductor apparatus including: a semiconductor substrate having a drift region; an emitter region provided inside the semiconductor substrate and above the drift region; a base region provided between the emitter and drift regions; an accumulation region provided between the base and drift regions; and a plurality of gate trench portions provided to penetrate the accumulation region from an upper surface of the semiconductor substrate. The base region has: a low concentration base region provided in contact with the gate trench portions; and a high concentration base region provided apart from the gate trench portions and having a doping concentration higher than the low concentration base region. The high concentration base region is provided below the emitter region, and a width of the high concentration base region in a depth direction of the semiconductor substrate is larger than 0.1 ?m.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: February 11, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10527654
    Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 7, 2020
    Assignee: Vishay SIliconix, LLC
    Inventors: M. Ayman Shibib, Wenjie Zhang
  • Patent number: 10529799
    Abstract: A semiconductor device includes a semiconductor substrate, and a semiconductor layer disposed on the semiconductor substrate. First and second pillar layers, of respective first and second conductivity types, are alternately provided in a direction in parallel with a main surface in an active region of the semiconductor layer and in a termination region. A pillar pitch in the termination region is set to be larger than a pillar pitch in the active region. A product of a width of one of the first pillar layers and effective impurity concentration of the first conductivity of the one of the first pillar layers is equal to a product of a width of one of the second pillar layers and effective impurity concentration of the second conductivity of the one of the second pillar layers.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: January 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masayuki Furuhashi, Kohei Ebihara
  • Patent number: 10510878
    Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chung-Yen Chien, Sheng-Wei Fu, Chung-Yeh Lee
  • Patent number: 10497777
    Abstract: A semiconductor power device includes an n-type drift layer, a plurality of first p-doped regions, a plurality of n-doped regions, a plurality of second p-doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a plurality of source contacts. Each first p-doped region includes a first p-doped portion and a plurality of first p-doped arms extending outwards from the first p-doped portion. Each n-doped region includes an n-doped portion and a plurality of n-doped arms extending outwards from the n-doped portion.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 3, 2019
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee
  • Patent number: 10490548
    Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 26, 2019
    Assignee: Power Integrations, Inc.
    Inventors: Alexey Kudymov, Jamal Ramdani
  • Patent number: 10483389
    Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 19, 2019
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Patent number: 10468479
    Abstract: A semiconductor device includes a semiconductor body, which includes transistor cells and a drift zone between a drain layer and the transistor cells. The drift zone includes a compensation structure. Above a depletion voltage a first output charge gradient obtained by increasing a drain-to-source voltage from the depletion voltage to a maximum drain-to-source voltage deviates by less than 5% from a second output charge gradient obtained by decreasing the drain-to-source voltage from the maximum drain-to-source voltage to the depletion voltage. At the depletion voltage the first output charge gradient exhibits a maximum curvature.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Bjoern Fischer, Joachim Weyers
  • Patent number: 10461180
    Abstract: A semiconductor device including: drift regions formed on a semiconductor substrate; gate trench portions extending in predetermined extending directions from a semiconductor substrate upper surface; first and second mesa portions being in direct contact with one and the other sides of a gate trench portion side wall respectively; accumulation regions being in direct contact with the gate trench portions, above the drift regions, and having doping concentration higher than drift region concentration; a base region being in direct contact with the gate trench portions, above the accumulation regions; emitter regions being in direct contact with the one side wall of a gate trench portion on a semiconductor substrate upper surface in the first mesa portion, and having doping concentration higher than drift region concentration; and electrically floating second conductivity type floating regions provided spaced from the gate trench portion below the base region in the second mesa portion is provided.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 29, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10453928
    Abstract: According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: October 22, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventor: Raymond A. Kjar
  • Patent number: 10446497
    Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 15, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Dan Grimm, Gregory Dix
  • Patent number: 10418442
    Abstract: Provided is a trench gate MOSFET including a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a first conductive layer of a second conductivity type, a second conductive layer and an interlayer insulating layer. The epitaxial layer is disposed on the substrate and has at least one trench therein. The first conductive layer is disposed in the lower portion of the trench and in physical contact with the epitaxial layer. The second conductive layer is disposed in the upper portion of the trench. The interlayer insulating layer is disposed between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: September 17, 2019
    Assignee: UBIQ Semiconductor Corp.
    Inventors: Chin-Fu Chen, Yi-Yun Tsai
  • Patent number: 10403758
    Abstract: A vertical MOS transistor includes a substrate having therein a first source/drain region and a first ILD layer. A nanowire is disposed in the first ILD layer. A lower end of the nanowire is in direct contact with the first source/drain region, and an upper end of the nanowire is coupled with a second source/drain region. The second source/drain region includes a conductive layer. A gate electrode is disposed in the first ILD layer. The gate electrode surrounds the nanowire. A contact hole is disposed in the first ILD layer. The contact hole exposes a portion of the first source/drain region. A contact plug is disposed in the contact hole. A second ILD layer covers the first ILD layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Wen Hung
  • Patent number: 10388801
    Abstract: A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mihir Mudholkar, Mohammed T. Quddus, Ikhoon Shin, Scott M. Donaldson
  • Patent number: 10381447
    Abstract: A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 13, 2019
    Assignee: NXP B.V.
    Inventors: Lukas Frederik Tiemeijer, Viet Thanh Dinh, Valerie Marthe Girault
  • Patent number: 10373945
    Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 6, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Zheng Bian
  • Patent number: 10374079
    Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 6, 2019
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirotaka Saikaku, Jun Sakakibara, Shoji Mizuno, Yuichi Takeuchi
  • Patent number: 10361267
    Abstract: A semiconductor device includes a compound semiconductor substrate including a gate region and an active region, a trench provided in a range between the gate region and the active region, a gate insulating film disposed in the trench, a source electrode, and a drain electrode. The gate region includes a first gate region of a p-type being in contact with the gate insulating film, a second gate region of the p-type having a p-type impurity concentration lower than a p-type impurity concentration of the first gate region, a third gate region of an n-type, and a fourth gate region of the p-type. The active region includes a source region of the n-type being in contact with the gate insulating film, a body region of the p-type facing the second gate region via the gate insulating film, and a drain region of the n-type.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 23, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takashi Okawa
  • Patent number: 10355122
    Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Satoshi Eguchi, Shigeaki Saito, Daisuke Taniguchi, Natsuo Yamaguchi
  • Patent number: 10340373
    Abstract: The present invention relates to the technical field of the power semiconductor device relates to a reverse conducting insulated gate bipolar transistor (RC-IGBT). The RC-IGBT comprises a P-type region, an N-type emitter region, a P-type body contact region, a dielectric trench, a collector region, and an electrical filed cutting-off region. The beneficial effect of the present invention is that, when compared with traditional RC-IGBT, the IGBT of the present invention can eliminate negative resistance effect and effectively improve the performance of forward and reverse conduction.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 2, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Xiaorong Luo, Gaoqiang Deng, Kun Zhou, Qing Liu, Linhua Huang, Tao Sun, Bo Zhang
  • Patent number: 10332828
    Abstract: Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 25, 2019
    Assignees: AGILE POWER SWITCH 3D—INTEGRATION APSI3D, IRT SAINT EXUPERY (AESE)
    Inventors: Jacques Pierre Henri Favre, Jean-Michel Francis Reynes, Raphaël Riva, Bernard José Charles Du Trieu De Terdonck
  • Patent number: 10276654
    Abstract: A semiconductor device including a substrate, an active portion and a well region both formed in the substrate on a first surface side thereof, and a low-resistivity layer formed in the substrate on a second surface side thereof. A first parallel pn structure is formed in the substrate between the active portion and the low-resistivity layer, the first parallel pn structure having a first region and a second region that are repeatedly alternated at a first repetition pitch. A second parallel pn structure is formed in the substrate between the well region and the low-resistivity layer, the second parallel pn structure having a third region and a fourth region that are repeatedly alternated at a second repetition pitch that is smaller than the first repetition pitch, the well region and the second parallel pn structure being isolated from each other.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Toshiaki Sakata
  • Patent number: 10262988
    Abstract: An electrostatic discharge protection device and a method of making the same. The device includes a device area located on a semiconductor substrate. The device also includes an array of coextensive, laterally spaced fingers located within the device area. Each finger includes an elongate source and an elongate drain separated by an elongate gate. The fingers are electrically connected in parallel for conducting an electrostatic discharge current during an electrostatic discharge event. The device further includes a plurality of body contact regions. A layout of the body contact regions is graded such that a greater number of the body contact regions, larger body contact regions, or both are located towards a periphery of the device area than towards a central part of the device area. The layout of the body contact regions may encourage triggering of the electrostatic discharge protection device within the central part of the device area.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: April 16, 2019
    Assignee: Nexperia B.V.
    Inventors: Gijs Jan De Raad, Suzana Domingues, Harrie Martinus Maria Horstink
  • Patent number: 10236342
    Abstract: An electronic device can include a termination structure that includes a substrate, a semiconductor layer, and a first trench. The substrate includes a semiconductor material of a first conductivity type. The semiconductor layer has a second conductivity type opposite the first conductivity type and overlies the substrate and has a primary surface. The first trench extends through a majority of a thickness of the semiconductor layer. In an embodiment, a body extension region of the second conductivity type is adjacent to the primary surface and spaced apart from the first trench. In another embodiment, a doped region of the first conductivity type is adjacent to the primary surface and abuts the first trench. In a further embodiment, the termination structure can include a second trench extending through a majority of the thickness of the semiconductor layer and a doped region is spaced apart from the first and second trenches.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 19, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gary H. Loechelt
  • Patent number: 10236352
    Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having a first side; forming a trench in the semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to the first side of the semiconductor substrate; forming an insulation structure including at least a first insulation layer and a second insulation layer on the sidewall and the bottom of the trench; forming a lower conductive structure in the lower portion of the trench; removing the second insulation layer in an upper portion of the trench while leaving the second insulation layer at least partially in a lower portion of the trench; and forming an upper conductive structure in the upper portion of the trench.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Robert Haase, Martin Vielemeyer
  • Patent number: 10236374
    Abstract: In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p? type drift layer comprised of the area in which the p type impurity is introduced, as well as an n? type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Kinya Ohtani, Yasuhiro Nishimura
  • Patent number: 10224424
    Abstract: A semiconductor module comprises a semiconductor chip comprising a semiconductor switch having a collector, emitter and gate, a collector terminal connected to the collector, gate terminal connected to the gate, an emitter terminal connected to the emitter via an emitter conductor path having an emitter inductance, an auxiliary emitter terminal connected to the emitter, a first conductor path connected to the emitter, and a second conductor path connected to the emitter having a different mutually inductive coupling with the emitter conductor path as the first conductor path. The first conductor path and the second conductor path are connectable to the auxiliary emitter terminal and/or the first conductor path is connected to the auxiliary emitter terminal and the second conductor path is connected to a second auxiliary emitter terminal.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: March 5, 2019
    Assignee: ABB Schweiz AG
    Inventors: Samuel Hartmann, Didier Cottet, Slavo Kicin
  • Patent number: 10217856
    Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 26, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Toshio Nakajima
  • Patent number: 10217636
    Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Victorina Poenariu, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Gerald Reinwald, Roland Rupp, Gerald Unegg
  • Patent number: 10186575
    Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: January 22, 2019
    Assignees: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuyuki Kawada, Shiyang Ji, Ryoji Kosugi, Hidenori Koketsu, Kazuhiro Mochizuki
  • Patent number: 10177045
    Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 8, 2019
    Assignee: Newport Fab, LLC
    Inventors: Edward J. Preisler, Marco Racanelli, Paul D. Hurwitz
  • Patent number: RE47854
    Abstract: The semiconductor component has several regularly arranged active cells (1), each comprising at least one main defining line (8). A bonding wire (18, 20) is fixed to at least one bonding surface (14, 16) by bonding with a bonding tool, oscillating in a main oscillation direction (22, 24), for external electrical contacting. The bonding surfaces (14, 16) are of such a size and oriented such that the main oscillation direction (22, 24) runs at an angle (?), with a difference of 90° to the main defining line (8).
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: February 11, 2020
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer