Abstract: A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed an outer peripheral region of the semiconductor substrate.

Abstract: The present invention provides a nitride-based multi-channel switching device having a plurality of transistors. The multi-channel switching device comprises a substrate, a plurality gate structures, a plurality of source electrodes and a plurality of drain electrodes. The gate structures, source electrodes and drain electrodes are grouped to form the plurality of transistors and arranged such that each gate structure disposed between a source electrode and drain electrode. Each group of the gate structures are electrically interconnected and connected to at least one gate pad corresponding to each of the transistor. Each group of the drain electrode are electrically interconnected and connected to at least one drain pad corresponding to each of the transistor. All groups of the source electrodes are electrically interconnected and connected to at least one common source pad.

Abstract: Amplifier having electrostatic discharge and surge protection circuit. In some embodiments, a radio-frequency integrated circuit can include an amplifier, a controller configured to control operation of the amplifier, and a clamp circuit configured to provide electrostatic discharge protection and surge protection for either or both of the amplifier and the controller. The clamp circuit can include a feedback combination clamp implemented to direct a current associated with either or both of an electrostatic discharge and a surge at a first node to a second node.

Abstract: A power amplifier module includes a first power amplifier that amplifies an input signal and outputs a first transmission signal; a first switch circuit that receives input of the first transmission signal and performs switching to, of a plurality of signal paths, a signal path through which the first transmission signal passes; and a second switch circuit that receives input of the first transmission signal output from the first switch circuit through the signal path to which the first switch circuit has performed switching and switches between signal paths to an antenna terminal. The second switch circuit includes a power supply circuit that supplies a reference voltage to the first switch circuit and the second switch circuit.

Abstract: A semiconductor device (A1) includes a semiconductor layer having a first face with a trench (3) formed thereon and a second face opposite to the first face, a gate electrode (41), and a gate insulating layer (5). The semiconductor layer includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), and an n-type semiconductor region (14). The trench (3) is formed so as to penetrate through the p-type semiconductor layer (13) and to reach the second n-type semiconductor layer (12). The p-type semiconductor layer (13) includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench (3) is. Such structure allows suppressing dielectric breakdown in the gate insulating layer (5).

Abstract: An object of the present disclosure is to reduce masks and to reduce the variation in the profile of an impurity layer in a semiconductor device. A method of manufacturing a semiconductor device includes a step (b) of forming a base layer on a first main surface side of a drift layer in an active region by implanting p-type impurity ions of using the first mask, a step of (c) of forming an emitter layer on the first main surface side of the base layer by implanting n-type impurity ions using the first mask, a step (d) of forming trenches after the steps (b) and (c), a step (e) of embedding a gate electrode inside the trenches, and a step (g) of converting a part of the emitter layer into a first contact layer by implanting the p-type impurity ions having a high dosage using a second mask.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

Abstract: Power semiconductor devices, and more particularly arrangements of power semiconductor devices for improved thermal performance in high power applications are disclosed. Arrangements for multiple power semiconductor devices within a package and/or module are provided that more efficiently utilize the active device area of each power semiconductor device for a given operational specification. Certain arrangements are provided that reduce the effects of thermal crowding in order to provide increased power capability or a similar power capability in a reduced device size. Improved thermal balancing may be provided by variable spacing and/or variable offset distances between next-adjacent power semiconductor devices. In this manner, active areas of power devices and/or modules may include an increased density of power semiconductor devices within a given area while also exhibiting improved thermal profiles during operation, thereby providing improved operating characteristics and/or increased operating lifetimes.

Abstract: Provided is a novel power conversion device that enables estimation of a temperature of a power device without using a temperature sensing diode and can accurately estimate a temperature and a current of a current sensing element that observes a main current. A measurement voltage (Vref) is applied between source terminals (31s and 49s) of a main control element 31 and a current sensing element 49 in a state in which the main control element 31 and the current sensing element 49 are turned off, and a temperature of a power device 30 is estimated from a current (Ib) flowing between the source terminals (31s and 49s) of the main control element 31 and the current sensing element 49 at the time of the application by using the fact that a resistance value of a semiconductor substrate between the source terminals of the main control element 31 and the current sensing element 49 has temperature dependency.

Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.

Abstract: A semiconductor device has a super junction structure and includes a first semiconductor layer of the second conductive type disposed on the first column region and the second column region, a second semiconductor layer of the first conductive type disposed on the first semiconductor layer, a first semiconductor region of the first conductive type that is electrically connected to the first electrode and is disposed in a surface layer portion of the second semiconductor layer to be separated from the first semiconductor layer, and a second semiconductor region of the second conductive type that is electrically connected to the second electrode and that is disposed at least in the surface layer portion of the second semiconductor layer to be separated from the first semiconductor region and is electrically connected to the first semiconductor layer.

Abstract: A semiconductor arrangement includes a controllable semiconductor element having an active region, and bonding wires arranged in parallel to each other in a first horizontal direction. The active region has a first length in the first horizontal direction and a first width in a second horizontal direction perpendicular to the first horizontal direction. Each bonding wire is electrically and mechanically coupled to the controllable semiconductor element by a first number of bond connections arranged above the active region. A first bond connection of each bonding wire is arranged at a first distance from a first edge of the active region. A second bond connection of each bonding wire is arranged at a second distance from a second edge of the active region opposite the first edge. The first and second distances are both less than the first length divided by twice the first number of bond connections.

Abstract: High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of contacts in parallel. Thereby, the total gate width and the power rating of a high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

Abstract: High-voltage semiconductor devices are disclosed, each having gate, source and drain electrodes. A deep well layer is formed on a substrate and has a surface, where the substrate and the deep well layer are of first-type and second-type conductivities, respectively. A field isolation layer on the surface isolates a drain active region from a source active region. The source electrode contacts the source active region on the surface to form an ohmic contact. The drain electrode contacts the drain active region on the surface. A first well layer of the first-type conductivity is formed on the surface and between the ohmic contact and the drain active region, and at least a portion of the first well layer is under the field isolation layer. A bottom layer of the first-type conductivity is formed at a bottom of the deep well layer. The gate electrode is on the field isolation layer.

Abstract: A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

Abstract: Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.

Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Abstract: A semiconductor device comprising a semiconductor substrate including an upper surface and a lower surface wherein a donor concentration of a drift region is higher than a base doping concentration of the semiconductor substrate, entirely over the drift region in a depth direction connecting the upper surface and the lower surface is provided.

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

Abstract: The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material filling the insulation layer groove.

Abstract: A power device can be structured with a power switch having multiple arrangements such that the power switch can operate as a power switch with the capability to measure properties of the power switch. An example power device can comprise a main arrangement of transistor cells and a sensor arrangement of sensor transistor cells. The main arrangement can be structured to operate as a power switch, with the transistor cells of the main arrangement having control nodes connected in parallel to receive a common control signal. The sensor arrangement of sensor transistor cells can be structured to measure one or more parameters of the main arrangement, with the sensor transistor cells having sensor control nodes connected in parallel to receive a common sensor control signal. The sensor transistor cells can have a common transistor terminal shared with a common transistor terminal of the transistor cells of the main arrangement.

Abstract: A method for increasing a forward biased safe operating area of a device includes forming a gate; and forming a segmented source close to the gate, wherein the segmented source includes first segments associated with a first threshold voltage and second segments associated with a second threshold voltage different from the first threshold voltage, wherein at least one device characteristic associated with the first segments is different from the same device characteristic associated with the second segments.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

Abstract: The present disclosure provides a semiconductor device capable of reducing wiring resistance by using a stripe wire. The semiconductor device includes: a source pad electrode formed on a second interlayer insulating layer; a plurality of source extraction electrodes extracted in a first direction from the source pad electrode; a drain pad electrode formed on the second interlayer insulating layer; and a plurality of drain extraction electrodes extracted in the first direction from the drain pad electrode. The source pad electrode and the plurality of source extraction electrodes are electrically connected to a plurality of source wires of stripe wire covered by the second interlayer insulating layer. The drain pad electrode and the plurality of drain extraction electrodes are electrically connected to a plurality of drain wires of the stripe wire. The plurality of drain extraction electrodes are engaged with the plurality of source extraction electrodes.

Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.

Abstract: A semiconductor device and a method of making thereof are disclosed. The device includes a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type formed on the substrate. A buffer layer between the substrate and the epitaxial layer is doped with the first conductivity type at a doping level between that of the substrate and that of the epitaxial layer. A cell includes a body region doped with the second conductivity formed in the epitaxial layer. The second conductivity type is opposite the first conductivity type. The cell includes a source region doped with the first conductivity type and formed in at least the body region. The device further includes a short region doped with the second conductivity type formed in the epitaxial layer separated from source region of the cell by the body region of the cell wherein the short region is conductively coupled with the source region.

Abstract: A semiconductor device includes a first substrate having a first side for forming memory cells and an opposing second side, a doped region formed in the first side of the first substrate, a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, and a transistor formed in a first side of a second substrate and coupled to the first connection structure. The first VIA extends from the second side of the first substrate to the doped region. The memory cells include a plurality of word lines formed over the first side of the first substrate, a plurality of insulating layers disposed between the plurality of word lines, and a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the base substrate includes a semiconductor body that can be doped, and a first conductive layer and a second conductive layer that are on the semiconductor body; the first transistor includes a first doped region in contact with the first electrode of the first transistor, and a second doped region in contact with a second electrode of the first transistor, and the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have a same doping type, and are both in the semiconductor body.

Abstract: According to one embodiment, a semiconductor device has a cell region and an end region adjacent to the cell region in a first direction and surrounding the cell region. A first semiconductor layer of a first conductivity type is in the cell region and the end region. Guard rings of a second conductivity type are at a first surface in the end region. The guard rings surround the cell region. An insulating film is on the first surface in the end region. Conductive members are on the insulating film and separated from the guard rings in a second direction. A first conductive member has a cell-region-side edge above a central portion of a first guard ring. The first guard ring has an end-region-side edge below a central portion of the first conductive member.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: In the semiconductor device, a high-concentration diffusion layer and a low-concentration diffusion layer are disposed around a drain diffusion layer of an ESD protection element. The high-concentration diffusion layer is separated from a gate electrode, and a medium concentration LDD diffusion layer is disposed in a separation gap. Variations in characteristics are suppressed by reducing thermal treatment on the high-concentration diffusion layer and a medium concentration diffusion layer.

Abstract: An integrated circuit includes; a substrate including a single active region, a first active resistor formed on the substrate, and a transistor including a first junction area in the single active region. The first active resistor and the transistor are electrically connected through the first junction area. The first active resistor is formed between a first node and a second node included in the first junction area. The first node is connected to a first contact, and the second node is connected to a second contact.

Abstract: Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.

Abstract: A semiconductor device includes: an n?-type epitaxial layer having an element main surface; a p?-type body region, an n+-type source region, and n+-type drain regions; and a gate electrode including a second opening and first openings formed in a portion separated from the second opening toward the drain regions, wherein the body region selectively has a second portion exposed to the first openings of the gate electrode, and wherein the semiconductor device further includes a p+-type body contact region formed in the portion of the body region exposed to the first openings and having an impurity concentration higher than an impurity concentration of the body region.

Abstract: The present disclosure relates to a semiconductor device structure with a serpentine conductive feature and a method for forming the semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed over the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed over the first mask layer. The first mask layer and the second mask layer are made of different materials. The semiconductor device structure further includes a conductive feature penetrating through the first mask layer and the second mask layer to connect to the conductive pad. The conductive feature has a serpentine pattern in a top view.

Abstract: Contact designs for semiconductor FET devices are provided. In one aspect, a contact structure includes: a metal line(s); a first ILD surrounding the metal line(s), wherein a top surface of the first ILD is recessed below a top surface of the metal line(s); a liner disposed on the first ILD and on portions of the metal line(s); a top contact(s) disposed over, and in direct contact with, the metal line(s), wherein an upper portion of the top contact(s) has a width W1 and a height H1, wherein a lower portion of the top contact(s) has a width W2 and a height H2, and wherein W1<W2 and H1>H2; and a second ILD disposed over the liner and surrounding the top contact(s). A semiconductor FET device and methods for fabrication thereof are also provided.

Abstract: A semiconductor device (300) comprising: a doped semiconductor substrate (302); an epitaxial layer (304), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region disposed on top of the epitaxial layer; and a contact diffusion (350) disposed on top of the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate.

Abstract: According to one embodiment, a semiconductor device includes first, second, third semiconductor members, a first conductive member, a connection member, and an insulating member. The first electrode includes first, second, and third electrode regions. A direction from the first toward second electrode is along a first direction. The second electrode includes fourth, fifth, and sixth electrode regions. The first semiconductor member includes first, second, third, fourth, and fifth partial regions. The second semiconductor member includes first and second semiconductor regions. The third semiconductor member includes third and fourth semiconductor regions. The third electrode is provided between the third partial region and the sixth electrode region in the first direction. The connection member is electrically connected to the first conductive member and the second electrode. The insulating member includes first, second, third, fourth, and fifth portions.

Abstract: The present disclosure provides a manufacture method of an LDMOS. The manufacture method includes: forming a drift region in a substrate; forming a gate structure on the substrate, the gate structure defining a source region and a drain region which are separated from each other, and the gate structure including a gate oxide layer and a gate conductor layer which are successively stacked on the substrate; forming a first doped region in the source region, wherein the first doped region is surrounded by the drift region; forming a first barrier layer with a first opening on the source region and in connect with sidewall of the gate structure; forming a first implantation region in the source region through self-aligned implantation on the basis of the first opening of the first barrier layer; and forming a second implantation region and a third implantation region respectively.

Abstract: A power converter includes a first substrate on which a module including a switching element is mounted, a second substrate on which a smoothing capacitor is mounted, and a terminal block connecting the first substrate and the second substrate, with the first and second substrates located to face each other. The terminal block includes a current path over which at least one of current flowing from the module to the smoothing capacitor and current flowing from the smoothing capacitor to the module flows.

Abstract: A semiconductor device includes: a first gate line and a second gate line extending only along a first direction, a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line, a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line, and first contact plugs on the first gate line. Preferably, the first direction is perpendicular to the second direction and the first gate line and the second gate line are directly connected to the fifth gate line and the sixth gate line.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a gate structure extending from a first surface into the semiconductor substrate, a plurality of needle-shaped first field plate structures extending from the first surface into the semiconductor substrate, body regions of a second conductivity type, and source regions of a first conductivity type formed between the body regions and the first surface. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.

Abstract: A semiconductor device includes an edge terminal structure portion provided between the active portion and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate, in which the edge terminal structure portion has a first high concentration region of the first conductivity type which has a donor concentration higher than a doping concentration of the bulk donor in a region between the upper surface and a lower surface of the semiconductor substrate, an upper surface of the first high concentration region is located on an upper surface side of the semiconductor substrate, and a lower surface of the first high concentration region is located on a lower surface side of the semiconductor substrate.

Abstract: Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view.

Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

Abstract: A high-definition display device is provided. A display device with low power consumption is provided. A highly reliable display device is provided. The display device includes a first transistor and a display element electrically connected to the first transistor. The first transistor includes a first oxide, a second oxide, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor and the second conductor are positioned over the first oxide to be apart from each other. The first insulator is positioned over the first conductor and the second conductor and includes an opening. The opening overlaps with a portion between the first conductor and the second conductor. The third conductor is positioned in the opening. The second insulator is positioned between the third conductor, and the first oxide, the first conductor, the second conductor, and the first insulator.

Abstract: Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a split-gate structure. For example, an Integrated Circuit (IC) may include a MOS including a body; a source; a drain; and a split-gate structure including a control gate and at least one voltage-controlled Field-Plate (FP), the control gate is between the source and the voltage-controlled FP, the voltage-controlled FP is between the control gate and the drain, the control gate configured to switch the MOS transistor between an on state and an off state according to a switching voltage; and a voltage controller configured to apply a variable control voltage to the voltage-controlled FP, the variable control voltage based on at least one control parameter, the at least one control parameter including at least one of a load current driven by the MOS transistor or a switching frequency of the switching voltage.