Plural Sections Connected In Parallel (e.g., Power Mosfet) Patents (Class 257/341)
  • Patent number: 11121211
    Abstract: A lateral superjunction includes a substrate layer, a selective epitaxy layer deposited on the substrate layer, a trench formed into the selective epitaxy layer to expose a portion of the substrate layer, a first layer of semiconductor deposited in the trench, a second layer of semiconductor deposited adjacent to the first layer, and a first end layer of semiconductor deposited adjacent to the first layer of semiconductor and a second end layer of semiconductor deposited adjacent to the second layer of semiconductor.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 14, 2021
    Assignee: The Texas A&M University System
    Inventors: Michael Everett Babb, Harlan Rusty Harris
  • Patent number: 11101372
    Abstract: Power semiconductor devices can often be expensive to produce and/or expensive to operate (i.e. inefficient). The present structure seeks to overcome these problems by providing a double-sided vertical power transistor structure that poses a unipolar path and a second parallel bipolar path.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: August 24, 2021
    Inventor: John Wood
  • Patent number: 11094779
    Abstract: An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 17, 2021
    Assignee: Infineon Technologies AG
    Inventors: Philip Christoph Brandt, Andre Rainer Stegner, Francisco Javier Santos Rodriguez, Frank Dieter Pfirsch, Hans-Joachim Schulze, Manfred Pfaffenlehner, Thomas Auer
  • Patent number: 11075264
    Abstract: Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/?1.5° of a crystallographic axis of the silicon carbide material forming the drift region.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 27, 2021
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Alexander V. Suvorov, Vipindas Pala, Daniel J. Lichtenwalner, Qingchun Zhang
  • Patent number: 11070127
    Abstract: A semiconductor device that compensates for imbalance between a plurality of semiconductor elements connected in parallel by negative feedback to achieve current balance utilizing reversed temperature characteristics without providing any dedicated element just for cancelling temperature characteristics. A gate driving circuit turns ON a power semiconductor element by applying a voltage elevated by a charge pump (CP) circuit to a gate through a resistor connected between the CP circuit and the gate. The power semiconductor element is turned OFF by control circuit that gives a control signal to turn ON a MOS switch in the gate driving circuit and discharges the gate through a diode.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: July 20, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Morio Iwamizu
  • Patent number: 11056581
    Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 6, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna, Meng-Chia Lee, Ralph N. Wall
  • Patent number: 10998398
    Abstract: A semiconductor device includes a plurality of broad buffer layers provided in a drift layer. Each of the plurality of the broad buffer layers has an impurity concentration exceeding that of a portion of the drift layer excluding the broad buffer layers, and has a mountain-shaped impurity concentration distribution in which a local maximum value is less than the impurity concentration of an anode layer and a cathode layer. The plurality of broad buffer layers are disposed at different depths from a first main surface of the drift layer, respectively, the number of broad buffer layers close to the first main surface from the intermediate position of the drift layer is at least one, and number of broad buffer layers close to a second main surface of the drift layer from the intermediate position of the drift layer is at least two. The broad buffer layer includes a hydrogen-related donor.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: May 4, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Michio Nemoto, Takashi Yoshimura
  • Patent number: 10991812
    Abstract: Disclosed is a transistor device. The transistor device includes: in a semiconductor body, a drift region, a body region adjoining the drift region, and a source region separated from the drift region by the body region; a gate electrode dielectrically insulated from the body region by a gate dielectric; a source electrode electrically connected to the source region; at least one field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a rectifier element coupled between the source electrode and the field electrode. The field electrode and the field electrode dielectric are arranged in a first trench that extends from a first surface of the semiconductor body into the semiconductor body. The rectifier element is integrated in the first trench in a rectifier region that is adjacent at least one of the source region and the body region.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 27, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Robert Haase, Gerhard Noebauer, Martin Poelzl
  • Patent number: 10978387
    Abstract: A semiconductor device includes: first, second, and third tiers formed on a substrate, wherein the first tier is formed over the substrate, the second tier is formed over the first tier, and the third tier is formed over the second tier, wherein the second tier comprises a first interconnection line that is configured to transmit a signal, and wherein a portion of the first tier disposed directly under the first interconnection line of the second tier lacks any interconnection lines and a portion of the third tier disposed directly above the first interconnection line of the second tier lacks any interconnection lines.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Cheng, Tien-Chien Huang
  • Patent number: 10965281
    Abstract: An electronic circuit provided with a III/V semiconductor domain, and a method of operating such a circuit is presented. In particular, the present application relates to electronic circuit based on a Gallium Nitride (GaN) semiconductor. GaN components must be controlled in a way that ensures proper operation over a wide variation of GaN parameters. There is a circuit comprising a first domain coupled to a second domain, the first domain being based on a III/V semiconductor; wherein the first domain comprises a first component and a second component. The second component being representative of an electrical characteristic of the first component. The second domain contains a sensor adapted to sense an electrical quantity of the second component and an input generator coupled to the sensor. The input generator is adapted to provide at least one input, based on the electrical quantity, to the first domain.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 30, 2021
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Christoph Nagl, Nebojsa Jelaca, Horst Knoedgen
  • Patent number: 10957792
    Abstract: A semiconductor device includes a body region of a second conductivity type, a body contact region of the second conductivity type formed in the body region and having a higher average doping concentration than the body region, a source region of a first conductivity type opposite the second conductivity type formed in the body region adjacent the body contact region, a drift zone of the first conductivity type spaced apart from the source region by a section of the body region which forms a channel region of the semiconductor device, and a gate electrode configured to control the channel region. The body contact region extends under a majority of the source region in a direction towards the channel region and has a doping concentration of at least 1e18 cm?3 under the majority of the source region. Additional semiconductor device embodiments and methods of manufacture are described.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Chi Dong Nguyen, Andreas Rupp
  • Patent number: 10957788
    Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Hölzl, Henning Kraack, Gabor Mezoesi, Hans-Joachim Schulze, Waqas Mumtaz Syed
  • Patent number: 10930775
    Abstract: A silicon carbide semiconductor device has a rectangle-shaped active region in which a main current flows, and a termination region surrounding the active region in a plan view. The device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type on the front surface of the substrate, a second semiconductor layer of a second conductivity type, at a surface at the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer, the second semiconductor region disposed from a periphery of the active region to reach the termination region, and extending along each of directions of four sides of the active region. At the four sides of the active region, a cross-sectional structure of each layer and each region of the device is identical to one another.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Hoshi, Yuichi Hashizume, Keishirou Kumada
  • Patent number: 10903341
    Abstract: A method for manufacturing a MOSFET semiconductor device includes providing a wafer including a semiconductor body having a first side, a first semiconductor region adjacent to the first side, a second semiconductor region adjacent to the first side and forming a first pn-junction with the first semiconductor region, and a third semiconductor region adjacent to the first side and forming a second pn-junction with the second semiconductor region, a first dielectric layer arranged on the first side, a gate electrode embedded in the first dielectric layer, and a second dielectric layer arranged on the first dielectric layer. Next to the gate electrode, a trench is formed through the first dielectric layer and the second dielectric layer. At a side wall of the trench, a dielectric spacer is formed. The trench is extended into the semiconductor body to form a contact trench.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Riegler, Wolfgang Jantscher, Manfred Pippan, Maik Stegemann
  • Patent number: 10903449
    Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: January 26, 2021
    Assignee: Japan Display Inc.
    Inventor: Akinori Kamiya
  • Patent number: 10886372
    Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery below and horizontally overlapping a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 5, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
  • Patent number: 10879388
    Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device includes a stop layer that is disposed at least in part laterally between the pits. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts, wherein the ohmic metal contacts at least parts of the stop layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 29, 2020
    Assignees: Purdue Research Foundation, GLOBAL POWER TECHNOLOGIES GROUP
    Inventor: James Albert Cooper, Jr.
  • Patent number: 10868113
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 15, 2020
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. Yedinak, Ashok Challa, Dean E. Probst, Daniel Kinzer
  • Patent number: 10868123
    Abstract: The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n? type drift region and not penetrating a SiC substrate; an n+ type side surface diffusion region formed on each side surface of the first trench; an n+ type bottom diffusion region formed under the n? type drift region and in contact with the n+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n? type drift region at regular spacings of 0.4 ?m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hajime Akiyama, Manabu Yoshino
  • Patent number: 10861844
    Abstract: An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, James P. Di Sarro
  • Patent number: 10847428
    Abstract: A four-terminal switch, and a switching lattice comprising four-terminal switches. The four-terminal switch operates and is fabricated according to the principles of complementary metal oxide semiconductor (CMOS) technology. The four-terminal switch includes a bulk layer; a single transistor channel located at a surface of the bulk layer; and four diffusion regions positioned around the single transistor channel. The single transistor channel is a single H shaped transistor channel and the four diffusion regions are positioned around the single H shaped transistor channel.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 24, 2020
    Assignee: ISTANBUL TEKNIK UNIVERSITESI
    Inventors: Mustafa Altun, Serzat Safaltin, Ismail Cevik
  • Patent number: 10840365
    Abstract: It is a purpose of the present invention to provide an insulated gate bipolar transistor device or the like that exhibits high performance and that is suitable for mass production. The insulated bipolar transistor device includes multiple trench structures including at least a trench gate, a first dummy trench, and a second dummy trench. The first dummy trench and the second dummy trench are configured as adjacent trenches. The trench gate is connected to a gate electrode layer. The first dummy trench and the second dummy trench are connected to an emitter electrode layer, and are not connected to the gate electrode layer. A first conductive source layer is also formed between the first dummy trench and the second dummy trench.
    Type: Grant
    Filed: December 9, 2017
    Date of Patent: November 17, 2020
    Assignees: Kyushu Institute of Technology, Mitsubishi Electric Corporation, Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Katsumi Satoh, Tomoko Matsudai
  • Patent number: 10797182
    Abstract: A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mihir Mudholkar, Mohammed T. Quddus, Ikhoon Shin, Scott M. Donaldson
  • Patent number: 10784340
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate structure, a gate structure, a drift region, a drain region in the substrate structure, two isolation structures at opposite sides of the drift region, wherein the drift region has a first width, the isolation structure has a second width, a ratio of the first width to the second width is in a range from 1 to 4. The semiconductor device further includes a super-junction doped structure in the drift region and including a plurality of first-conductive-type doped sub-regions and a plurality of second-conductive-type doped sub-regions which are alternately disposed. Widths of the plurality of first-conductive-type doped sub-regions decrease from the gate structure to the drain region, and widths of the plurality of second-conductive-type doped sub-regions also decrease from the gate structure to the drain region.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 22, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: MD Imran Siddiqui, Po-An Chen
  • Patent number: 10770380
    Abstract: A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 8, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Akihiro Kimura, Takeshi Sunaga, Shouji Yasunaga, Akihiro Koga
  • Patent number: 10770583
    Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: September 8, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kengo Omori
  • Patent number: 10753964
    Abstract: An integrated circuit device for controlling and sensing electrical current is provided. The integrated circuit device comprises a main transistor device, configured for controlling a main current, and a plurality of sensing transistor devices, configured for controlling a combined sensing current. The main transistor device and the plurality of sensing transistor devices are connected to a common gate node. The on-state resistance of the main transistor device is lower than a combined on-state resistance of the plurality of sensing transistor devices. The sensing transistor devices are distributed throughout at least a section of the integrated circuit to reduce an influence of at least one local property of the integrated circuit device on the combined sensing current.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 25, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Philippe Deval
  • Patent number: 10746890
    Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Furen Lin, Frank Baiocchi, Haian Lin, Yunlong Liu, Lark Liu, Wei Song, ZiQiang Zhao
  • Patent number: 10727326
    Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Meng-Chia Lee, Ralph N. Wall, Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna
  • Patent number: 10707312
    Abstract: According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate, a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies, a gate adjacent to the base layer with a gate insulating film therebetween, a source layer connected to the base layer, and a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 7, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Matsuba, Hung Hung, Tatsuya Nishiwaki, Kikuo Aida, Kohei Oasa
  • Patent number: 10692998
    Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 23, 2020
    Assignee: Cree, Inc.
    Inventors: Khaled Fayed, Simon Wood
  • Patent number: 10679984
    Abstract: A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes: a unipolar component at least including an epitaxial layer; a transition layer connected to the epitaxial layer; and a bypass component connected to the transition layer; the unipolar component and the bypass component are connected in parallel and the transition layer is configured between the unipolar component and the bypass component.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Hiroshi Shikauchi, Satoru Washiya, Yuki Tanaka, Ning Wei
  • Patent number: 10658497
    Abstract: A method for forming semiconductor device includes providing a semiconductor substrate having an initial surface oxygen concentration in a surface region of less than 6×1017 cm?3, forming an epitaxial layer on a first side of the semiconductor substrate, and implanting dopants into the epitaxial layer. An optional thermal anneal is carried out prior to forming the epitaxial layer and/or a thermal treatment is carried out after implanting dopants.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 19, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Hölzl, Henning Kraack, Gabor Mezoesi, Hans-Joachim Schulze, Waqas Mumtaz Syed
  • Patent number: 10651124
    Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 12, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Yenting Wen, George Chang
  • Patent number: 10629725
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoyuki Ohse
  • Patent number: 10615273
    Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 7, 2020
    Assignee: Cree, Inc.
    Inventors: Yueying Liu, Saptharishi Sriram, Scott Sheppard
  • Patent number: 10593781
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 17, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Yan Chen, Yan Chun Ma, Dae-Sub Jung
  • Patent number: 10586791
    Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: March 10, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Qingjie Ma, Wei Xu, Jingwei Xu, Yang Wang
  • Patent number: 10580951
    Abstract: A package structure for a backlight module includes a flexible base film, a plurality of pads, a light-emitting component, a patterned circuit layer. The flexible base film includes a plurality of conductive vias, a first surface, and a second surface opposite to the first surface. The conductive vias connect the first surface and the second surface. In addition, a material of the flexible base film includes polyimide and white fillings. The pads are disposed on the first surface. The conductive vias are connected to the pads. The light-emitting component is disposed on the pads and electrically connected to the pads. The patterned circuit layer is disposed on the second surface and electrically connected to the conductive vias.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 3, 2020
    Assignee: UNIFLEX Technology Inc.
    Inventors: Yi-Chun Liu, Ying-Hsing Chen, Bo-Hua Chen, Yuan-Chih Lee
  • Patent number: 10580884
    Abstract: Methods and designs are provided for a vertical power semiconductor switch having an IGBT-with-built-in-diode bottom-side structure combined with a SJMOS topside structure in such a way as to provide fast switching with low switching losses (MOSFET), low on-resistance at low currents (SJMOS), low on-resistance at high currents (IGBT), and high current-density capability (IGBT).
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 3, 2020
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Zhijun Qu
  • Patent number: 10573584
    Abstract: A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 25, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Akihiro Kimura, Takeshi Sunaga, Shouji Yasunaga, Akihiro Koga
  • Patent number: 10573594
    Abstract: A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a Doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. The isolation feature can take the form of a structure that is constructed of a conductive material coupled to ground and which separates the elements of the amplifier. The isolation feature can be included in a variety of semiconductor packages, including air cavity packages and overmolded packages. Through the use of the isolation feature provided by embodiments of the present invention a significant improvement in signal isolation between amplifier elements is realized, thereby improving performance of the dual-path amplifier.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: February 25, 2020
    Assignee: NXP USA, Inc.
    Inventors: Peter H. Aaen, David J. Dougherty, Manuel F. Romero, Lakshminarayan Viswanathan
  • Patent number: 10559682
    Abstract: To provide a semiconductor apparatus including: a semiconductor substrate having a drift region; an emitter region provided inside the semiconductor substrate and above the drift region; a base region provided between the emitter and drift regions; an accumulation region provided between the base and drift regions; and a plurality of gate trench portions provided to penetrate the accumulation region from an upper surface of the semiconductor substrate. The base region has: a low concentration base region provided in contact with the gate trench portions; and a high concentration base region provided apart from the gate trench portions and having a doping concentration higher than the low concentration base region. The high concentration base region is provided below the emitter region, and a width of the high concentration base region in a depth direction of the semiconductor substrate is larger than 0.1 ?m.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: February 11, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10529799
    Abstract: A semiconductor device includes a semiconductor substrate, and a semiconductor layer disposed on the semiconductor substrate. First and second pillar layers, of respective first and second conductivity types, are alternately provided in a direction in parallel with a main surface in an active region of the semiconductor layer and in a termination region. A pillar pitch in the termination region is set to be larger than a pillar pitch in the active region. A product of a width of one of the first pillar layers and effective impurity concentration of the first conductivity of the one of the first pillar layers is equal to a product of a width of one of the second pillar layers and effective impurity concentration of the second conductivity of the one of the second pillar layers.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: January 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masayuki Furuhashi, Kohei Ebihara
  • Patent number: 10527654
    Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 7, 2020
    Assignee: Vishay SIliconix, LLC
    Inventors: M. Ayman Shibib, Wenjie Zhang
  • Patent number: 10510878
    Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chung-Yen Chien, Sheng-Wei Fu, Chung-Yeh Lee
  • Patent number: 10497777
    Abstract: A semiconductor power device includes an n-type drift layer, a plurality of first p-doped regions, a plurality of n-doped regions, a plurality of second p-doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a plurality of source contacts. Each first p-doped region includes a first p-doped portion and a plurality of first p-doped arms extending outwards from the first p-doped portion. Each n-doped region includes an n-doped portion and a plurality of n-doped arms extending outwards from the n-doped portion.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 3, 2019
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee
  • Patent number: 10490548
    Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 26, 2019
    Assignee: Power Integrations, Inc.
    Inventors: Alexey Kudymov, Jamal Ramdani
  • Patent number: RE47854
    Abstract: The semiconductor component has several regularly arranged active cells (1), each comprising at least one main defining line (8). A bonding wire (18, 20) is fixed to at least one bonding surface (14, 16) by bonding with a bonding tool, oscillating in a main oscillation direction (22, 24), for external electrical contacting. The bonding surfaces (14, 16) are of such a size and oriented such that the main oscillation direction (22, 24) runs at an angle (?), with a difference of 90° to the main defining line (8).
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: February 11, 2020
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: RE48450
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii