With Means (e.g., A Buried Channel Stop Layer) To Prevent Leakage Current Along The Interface Of The Semiconductor Layer And The Insulating Substrate Patents (Class 257/349)
  • Patent number: 7994575
    Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Larry Alan Nesbit
  • Patent number: 7977196
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7977749
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20110163382
    Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Antonio L. P. Rotondaro
  • Patent number: 7973361
    Abstract: A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: July 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshinobu Sato, Hiroyoshi Ogura, Hisao Ichijo, Teruhisa Ikuta, Toru Terashita
  • Patent number: 7964873
    Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first polysilicon member that is formed on the substrate and includes an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region; a first insulator formed on the first polysilicon member and having an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region; and a first electrode formed on the first• insulator and having an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chun-Gi You
  • Patent number: 7960791
    Abstract: Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features (e.g., strained fins, a space between two fins that is approximately 0.5 to 3 times greater than a width of a single fin, a first dielectric layer on the inner sidewalls of each pair of fins with a different thickness and/or a different dielectric material than a second dielectric layer on the outer sidewalls of each pair of fins, etc.).
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7960792
    Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: June 14, 2011
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
  • Patent number: 7956416
    Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Eric R. Blomiley
  • Patent number: 7952151
    Abstract: A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-woo Oh, Dong-gun Park, Dong-won Kim, Sung-dae Suk
  • Patent number: 7948027
    Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: May 24, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Shing-Hwa Renn, Cheng-Chih Huang, Yung-Meng Huang
  • Patent number: 7943933
    Abstract: Disclosed herein is a TFT substrate which exhibits good characteristic properties despite the omission of the barrier metal layer to be normally interposed between the source-drain electrodes and the semiconductor layer in the TFT. The TFT substrate permits sure and direct connection with the semiconductor layer of the TFT. The thin film transistor substrate has a substrate, a semiconductor layer and source-drain electrodes. The source-drain electrodes are composed of oxygen-containing layers and thin films of pure copper or a copper alloy. The oxygen-containing layer contains oxygen such that part or all of oxygen combines with silicon in the semiconductor layer. And, the thin films of pure copper or a copper alloy connect with the semiconductor layer of the thin film transistor through the oxygen-containing layers.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: May 17, 2011
    Assignee: Kobe Steel, Ltd.
    Inventors: Aya Hino, Hiroshi Gotou
  • Patent number: 7944021
    Abstract: A semiconductor device includes an element isolation film formed on a semiconductor substrate surface of one conductivity type, a gate electrode having one pair of end portions located on a boundary between an element isolation film and an element forming region, a source region and a drain region of a reverse conductivity type arranged to sandwich a region immediately below a gate electrode, and an impurity diffusion region of the one conductivity type formed in the element forming region. The source region is separated from a region on a boundary side between the element isolation film and the element forming region in the region immediately below the gate electrode in the element forming region. In the impurity diffusion region, a portion adjacent to the region on the boundary side is arranged between the source region and the element isolation film, and is in contact with the source region and the region on the boundary side.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: May 17, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Kouji Tanaka
  • Patent number: 7939889
    Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: May 10, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Rung Hsu, Chen-Nan Yeh, Cheng-Hung Chang
  • Patent number: 7927962
    Abstract: A method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, the method comprising: (a) forming a buffer layer on a semiconductor substrate; (b) patterning the buffer layer in a first direction to form buffer layer patterns having lateral surfaces and being spaced from each other at predetermined intervals; (c) forming a semiconductor epitaxial layer on and between the buffer layer patterns; (d) forming a first trench in the semiconductor epitaxial layer in a second direction perpendicular to the first direction to expose lateral surfaces of the buffer layer patterns; (e) selectively removing the buffer layer patterns exposed by the first trench to form spaces; (f) forming buried insulation films in the spaces formed by removal of the buffer layer patterns, a portion of semiconductor epitaxial layer being disposed between the buried insulation films; (g) removing a portion of the semiconductor epitaxial layer disposed between the buried insulation films to form a sec
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: April 19, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Soo Yoo
  • Patent number: 7923782
    Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Philip J. Oldiges, Bruce B. Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen, Ying Zhang
  • Patent number: 7919813
    Abstract: Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×1013 cm?2 or more in areal density, wherein a depth from the junction position formed between the diffusion region and the semiconductor substrate to the bottom of the F-containing NiSi layer is confined within the range of 20 to 100 nm, and the concentration of F atoms at an interface between the F-containing NiSi layer and the semiconductor substrate is 8.0×1018 cm?3 or more.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: April 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakatsu Tsuchiaki
  • Patent number: 7915657
    Abstract: Disclosed herein is a semiconductor integrated circuit including: a memory circuit section used for storing data; and a non-memory circuit section which is provided to serve as a section other than the memory circuit section and used for storing no data, wherein the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the non-memory circuit section is lower than the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the memory circuit section.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: March 29, 2011
    Assignee: Sony Corporation
    Inventors: Nobukazu Mikami, Hiroki Usui, Takuya Nakauchi
  • Patent number: 7906813
    Abstract: A semiconductor device, includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; a first circuit block formed on the semiconductor layer; and a second and a third circuit blocks formed on the semiconductor substrate, isolated from each other by the first circuit block.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: March 15, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7872308
    Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the s
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: January 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
  • Patent number: 7868396
    Abstract: A power semiconductor component includes a drift zone in a semiconductor body, a component junction and a compensation zone. The component junction is disposed between the drift zone and a further component zone, which is configured such that when a blocking voltage is applied to the component junction, a space charge zone forms extending generally in a first direction in the drift zone. The compensation zone is disposed adjacent to the drift zone in a second direction and includes at least one high-dielectric material having a temperature-dependent dielectric constant. The temperature dependence of the compensation zone varies in the second direction.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: January 11, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Rueb, Franz Hirler
  • Patent number: 7859064
    Abstract: A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: December 28, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-woo Oh, Dong-gun Park, Dong-won Kim, Sung-dae Suk
  • Patent number: 7855427
    Abstract: A semiconductor layer provided on a BOX (buried oxide) layer includes a first P-type region, an N+-type region, and an N?-type region which together form a diode. A plurality of second P-type regions are provided on a bottom part of the semiconductor layer. A plurality of insulating oxide films are interposed between the plurality of second P-type regions. When the diode is in a reverse-biased state, the second P-type region directly below the N+-type region is approximately the same in potential as the N+-type region. The second P-type region will be lower in potential relative to this second P-type region directly below the N+-type region, as the second P-type region gets nearer to the first P-type region. Electric field concentration can thus be relaxed at an interface between the semiconductor layer and the BOX layer, whereby improvement in breakdown voltage of the diode is realized.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: December 21, 2010
    Assignee: Mitsubushi Denki Kabushiki Kaisha
    Inventor: Tomohide Terashima
  • Patent number: 7855416
    Abstract: Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of ?4 to ?3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: December 21, 2010
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventors: Hidehito Kitakado, Masahiko Hayakawa, Shunpei Yamazaki, Taketomi Asami
  • Patent number: 7855417
    Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: December 21, 2010
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
  • Patent number: 7851285
    Abstract: A method for fabricating a non-volatile memory device includes forming a charge tunneling layer composed of a hafnium silicate (HfSixOyNz) layer on a semiconductor substrate. A charge trapping layer composed of a hafnium oxide nitride (HfOxNy) layer is formed on the charge tunneling layer. A charge blocking layer composed of a hafnium oxide layer is formed on the charge trapping layer. A gate layer is formed on the charge blocking layer. A non-volatile memory device fabricated by the method is also disclosed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: December 14, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang Soo Park
  • Patent number: 7851860
    Abstract: An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: December 14, 2010
    Assignee: Honeywell International Inc.
    Inventors: Cheisan J. Yue, James D. Seefeldt
  • Patent number: 7821062
    Abstract: A field effect transistor is provided having a source region, a drain region formed in a first well region, and a channel region. The first well region is doped with doping atoms of a first conductivity type. At least a part of the channel region which extends into the first well region is doped with doping atoms of a second conductivity type, the second conductivity type being a different conductivity type than the first conductivity type.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: October 26, 2010
    Assignee: Infineon Technologies AG
    Inventor: Harald Gossner
  • Patent number: 7821066
    Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: October 26, 2010
    Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
  • Patent number: 7816735
    Abstract: Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: October 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Yong-Hoon Son, Si-Young Choi, Jong-Wook Lee, Byeong-Chan Lee, InSoo Jung
  • Patent number: 7816242
    Abstract: A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the two adjacent faces being larger than that of the insulator layer in a region other than the vicinity of the boundary line, and a band of conductor layer formed facing a middle portion of the plate-like semiconductor layer via the insulator layer.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: October 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mizuki Ono
  • Patent number: 7816664
    Abstract: A high-quality, substantially relaxed SiGe-on-insulator substrate material which may be used as a template for strained Si is described. The substantially relaxed SiGe-on-insulator substrate includes a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially relaxed SiGe layer present atop the insulating region. The insulating region includes an upper region that is comprised of a thermal oxide and the substantially relaxed SiGe layer has a thickness of about 2000 nm or less.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 7811873
    Abstract: A method for fabricating MOS-FET using a SOI substrate includes a process of ion implantation of an impurity into a channel region in a SOI layer; and a process of channel-annealing in a non-oxidized atmosphere. In the ion implantation process, a concentration peak of the impurity is made to exist in the SOI layer. Moreover in the channel-annealing process, the impurity is distributed with a high concentration in the vicinity of the surface of the SOI layer under the following condition with the anneal temperature as T (K) and annealing time as t (minutes): 506×1000/T?490<t<400×1000/T?386.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: October 12, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Marie Mochizuki
  • Patent number: 7803670
    Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: September 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ted R. White, Leo Mathew, Bich-Yen Nguyen, Zhonghai Shi, Voon-Yew Thean, Mariam G. Sadaka
  • Patent number: 7800165
    Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hiroyuki Ito, Bunji Mizuno
  • Patent number: 7795679
    Abstract: Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: September 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ethan H. Cannon, Fen Chen
  • Patent number: 7795681
    Abstract: A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET may be drain-centric, with the source region and an optional dielectric-filled trench surrounding the drain region.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: September 14, 2010
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 7781302
    Abstract: Methods of fabricating a semiconductor device include forming a mask pattern on a semiconductor substrate and which exposes defined regions of the semiconductor substrate. Oxygen ions are implanted into the defined regions of the semiconductor substrate using the mask pattern as an ion implantation mask. The oxygen ion implanted regions of the semiconductor substrate are annealed at one or more temperatures in a range that is sufficiently high to form silicon oxide substantially throughout the oxygen ion implanted regions by reacting the implanted oxygen ions with silicon in the oxygen ion implanted regions, and that is sufficiently low to substantially prevent oxidation of the semiconductor substrate adjacent to the oxygen ion implanted regions.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Won Cha, Dae-Lok Bae
  • Patent number: 7781838
    Abstract: An integrated circuit including a floating body transistor and method. One embodiment provides a transistor including a body region formed in a first portion and a first and a second source/drain region formed in a second and a third portion. The body region is formed in a semiconductor substrate. The integrated circuit further includes a buried structure disposed at least below the body region and a first and a second insulating structure including an insulating material and being disposed at least between the body region and regions of the second and the third portion below the first and the second source drain region, wherein the first and the second insulating structure contact the buried structure.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: August 24, 2010
    Assignee: Qimonda AG
    Inventor: Dongping Wu
  • Patent number: 7772648
    Abstract: The present invention includes a silicon-on-insulator (SOI) wafer that enhances certain performance parameters by increasing silicon device layer and insulator layer thicknesses and increasing silicon handle wafer resistivity. By increasing the silicon device layer thickness, effects of the floating body problem may be significantly reduced. By increasing the insulator layer thickness and the silicon handle wafer resistivity, influences from the silicon handle wafer on devices formed using the silicon device layer may be significantly reduced. As a result, standard tools, methods, and processes may be used.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: August 10, 2010
    Assignee: RF Micro Devices, Inc.
    Inventors: Tony Ivanov, Julio Costa, Michael Carroll, Thomas Gregory McKay, Christian Rye Iversen
  • Patent number: 7772645
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 10, 2010
    Assignees: NEC Corporation, NEC LCD Technologies, Ltd.
    Inventor: Shigeru Mori
  • Publication number: 20100193840
    Abstract: A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
    Type: Application
    Filed: April 9, 2010
    Publication date: August 5, 2010
    Inventors: Brian S. Doyle, Been-Yih Jin, Jack T. Kavalieros, Suman Datta
  • Patent number: 7759736
    Abstract: A deposition oxide interface with improved oxygen bonding and a method for bonding oxygen in an oxide layer are provided. The method includes depositing an M oxide layer where M is a first element selected from a group including elements chemically defined as a solid and having an oxidation state in a range of +2 to +5, plasma oxidizing the M oxide layer at a temperature of less than 400° C. using a high density plasma source, and in response to plasma oxidizing the M oxide layer, improving M-oxygen bonding in the M oxide layer. The plasma oxidation process diffuses excited oxygen radicals into the oxide layer. The plasma oxidation is performed at specified parameters including temperature, power density, pressure, process gas composition, and process gas flow. In some aspects of the method, M is silicon, and the oxide interface is incorporated into a thin film transistor.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: July 20, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Pooran Chandra Joshi
  • Patent number: 7758760
    Abstract: A thin film transistor (TFT) array panel and method of manufacturing the same are provided. The method includes forming a semiconductor layer and an ohmic contact layer over a gate line, forming a conductive layer on the ohmic contact layer, forming a first photosensitive layer pattern on the conductive layer, etching the conductive layer using the first photosensitive layer pattern as an etching mask, etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O2) gas using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern, and etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Ha Choi, Min-Seok Oh, Hong-Kee Chin, Sang-Gab Kim, Yu-Gwang Jeong
  • Publication number: 20100148261
    Abstract: A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.
    Type: Application
    Filed: October 13, 2006
    Publication date: June 17, 2010
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Michiko Takei, Kazuhide Tomiyasu
  • Publication number: 20100140709
    Abstract: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 10, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Chandra V. Mouli
  • Patent number: 7723789
    Abstract: A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A nonvolatile memory device with nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has the capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 25, 2010
    Assignee: National Chiao Tung University
    Inventors: Horng-Chih Lin, Chun-Jung Su, Hsin-Hwei Hsu
  • Patent number: 7701010
    Abstract: In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Suk Shin
  • Publication number: 20100090282
    Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.
    Type: Application
    Filed: December 17, 2009
    Publication date: April 15, 2010
    Inventors: OSAMU OZAWA, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi
  • Patent number: RE41368
    Abstract: In an SOI (Silicon On Insulator) semiconductor device, a first semiconductor layer overlies a semiconductor substrate so as to sandwich an insulating layer, and second and third semiconductor layers with a different conductivity type from the second semiconductor layer are formed on the surface of the first semiconductor layer. At the interface between the first semiconductor layer and the insulating layer, a fourth semiconductor layer with a different conductivity type from the first semiconductor layer is formed. The fourth semiconductor layer includes an impurity of larger than 3×1012/cm2 so as not to be completely depleted even though a reverse bias voltage is applied between the second and third semiconductor layers.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Uemoto, Katsushige Yamashita, Takashi Miura