Complementary Field Effect Transistor Structures Only (i.e., Not Including Bipolar Transistors, Resistors, Or Other Components) Patents (Class 257/351)
  • Patent number: 10692799
    Abstract: An electronic device is disclosed, which includes a substrate including a first through hole; a first connecting element disposed in the first through hole; a first insulating layer disposed on the substrate and including a first via; a semiconductor layer disposed on the first insulating layer; and a first conductive layer disposed on the first insulating layer, wherein the first conductive layer includes a first conductive element extending into the first via to electrically connect the first connecting element and the semiconductor layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 23, 2020
    Assignee: InnoLux Corporation
    Inventors: Jui-Jen Yueh, Kuan-Feng Lee, Yuan-Lin Wu
  • Patent number: 10688269
    Abstract: A gas sensor for the detection of gases and vapors in air is particularly for the detection of anesthetic gases. A method for the detection and for the monitoring of such gases is also provided including detecting anesthetic gases with the gas sensor.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: June 23, 2020
    Assignee: DRÄGERWERK AG & CO. KGAA
    Inventors: Ernst-Günter Scharmer, Wolfgang Bäther, Livio Fornasiero, Christoph Marquardt, Günter Steppan
  • Patent number: 10686076
    Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate and at least one semiconductor fin. The semiconductor structure further includes a channel region within the semiconductor fin. The channel region includes a higher content of germanium than remaining portions of the semiconductor fin. The semiconductor structure also includes a gate stack in contact with the semiconductor fin. The method includes removing a dummy gate formed on at least one semiconductor fin. The removal of the dummy gate exposes a channel region of the semiconductor fin. A germanium dioxide layer is formed in contact with the channel region. A condensation process is performed after the germanium dioxide layer has been formed. The condensation process increases germanium content only in the channel region.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Patent number: 10686060
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • Patent number: 10658462
    Abstract: A semiconductor structure having electrostatic control and a low threshold voltage is provided. The structure includes an nFET containing vertically stacked and suspended Si channel material nanosheets stacked vertically above a pFET containing vertically stacked and suspended SiGe channel material nanosheets. The vertically stacked nFET and pFET include a single work function metal.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando, Alexander Reznicek
  • Patent number: 10644108
    Abstract: Embodiments of the invention are directed to a configuration of semiconductor devices having a substrate and a first feature formed on the substrate, wherein the first feature includes a first preserve region having compressive strain that extends throughout the first preserve region, and wherein the first feature further includes a cut region comprising a dielectric.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10629482
    Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer. An electrically-conducting connection is located in a first trench extending from the device layer through the buried insulator layer to a trap-rich layer such that the electrically-conducting connection is coupled with a substrate.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Patent number: 10613358
    Abstract: Methods and systems for a low-voltage integrated silicon high-speed modulator may include an optical modulator comprising first and second optical waveguides and two optical phase shifters, where each of the two optical phase shifters may comprise a p-n junction with a horizontal section and a vertical section and an optical signal is communicated to the first optical waveguide. A portion of the optical signal may then be coupled to the second optical waveguide. A phase of at least one optical signal in the waveguides may be modulated utilizing the optical phase shifters. A portion of the phase modulated optical signals may be coupled between the two waveguides, thereby generating two output signals from the modulator. A modulating signal may be applied to the phase shifters which may include a reverse bias.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 7, 2020
    Assignee: Luxtera, Inc.
    Inventors: Ali Ayazi, Kam-Yan Hon, Gianlorenzo Masini
  • Patent number: 10608014
    Abstract: A battery management chip circuit on the basis of an SOI process. The battery management chip circuit comprises a high-voltage multiplexer MUX, a voltage reference circuit, a Sigma-delta ADC (comprising an analog modulator and a digital filter), an SPI communication circuit, a function control circuit and a voltage value register. The battery management chip circuit is integrated on the basis of an SOI high-voltage process, and particularly, high-voltage MOS transistors adopted by the battery management chip circuit are high-voltage MOS device units on the basis of the SOI process. In addition, the present invention highlights the design of interface circuit-chopper circuit of the high-voltage multiplexer MUX and the Sigma-delta ADC, so as to describe the advantages such as decrease of difficulty of circuit design and reduction of layout area brought about when the present invention adopts the SOI process design and tape-out.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: March 31, 2020
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Xinhong Cheng, Xinchang Li, Zhonghao Wu, Dawei Xu, Yuehui Yu
  • Patent number: 10601337
    Abstract: A semiconductor device includes a P-type low potential region, an N-type first region, an N-type second region, an N-type third region, an annular trench, and a P-type isolation region. The N-type first region is provided on the principal surface of a P-type SOI layer provided to a P-type SOI substrate. The N-type first region has a concave portion. The N-type third region is provided inside the concave portion of the N-type first region so as to be away from the edge of the concave portion. A level-shift device is formed on the surface of the N-type third region. The P-type isolation region is a slit region extending in U-shape along the boundary between the N-type third region and the concave portion of the N-type first region.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 24, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kan Tanaka
  • Patent number: 10586852
    Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Han Lee, Myung Il Kang, Jae Hwan Lee, Sun Wook Kim, Seong Ju Kim, Sung Jin Park, Hong Seon Yang, Joo Hee Jung
  • Patent number: 10573554
    Abstract: A device structure with a backside contact includes a silicon-on-insulator substrate including a device layer, a buried insulator layer, and an electrically-conducting connection in a trench. A final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Patent number: 10566435
    Abstract: A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels, interfacial layers formed around the first channels, and dielectric material including first and second portions having respective thicknesses formed on the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels, the interfacial layers formed around the second channels, and the dielectric material formed on the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee
  • Patent number: 10566438
    Abstract: A substrate structure includes a set of nanosheet layers stacked upon a substrate. The substrate structure includes a p-channel region and an n-channel region. The substrate structure further includes divots within the p-channel region and the n-channel region. A first liner is formed within the divots of the n-channel region. The first liner is formed of a material having a positive charge. A second liner is formed within the divots of the p-channel region. The second liner is formed of a material having a negative charge. A p-type epitaxy is deposited in the p-channel region to form first air gap spacers of the divots in the p-channel region. An n-type epitaxy is deposited in the n-channel region to form second air gap spacers of the divots in the n-channel region.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita
  • Patent number: 10559607
    Abstract: A semiconductor device includes a substrate having a main surface, the main surface including a first region and a second region, and an element separation region that disposed on a boundary between the first region and the second region, a first filter disposed on the main surface in the first region, and a second filter disposed on the main surface in the second region, the first filter and the second filter overlapping each other in the element separation region in a plan view of the semiconductor device.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 11, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masao Okihara
  • Patent number: 10559623
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Patent number: 10548946
    Abstract: The inventions describe here cover therapeutic compositions, and methods of use, for neutralizing Type I interferons in a mammal. The compositions contain a soluble Orthopoxvirus IFN-binding protein that is modified to remove the cell-binding region, and that specifically binds to Type I IFNs, and a pharmaceutically acceptable carrier or excipient. Another variation of the invention entails a novel IFN-binding protein that is modified to remove the cell-binding region and the signal sequence.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 4, 2020
    Assignee: The government of the United States, as represented by the Secretary of the Army
    Inventors: Joseph Golden, Jay Hooper
  • Patent number: 10546930
    Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to a method of forming vertical channel devices. In one aspect, a method of forming vertical channel devices includes providing a semiconductor structure that includes a substrate and a plurality of vertical channel structures. The method additionally includes surrounding the vertical channel structures with respective wrap-around gates. The method additionally includes forming enlarged top portions by selectively growing a doped semiconductor material on respective top portions of at least a subset of the vertical channel structures. The method further includes forming a top electrode on each of the enlarged top portions.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: January 28, 2020
    Assignee: IMEC vzw
    Inventor: Juergen Boemmels
  • Patent number: 10546631
    Abstract: A static random access memory (SRAM) cell structure includes a first inverter. The first inverter includes a first transistor and a second transistor. The first transistor includes a first source electrode and a first drain electrode. The first source electrode is connected to a first voltage source. The first source electrode includes a first doped region and a second doped region disposed in the first doped region, and a conductivity type of the second doped region is complementary to a conductivity type of the first doped region. The first drain electrode is connected to a first storage node. The second transistor includes a second source electrode and a second drain electrode. The second source electrode is connected to a second voltage source. The second drain electrode is connected to the first storage node.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: January 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Su Xing
  • Patent number: 10535570
    Abstract: Methods for forming cointegrated III-V and Ge channels for vertical field effect transistors are described. Aspects of the invention include forming a first fin and a second fin on a substrate, wherein the first fin includes a first material including a first semiconductor material at a first concentration level, and wherein the second fin includes a second material including a second semiconductor material at a second concentration. A condensation oxidation is performed to increase the first concentration level to a targeted first final concentration level and increase the second concentration level to a targeted second final concentration level. The second fin is replaced with a third fin including a third material including a combination of a group III element with a group V element.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Patent number: 10529630
    Abstract: A substrate including an insulating layer, a semiconductor layer, and an insulating film stacked on a semiconductor substrate and having a trench filled with an element isolation portion is provided. After removal of the insulating film from a bulk region by a first dry etching, the semiconductor layer is removed from the bulk region by a second dry etching. Then, the insulating film in an SOI region and the insulating layer in the bulk region are removed. A gas containing a fluorocarbon gas is used for first dry etching. The etching thickness of the element isolation portion by a first dry etching is at least equal to the sum of the thicknesses of the insulating film just before starting the first dry etching and the semiconductor layer just before starting the first dry etching. After first dry etching and before second dry etching, oxygen plasma treatment is performed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiro Maruyama, Yoshiki Yamamoto, Toshiya Saitoh
  • Patent number: 10515951
    Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Cheng-Han Lee, Yi-Min Huang
  • Patent number: 10515905
    Abstract: A semiconductor device has a substrate with both compressive and tensile layers deposited overlying a single major surface (face) of the device. The tensile layer may be deposited directly on the substrate of the device, with the compressive layer overlying the tensile layer. A transition material may be located between the tensile layer and the compressive layer. The transition material may be a compound including the components of one or both of the tensile layer and the compressive layer. In a specific embodiment, the tensile material may be a silicon nitride, the compressive layer may be a silicon oxide, and the transition material may be a silicon oxy-nitride, which may be formed by oxidizing the surface of the tensile silicon nitride layer. By depositing both tensile and compressive layers on the same face of the device the opposite major surface (face) is free for processing.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 24, 2019
    Assignee: Raytheon Company
    Inventors: Michael J. Rondon, Andrew P. Clarke, George Grama
  • Patent number: 10497804
    Abstract: A vertical transistor structure includes a first transistor and a second transistor. The first transistor includes a first lower electrode connected to a second upper electrode of the second transistor, and a second upper electrode connected to a first lower electrode of the second transistor. The first transistor also includes a gate electrode connected to a gate electrode of the second transistor.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Park, Beom-Jin Park, Yun-Il Lee, Jung-Gun You, Dong-Hun Lee
  • Patent number: 10461187
    Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: October 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
  • Patent number: 10460944
    Abstract: Technologies for providing a semiconductor device, which can comprise a fully depleted semiconductor on insulator transistor and a method for forming the same are described. Various embodiments disclose a buried dielectric layer coupled to a semiconductor layer, and a back-gate stack is coupled to the buried dielectric layer, the back-gate stack comprising a back-gate conductor layer, a ferroelectric material layer coupled to the back-gate conductor layer, and a back-gate contact layer coupled to the ferroelectric material layer. A gate insulator can be coupled to the semiconductor layer, and a gate can be coupled to the gate insulator; the semiconductor layer can comprise a source, a drain and a channel region between the source and the drain. The negative capacitance property of the ferroelectric insulator provides back biasing of the fully depleted semiconductor on insulator transistor, including if using a relatively thick buried dielectric layer and a normal operating voltage.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shawn Fetterolf, Terry Hook
  • Patent number: 10431499
    Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guowei Xu, Hui Zang, Haiting Wang, Yue Zhong
  • Patent number: 10411137
    Abstract: Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 10, 2019
    Assignee: ABLIC Inc.
    Inventor: Tomomitsu Risaki
  • Patent number: 10381273
    Abstract: A substrate structure for a vertically stacked transistor includes a substrate having at least one fin and a cavity formed through a portion of the substrate. An inner spacer disposed in the cavity. A first epitaxy layer disposed upon the substrate, and a liner is disposed on portions of the first epitaxy layer and the inner spacer. A second epitaxy layer is disposed upon a top portion of the liner. The first epitaxy layer and the second epitaxy layer share a common U-shaped fin body formed by the inner spacer and the at least one fin.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh, Ruilong Xie
  • Patent number: 10367068
    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 30, 2019
    Assignee: STMicroelectronics SAA
    Inventors: Sotirios Athanasiou, Philippe Galy
  • Patent number: 10361202
    Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-chan Suh, Gi-gwan Park, Dong-woo Kim, Dong-suk Shin
  • Patent number: 10354927
    Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: July 16, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin, Yann Mignot
  • Patent number: 10332881
    Abstract: Integrating a gate-all-around (GAA) field-effect transistor(s) and a FinFET(s) on a common substrate of a semiconductor die is disclosed. GAA FETs and FinFETs can form integrated circuits (ICs). GAA FETs and FinFETs are integrated on a common substrate to optimize advantages of each type of FET. For example, FinFETs may be formed in the common substrate in the semiconductor die for forming circuits where reduced resistance and capacitance are important for performance, whereas GAA FETs may be formed in the common substrate in the semiconductor die for forming circuits with decreased threshold voltage to allow voltage scaling to lower supply voltages to reduce power consumption and also to reduce silicon area as a result of vertically stacked devices. This supports a designer having the freedom to separate control the channel width of the GAA FETs and FinFETs, which may be important for controlling drive strength and/or area for different circuits.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mustafa Badaroglu, Kern Rim
  • Patent number: 10325938
    Abstract: A TFT array substrate, a method for manufacturing the same, and a display device including such TFT array substrate are disclosed. The TFT array substrate includes a base substrate (100); and two thin film transistors located on the base substrate. The two thin film transistors each includes an active layer (102, 107) having a source region and a drain region, the two active layers of the two thin film transistors are superposed with each other in a direction perpendicular to the base substrate. The drain region of one of the two active layers is electrically connected to the source region of the other one of the two active layers so that the two thin film transistors are connected in series.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: June 18, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zheng Liu
  • Patent number: 10319779
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: June 11, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Patent number: 10297580
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a plurality of third transistors overlaying the second transistors; a third metal layer overlaying the plurality of third transistors; and a connective metal path between the third metal layer and at least one of the first transistors, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the first metal layer is powered by a first voltage and the second metal layer is powered by a second voltage.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: May 21, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 10297614
    Abstract: The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the gate structures. A replacement metal gate process used in the fabrication of such devices includes formation of the inner spacers following partial removal of dummy gate material. The remaining dummy gate material is then removed and replaced with gate dielectric and metal gate material.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10276453
    Abstract: Structures that include vertically-arranged field-effect transistors and methods for forming a structure that includes vertically-arranged field-effect transistors. A first field-effect transistor includes a section of a first fin, a first source/drain region, and a second source/drain region. The section of the first fin is arranged between the first source/drain region and the second source/drain region of the first field-effect transistor. A second field-effect transistor includes a second fin arranged over the section of the first fin, a first source/drain region, and a second source/drain region. A functional gate structure has an overlapping arrangement with the section of the first fin and also has an overlapping arrangement with a section of the second fin that is arranged between the first source/drain region and the second source/drain region of the second field-effect transistor.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Nan Wu
  • Patent number: 10263012
    Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: April 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki Makiyama, Yoshiki Yamamoto
  • Patent number: 10263098
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Patent number: 10224419
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Patent number: 10192819
    Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate a stacked pair of field effect transistors (FETs) (e.g., gate-all-around FETs) and metal components that enable power and/or signal connections to source/drain regions of those FETs. Specifically, the IC includes a first FET and a second FET stacked on and sharing a gate with the first FET. The metal components include an embedded contact in a source/drain region of the first FET and connected to a wire (e.g., a power or signal wire). The wire can be a front end of the line (FEOL) wire positioned laterally adjacent to the source/drain region and the embedded contact can extend laterally from the source/drain region to the FEOL wire. Alternatively, the wire can be a back end of the line (BEOL) wire and an insulated contact can extend vertically from the embedded contact through the second FET to the BEOL wire.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Lars Liebmann, Ruilong Xie
  • Patent number: 10186618
    Abstract: An object is to achieve high electrical characteristics (a high on-state current value, an excellent S value, and the like) and a highly reliable semiconductor device. A high on-state current value is achieved, whereby a further reduction in channel width (W) is achieved. A second conductive layer functioning as a gate electrode has a function of electrically surrounding side surfaces of a semiconductor film in a cross section in a channel width direction. With this structure, on-state current of a transistor can be increased. To achieve a semiconductor device with less hot-carrier degradation, the gate electrode has a tapered portion.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10186511
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Patent number: 10170487
    Abstract: A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Huang, Hong-Chen Cheng, Cheng Hung Lee, Hung-Jen Liao
  • Patent number: 10153008
    Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Sanjay Tiwari
  • Patent number: 10147651
    Abstract: A method of forming complementary vertical fins and vertical fins with uniform heights, including, forming a trench in a region of a substrate, wherein the trench extends through an upper portion of the substrate and a buried punch-through stop layer, and extends into a lower portion of the substrate, forming a reformed punch-through stop layer in a bottom portion of the trench, forming a fin formation region on the reformed punch-through stop layer, and forming a complementary vertical fin from the fin formation region and a vertical fin from the upper portion of the substrate on a first region of the substrate adjacent to the second region.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Jie Yang
  • Patent number: 10121781
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10096595
    Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juhan Kim, Mahbub Rashed, Navneet Jain, Anurag Mittal, Sangmoon Kim
  • Patent number: 10090156
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and a second stress layer in the substrate in the second region, wherein top surfaces of the first stress layer and the second stress layer are above a surface of the substrate. Further, the method includes forming a cover layer on each of the first stress layer and the second stress layer, and removing portions of the cover layer formed on adjacent side surfaces of the first stress layer and the second stress layer.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: October 2, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Lan Jin