Complementary Field Effect Transistor Structures Only (i.e., Not Including Bipolar Transistors, Resistors, Or Other Components) Patents (Class 257/351)
  • Patent number: 11121097
    Abstract: The present disclosure relates to a metal layer for an active x-ray attack prevention device for securing integrated circuits. In particular, the present disclosure relates to a structure including a semiconductor material, one or more devices on a front side of the semiconductor material, a backside patterned metal layer under the one or more devices, located and structured to protect the one or more devices from an active intrusion, and at least one contact providing an electrical connection through the semiconductor material to a front side of the backside patterned metal layer. The backside patterned metal layer is between a wafer and one of the semiconductor material and an insulator layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 14, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Sebastian T. Ventrone, Siva P. Adusumilli, John J. Ellis-Monaghan, Ajay Raman
  • Patent number: 11121138
    Abstract: A semiconductor device includes a transistor and a memory pickup cell formed over a well in a substrate. The transistor includes a first fin having a first width and two first source/drain features on the first fin. The pickup cell includes a second fin having a second width and two second source/drain features on the second fin. The well, the first fin, the second fin, and the second source/drain feature are of a first conductivity type. The first source/drain features are of a second conductivity type opposite to the first conductivity type. The second width is at least three times of the first width. The pickup cell further includes a stack of semiconductor layers over the second fin and connecting the two second source/drain features.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsun Chiu, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 11107736
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 31, 2021
    Inventors: Chun-Fai Cheng, Chang-Miao Liu, Kuan-Chung Chen
  • Patent number: 11107805
    Abstract: An integrated circuit includes a first cell and a second cell. The first cell with a first cell height along a first direction includes a first active region and a second active region that extend in a second direction different from the first direction. The first active region overlaps the second active region in a layout view. The second cell with a second cell height includes a first plurality of active regions and a second plurality of active regions. The first plurality of active regions and the second plurality of active regions extend in the second direction and the first plurality of active regions overlap the second plurality of active regions, respectively, in the layout view. The first cell abuts the second cell, and the first active region is aligned with one of the first plurality of active regions in the layout view.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Sing Li, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11094823
    Abstract: A method for inducing stress in a device channel includes forming a stress adjustment layer on a substrate, the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate. A device channel layer is formed on the stress adjustment layer. Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer. Source/drain regions are formed adjacent to the device channel layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 11088034
    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 10, 2021
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 11074985
    Abstract: A semiconductor device including at least an OTP unit cell is disclosed. The OTP unit cell includes a read select transistor, a data storage transistor serially connected to the read select transistor, and a program select transistor. The drain of the program select transistor is electrically coupled to the gate of the data storage transistor. The programming path for programming the three-transistor unit cell is different from the reading path for reading the OTP unit cell.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 27, 2021
    Assignee: HeFeChip Corporation Limited
    Inventor: Geeng-Chuan Chern
  • Patent number: 11069684
    Abstract: A semiconductor structure includes a first field-effect transistor disposed on a substrate. The first field-effect transistor includes a first metal gate, and a first source/drain region. A second field-effect transistor is vertically stacked above the first field-effect transistor. The second field-effect transistor includes a second metal gate, and a second source/drain region. The first metal gate and the second metal gate are vertically aligned and configured with an air gap disposed therebetween. The first source/drain region and the second source/drain region are vertically aligned and configured with another air gap disposed therebetween.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Chun-Chen Yeh, Dechao Guo, Alexander Reznicek
  • Patent number: 11069577
    Abstract: Methods of forming semiconductor devices include patterning a stack of layers that includes channel layers, n-type doped first sacrificial layers between the channel layers, and carbon-doped second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers and the second sacrificial layers are recessed relative to the channel layers with distinct respective etches to produce a flat, continuous, and vertical surface from sidewalls of the first sacrificial layers and respective second sacrificial layers. Inner spacers are formed in recesses formed by the recessing of the first sacrificial layers and the second sacrificial layers. The first sacrificial layers and the second sacrificial layers are etched away to leave the channel layers suspended.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 11056570
    Abstract: A substrate structure includes a set of nanosheet layers stacked upon a substrate. The substrate structure includes a p-channel region and an n-channel region. The substrate structure further includes divots within the p-channel region and the n-channel region. A first liner is formed within the divots of the n-channel region. The first liner is formed of a material having a positive charge. A second liner is formed within the divots of the p-channel region. The second liner is formed of a material having a negative charge. A p-type epitaxy is deposited in the p-channel region to form first air gap spacers of the divots in the p-channel region. An n-type epitaxy is deposited in the n-channel region to form second air gap spacers of the divots in the n-channel region.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita
  • Patent number: 11036090
    Abstract: Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate has a display region and a wiring region located on a periphery of the display region. The array substrate includes a base substrate, and a transparent conductive strip and a wire formed on the base substrate in the wiring region; the transparent conductive strip and the wire are located in different layers and are in direct contact with each other, and the wire has one or more exposure holes formed therein.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 15, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaoyuan Wang, Wu Wang, Rui Wang, Yajie Bai, Zhuo Xu
  • Patent number: 11031506
    Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first oxide; a second oxide, a first layer, and a second layer over the first oxide; an insulator over the second oxide; a first conductor over the insulator; a second conductor over the first layer; and a third conductor over the second layer. Each of the first and second layers includes a region with a thickness ranging from 0.5 nm to 3 nm. Each of the second and third conductors contains a conductive material having the physical property of extracting hydrogen.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 8, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshikazu Ohno, Daisuke Yamaguchi, Tomonori Nakayama
  • Patent number: 10998238
    Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10991722
    Abstract: One silicon MOSFET transistor, which is used as the VThreshold control, and a GaN power HEMT are integrated on a single die to enable a fully integrated depletion-mode power device. GaN area is created on a silicon substrate and GaN FETs are built in the GaN area. Outside of the GaN area, silicon transistors such as switch MOSFETs are built. Front end of line or back end of line metal connections are then made to create interconnections among the GaN FET and the silicon transistor. The short physical proximity of the silicon transistor and GaN HEMT significantly reduces the parasitic resistance and inductance between them. Thus, high speed signals are able to travel from the silicon transistor to the GaN HEMT with a higher frequency and lower distortion, without creating overshoot voltage when there is large parasitic inductance. Therefore, the cascode device can operate at a higher switching frequency.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ko-Tao Lee, Xin Zhang, Todd E. Takken
  • Patent number: 10991682
    Abstract: An electronic device is disclosed, the electronic device includes a substrate, a first auxiliary electrode formed on the substrate, an organic layer formed on the first auxiliary electrode, a first inorganic layer formed on the organic layer, a plurality of thin film transistors formed on the first inorganic layer, and a plurality of electronic units electrically connected to the plurality of thin film transistors, wherein the first auxiliary electrode is electrically connected to at least two of the plurality of electronic units.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 27, 2021
    Assignee: InnoLux Corporation
    Inventors: Jui-Jen Yueh, Kuan-Feng Lee
  • Patent number: 10991626
    Abstract: A semiconductor device includes: a substrate having a planar surface; a first gate-all-around field effect transistor (GAA-FET) provided on said substrate and comprising a first channel having an untrimmed volume of first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and a second GAA-FET provided on said substrate and comprising a second channel having a trimmed volume of second channel material which is less than said untrimmed volume of first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein said first and second GAA FETs are electrically connected as complementary FETs.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 27, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Subhadeep Kal, Anton Devilliers
  • Patent number: 10984725
    Abstract: A display panel includes a substrate and a plurality of pixel driving circuits disposed on the substrate, and the plurality of pixel driving circuits include a storage capacitor and transistors. The transistors include transistors of a first type and a second type. The transistor of the first type is a composite transistor and includes a first sub-transistor and a second sub-transistor that are connected in series. The first sub-transistor is a low-temperature polysilicon transistor, and the second sub-transistor is an oxide transistor. The transistor of the first type includes a composite active layer, a composite gate electrode, a composite source electrode, and a composite drain electrode. The composite source electrode or the composite drain electrode of the transistor of the first type is electrically connected to the storage capacitor, or the transistor of the first type is in an off state during a light-emitting phase.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: April 20, 2021
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd
    Inventors: Shui He, Kenji Sera, Shuxian Yang, Ming Yang
  • Patent number: 10971361
    Abstract: A laser annealing method is for irradiating an amorphous silicon film formed on a substrate 6 with laser beams and crystalizing the amorphous silicon film, wherein a plurality of first and second TFT formation portions 23, 24 on the substrate 6 are irradiated with laser beams at differing irradiation doses so as to crystalize the amorphous silicon film in the first TFT formation portions 23 into a polysilicon film having a crystalline state and crystalize the amorphous silicon film in the second TFT formation portions 24 into a polysilicon film having another crystalline state that is different from that of the polysilicon film in the first TFT formation portions 23.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: April 6, 2021
    Assignee: V TECHNOLOGY CO., LTD.
    Inventor: Michinobu Mizumura
  • Patent number: 10950609
    Abstract: Certain aspects of the present disclosure generally relate to a static random-access memory (SRAM) implemented using both a gate-all-around (GAA)-type transistor and a fin field-effect transistor (FinFET). For example, certain aspects are directed to an SRAM memory cell having a flip-flop (FF) having a pull-up (PU) transistor and a pull-down (PD) transistor, and a pass-gate (PG) transistor coupled between a bit line of the SRAM memory cell and the FF, a gate of the PG transistor being coupled to a word line (WL) of the SRAM memory cell. In certain aspects, at least one of the PU transistor, the PD transistor, or the PG transistor comprises a GAA transistor, and at least another one of the PU transistor, the PD transistor, or the PG transistor comprises a FinFET.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10943836
    Abstract: A complementary metal oxide semiconductor (CMOS) device that includes a gallium nitride n-type MOS and a silicon P-type MOS is disclosed. The device includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode. The device further includes a silicon/polysilicon layer formed over the gallium nitride transistor.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Valluri R. Rao, Han Wui Then
  • Patent number: 10943837
    Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 9, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10903123
    Abstract: A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Kangguo Cheng, Chen Zhang, Wenyu Xu
  • Patent number: 10896851
    Abstract: A method of fabricating a vertically stacked nanosheet semiconductor device includes epitaxially growing at least three layers each of alternating silicon and silicon germanium layers on a substrate and patterning a gate structure. The method includes performing at least three reactive ion etch processes forming recesses. The method includes forming source or drain regions in a channel formed by a shallow trench isolation layer formed in the recesses. The method includes growing a first epitaxial layer on the source or drain regions, forming at least three pFET structures. The method includes etching away a portion of each of the pFET structures and depositing a dielectric layer on each. The method includes growing a second epitaxial layer, forming at least three nFET structures. Each layer of the pFET structure and nFET structure are stacked vertically and each layer of the pFET structure and nFET structures have independent source or drain contacts.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Tenko Yamahita, Chun Wing Yeung, Chen Zhang
  • Patent number: 10892328
    Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Zhenxing Bi, Kangguo Cheng, Chi-Chun Liu
  • Patent number: 10872822
    Abstract: In a method of manufacturing a circuit including a MOSFET disposed in a MOSFET region and a negative capacitance FET (NCFET) disposed in a NCFET region, a dielectric layer is formed over a channel layer in the MOSFET region and the NCFET region. A first metallic layer is formed over the dielectric layer in the MOSFET region and the NCFET region. After the first metallic layer is formed, an annealing operation is performed only in the NCFET region. After the annealing operation, the first metallic layer is removed from the MOSFET region and the NCFET region. The annealing operation includes irradiating the first metallic layer and the dielectric layer in the NCFET region with an energy beam.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ling-Yen Yeh, Carlos H. Diaz, Wilman Tsai
  • Patent number: 10818663
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan
  • Patent number: 10811414
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate including a plurality of fins on a semiconductor substrate; forming a gate layer across the fins; forming a P-type doped epitaxial layer in the fins at both sides of the gate layer in a PMOS region of the semiconductor substrate; forming an N-region mask layer on top and sidewall surfaces of the fins in the NMOS region and covering the P-type doped epitaxial layer; forming an N-region trench; forming an N-type doped epitaxial layer by filling the N-region trench; forming an interlayer dielectric layer over the semiconductor substrate; forming a contact opening to expose the P-type doped epitaxial layer and the N-type doped epitaxial layer; and performing an N-type dopant segregated Schottky (DSS) doping process on a portion of the N-type doped epitaxial layer exposed by the contact opening.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 20, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 10811540
    Abstract: To provide a highly reliable semiconductor device that is suitable for miniaturization and higher density. A semiconductor device includes a first electrode including a protruding portion, a first insulator over the protruding portion, a second insulator covering the first electrode and the first insulator, and a second electrode over the second insulator. The second electrode includes a first region which overlaps with the first electrode with the first insulator and the second insulator provided therebetween and a second region which overlaps with the first electrode with the second insulator provided therebetween. The peripheral portion of the second electrode is provided in the first region.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 20, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Patent number: 10802566
    Abstract: A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low voltage levels, and the high-voltage PHY portion includes a driver circuit that retransmits the low-voltage data signals onto a bus at the required 3.3V level. Incoming 3.3V data signals pass through an attenuator circuit before being processed using a receiver circuit provided on the low-voltage PHY portion. In USB applications, outgoing USB High Speed data signals are generated by a driver circuit provided on a low-voltage USB PHY portion.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Synopsys, Inc.
    Inventors: Andrew Chung Chun Lam, Davit Petrosyan, Dino A. Toffolon, Morten Christiansen
  • Patent number: 10768368
    Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 8, 2020
    Assignee: Massachusetts Institute of Technology
    Inventors: Jason Scott Orcutt, Karan Kartik Mehta, Rajeev Jagga Ram, Amir Hossein Atabaki
  • Patent number: 10727255
    Abstract: A display device optimized to operate in a low frame rate mode under certain predetermined conditions is provided. To reduce pixel discharge during the low frame rate mode, the display device employees the TFTs with metal oxide semiconductor layer, the optical alignment layer with an upper portion and a lower portion having different resistivity. In addition, a passivation layer is provided between the optical alignment layer and the pixel or the common electrode for compensating the low resistivity of the lower portion of the optical alignment layer. As such, various visual defects associated with the pixel discharge can be reduced even when the display device is operating under the low frame rate mode.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 28, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Yousung Nam, Changseung Woo, Soonhwan Hong
  • Patent number: 10720528
    Abstract: A semiconductor structure is provided that includes a fin stack structure of, from bottom to top, a first semiconductor material fin portion, an insulator fin portion and a second semiconductor material fin portion. The first semiconductor material fin portion can be used as a first device region in which a first conductivity-type device (e.g., n-FET or p-FET) can be formed, while the second semiconductor material fin portion can be used as a second device region in which a second conductivity-type device (e.g., n-FET or p-FET), which is opposite the first conductivity-type device, can be formed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10707136
    Abstract: This disclosure is directed to a complementary metal oxide semiconductor (CMOS) transistor that includes a gallium nitride n-type MOS and a silicon P-type MOS. The transistor includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode; a polysilicon layer formed on the gallium nitride transistor, the polysilicon layer coplanar with a top side of the silicon 111 substrate; a first metal via disposed on the source electrode; a second metal via disposed on the gate electrode and isolated from the first metal via by a polysilicon layer; a first trench contact formed on the first metal via; and a second trench contact formed on the second metal via; the first trench contact isolated from the second trench contact by at least one replacement metal gate (RMG) polysilicon island.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Valluri R. Rao, Han Wui Then
  • Patent number: 10707866
    Abstract: A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Qingqing Liang, Ravi Pramod Kumar Vedula, George Peter Imthurn, Christopher Nelles Brindle, Sinan Goktepeli
  • Patent number: 10699911
    Abstract: Plasma processing methods that provide for conformal etching of silicon nitride while also providing selectivity to another layer are described. In one embodiment, an etch is provided that utilizes gases which include fluorine, nitrogen, and oxygen, for example a gas mixture of SF6, N2 and O2 gases. Specifically, a plasma etch utilizing SF6, N2 and O2 gases at high pressure with no bias is provided. The process accelerates silicon nitride etching by chemical reactions of [NO]x molecules from the plasma and [N] atoms from silicon nitride film. The etch provides a conformal (isotropic) etch that is selective to other materials such as silicon and silicon oxides (for example, but not limited to, silicon dioxide).
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 30, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Erdinc Karakas, Sonam D. Sherpa, Alok Ranjan
  • Patent number: 10688269
    Abstract: A gas sensor for the detection of gases and vapors in air is particularly for the detection of anesthetic gases. A method for the detection and for the monitoring of such gases is also provided including detecting anesthetic gases with the gas sensor.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: June 23, 2020
    Assignee: DRÄGERWERK AG & CO. KGAA
    Inventors: Ernst-Günter Scharmer, Wolfgang Bäther, Livio Fornasiero, Christoph Marquardt, Günter Steppan
  • Patent number: 10692799
    Abstract: An electronic device is disclosed, which includes a substrate including a first through hole; a first connecting element disposed in the first through hole; a first insulating layer disposed on the substrate and including a first via; a semiconductor layer disposed on the first insulating layer; and a first conductive layer disposed on the first insulating layer, wherein the first conductive layer includes a first conductive element extending into the first via to electrically connect the first connecting element and the semiconductor layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 23, 2020
    Assignee: InnoLux Corporation
    Inventors: Jui-Jen Yueh, Kuan-Feng Lee, Yuan-Lin Wu
  • Patent number: 10686060
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • Patent number: 10686076
    Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate and at least one semiconductor fin. The semiconductor structure further includes a channel region within the semiconductor fin. The channel region includes a higher content of germanium than remaining portions of the semiconductor fin. The semiconductor structure also includes a gate stack in contact with the semiconductor fin. The method includes removing a dummy gate formed on at least one semiconductor fin. The removal of the dummy gate exposes a channel region of the semiconductor fin. A germanium dioxide layer is formed in contact with the channel region. A condensation process is performed after the germanium dioxide layer has been formed. The condensation process increases germanium content only in the channel region.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Patent number: 10658462
    Abstract: A semiconductor structure having electrostatic control and a low threshold voltage is provided. The structure includes an nFET containing vertically stacked and suspended Si channel material nanosheets stacked vertically above a pFET containing vertically stacked and suspended SiGe channel material nanosheets. The vertically stacked nFET and pFET include a single work function metal.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando, Alexander Reznicek
  • Patent number: 10644108
    Abstract: Embodiments of the invention are directed to a configuration of semiconductor devices having a substrate and a first feature formed on the substrate, wherein the first feature includes a first preserve region having compressive strain that extends throughout the first preserve region, and wherein the first feature further includes a cut region comprising a dielectric.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10629482
    Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer. An electrically-conducting connection is located in a first trench extending from the device layer through the buried insulator layer to a trap-rich layer such that the electrically-conducting connection is coupled with a substrate.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Patent number: 10613358
    Abstract: Methods and systems for a low-voltage integrated silicon high-speed modulator may include an optical modulator comprising first and second optical waveguides and two optical phase shifters, where each of the two optical phase shifters may comprise a p-n junction with a horizontal section and a vertical section and an optical signal is communicated to the first optical waveguide. A portion of the optical signal may then be coupled to the second optical waveguide. A phase of at least one optical signal in the waveguides may be modulated utilizing the optical phase shifters. A portion of the phase modulated optical signals may be coupled between the two waveguides, thereby generating two output signals from the modulator. A modulating signal may be applied to the phase shifters which may include a reverse bias.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 7, 2020
    Assignee: Luxtera, Inc.
    Inventors: Ali Ayazi, Kam-Yan Hon, Gianlorenzo Masini
  • Patent number: 10608014
    Abstract: A battery management chip circuit on the basis of an SOI process. The battery management chip circuit comprises a high-voltage multiplexer MUX, a voltage reference circuit, a Sigma-delta ADC (comprising an analog modulator and a digital filter), an SPI communication circuit, a function control circuit and a voltage value register. The battery management chip circuit is integrated on the basis of an SOI high-voltage process, and particularly, high-voltage MOS transistors adopted by the battery management chip circuit are high-voltage MOS device units on the basis of the SOI process. In addition, the present invention highlights the design of interface circuit-chopper circuit of the high-voltage multiplexer MUX and the Sigma-delta ADC, so as to describe the advantages such as decrease of difficulty of circuit design and reduction of layout area brought about when the present invention adopts the SOI process design and tape-out.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: March 31, 2020
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Xinhong Cheng, Xinchang Li, Zhonghao Wu, Dawei Xu, Yuehui Yu
  • Patent number: 10601337
    Abstract: A semiconductor device includes a P-type low potential region, an N-type first region, an N-type second region, an N-type third region, an annular trench, and a P-type isolation region. The N-type first region is provided on the principal surface of a P-type SOI layer provided to a P-type SOI substrate. The N-type first region has a concave portion. The N-type third region is provided inside the concave portion of the N-type first region so as to be away from the edge of the concave portion. A level-shift device is formed on the surface of the N-type third region. The P-type isolation region is a slit region extending in U-shape along the boundary between the N-type third region and the concave portion of the N-type first region.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 24, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kan Tanaka
  • Patent number: 10586852
    Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Han Lee, Myung Il Kang, Jae Hwan Lee, Sun Wook Kim, Seong Ju Kim, Sung Jin Park, Hong Seon Yang, Joo Hee Jung
  • Patent number: 10573554
    Abstract: A device structure with a backside contact includes a silicon-on-insulator substrate including a device layer, a buried insulator layer, and an electrically-conducting connection in a trench. A final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Patent number: 10566435
    Abstract: A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels, interfacial layers formed around the first channels, and dielectric material including first and second portions having respective thicknesses formed on the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels, the interfacial layers formed around the second channels, and the dielectric material formed on the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee
  • Patent number: 10566438
    Abstract: A substrate structure includes a set of nanosheet layers stacked upon a substrate. The substrate structure includes a p-channel region and an n-channel region. The substrate structure further includes divots within the p-channel region and the n-channel region. A first liner is formed within the divots of the n-channel region. The first liner is formed of a material having a positive charge. A second liner is formed within the divots of the p-channel region. The second liner is formed of a material having a negative charge. A p-type epitaxy is deposited in the p-channel region to form first air gap spacers of the divots in the p-channel region. An n-type epitaxy is deposited in the n-channel region to form second air gap spacers of the divots in the n-channel region.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita
  • Patent number: 10559623
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu