Substrate Is Single Crystal Insulator (e.g., Sapphire Or Spinel) Patents (Class 257/352)
  • Patent number: 10249622
    Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Keith E. Fogel, Sivananda K. Kanakasabapathy, Alexander Reznicek
  • Patent number: 10236343
    Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dina H. Triyoso, Timothy J. McArdle, Judson R. Holt, Amy L. Child, George R. Mulfinger
  • Patent number: 10233562
    Abstract: A manufacturing method of a single crystal uses a single-crystal pull-up apparatus includes: adding the red phosphorus to the silicon melt so that a resistivity of the single crystal falls in a range from 0.7 m?·cm to 0.9 m?·cm; subjecting an evaluation silicon wafer obtained from the single crystal to a heat treatment in which the evaluation silicon wafer is heated at 1200 degrees C. for 30 seconds in a hydrogen atmosphere; and pull-up the single crystal while appropriately controlling a period for a temperature of the single crystal to be in a range of 570±70 degrees C. so that the number of pits generated on the evaluation silicon wafer becomes 0.1/cm2 or less.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: March 19, 2019
    Assignee: SUMCO TECHXIV CORPORATION
    Inventors: Yasuhito Narushima, Toshimichi Kubota, Fukuo Ogawa, Masayuki Uto
  • Patent number: 10043916
    Abstract: Embodiments of the invention disclose a thin-film transistor having a channel structure that has an increased width-length ratio and a manufacturing method thereof, a display substrate and a display device. The thin-film transistor comprises a gate, a gate insulation layer and an active layer stacked on a substrate, the active layer is formed therein with a source region, a drain region and a channel region, a surface of the active layer facing the gate insulation layer is at least partially formed with a non-planar surface in the channel region, such that the non-planar surface of the active layer has a tortuous shape in a width direction of the channel region.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: August 7, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Na Zhao, Xufei Xu, Gaofei Shi
  • Patent number: 9991392
    Abstract: To provide a novel semiconductor device which includes a transistor and a metal film containing Cu for a wiring, a signal line, or the like. The semiconductor device includes a first wiring, a second wiring, a first transistor, and a second transistor. The first wiring is electrically connected to a source or a drain of the first transistor, and the second wiring is electrically connected to a gate of the second transistor. The first wiring and the second wiring each include a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). The Cu—X alloy film in the first wiring is connected to the Cu—X alloy film in the second wiring.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: June 5, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Masami Jintyou, Takashi Hamochi, Satoshi Higano, Shunpei Yamazaki
  • Patent number: 9972644
    Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 15, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu
  • Patent number: 9941393
    Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: April 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9899448
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 20, 2018
    Assignees: LAPIS Semiconductor Co., Ltd., INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Patent number: 9859396
    Abstract: A method for forming a plurality of semiconductor devices on a plurality of semiconductor wafers includes forming an electrically conductive layer on a surface of a first semiconductor wafer so that a Schottky-contact is generated between the electrically conductive layer formed on the first semiconductor wafer and the first semiconductor wafer. The method further includes forming an electrically conductive layer on a surface of a second semiconductor wafer so that a Schottky-contact is generated between the electrically conductive layer formed on the second semiconductor wafer and the second semiconductor wafer. A material composition of the electrically conductive layers formed on the first and second semiconductor wafers are selected based on a value of the physical property of the first and second semiconductor wafers, respectively. The material composition of the electrically conductive layers formed on the first and second semiconductor wafers are different.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath
  • Patent number: 9817287
    Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: November 14, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD, BEIJING BOE DISPLAY TECHNOLOGY CO., LTD
    Inventors: Xiaowei Liu, Xi Chen, Zhenfei Cai, Yao Liu, Liangliang Li, Zongjie Guo
  • Patent number: 9735052
    Abstract: A method for fabricating a semiconductor device includes forming a dielectric layer over a substrate, forming an etch-stop-layer (ESL) over the dielectric layer, forming a first patterned hard mask (HM) defining a first trench over the ESL, forming a second trench extending through the ESL and the dielectric layer. The second trench is adjacent the first trench. The method also includes filling in the first trench and the second trench with a first material layer, extending the first trench through the ESL and the dielectric layer while the first material layer is filled in the second trench to form an extended first trench, forming a first metal line within the extended first trench, forming a capping layer over the first metal line and removing a portion of the first metal line to form a first cut by using the ESL and the first material layer as an etch mask.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Tsai, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu, Hsin-Ping Chen
  • Patent number: 9653464
    Abstract: A method for forming a semiconductor device, including forming one or more fin structures on a semiconductor substrate, where the fin structure defines source and drain regions. The method includes forming a gate stack, depositing a first contact insulator layer, and applying an etching process to portions of the first insulator layer to form a trench that extends to the source region. The method also includes depositing an epitaxial lower band gap source material into the trench and extending to the source region, depositing a second insulator layer, applying a second etching process to portions of the second insulator layer to form a trench that extends to the source and drain regions, and depositing a metalizing material over the substrate.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 9431435
    Abstract: To improve the electrical characteristics of a semiconductor device including an oxide semiconductor, and to provide a highly reliable semiconductor device with a small variation in electrical characteristics. The semiconductor device includes a first insulating film, a first barrier film over the first insulating film, a second insulating film over the first barrier film, and a first transistor including a first oxide semiconductor film over the second insulating film. The amount of hydrogen molecules released from the first insulating film at a given temperature higher than or equal to 400° C., which is measured by thermal desorption spectroscopy, is less than or equal to 130% of the amount of released hydrogen molecules at 300° C. The second insulating film includes a region containing oxygen at a higher proportion than oxygen in the stoichiometric composition.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 30, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ando, Hidekazu Miyairi, Naoto Yamade, Asako Higa, Miki Suzuki, Yoshinori Ieda, Yasutaka Suzuki, Kosei Nei, Shunpei Yamazaki
  • Patent number: 9318631
    Abstract: A method for manufacturing a photodiode including the steps of providing a substrate, solution depositing a quantum nanomaterial layer onto the substrate, the quantum nanomaterial layer including a number of quantum nanomaterials having a ligand coating, and applying a thin-film oxide layer over the quantum nanomaterial layer.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: April 19, 2016
    Assignee: The Boeing Company
    Inventors: Larken E. Euliss, G. Michael Granger, Keith J. Davis, Nicole L. Abueg, Peter D. Brewer, Brett Nosho
  • Patent number: 9196677
    Abstract: In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ming-Chyi Liu
  • Publication number: 20150145052
    Abstract: Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance.
    Type: Application
    Filed: October 22, 2014
    Publication date: May 28, 2015
    Inventors: Eric S. Shapiro, Matt Allison
  • Patent number: 9041109
    Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A channel region is epitaxially grown from a physically exposed surface of the crystalline insulator layer. The channel region has a uniform thickness that can be less than the thickness of the source region and the drain region, and is epitaxially aligned to the crystalline insulator layer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Pouya Hashemi, Ali Khakifirooz
  • Publication number: 20150123205
    Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer. A contoured channel region is epitaxially grown on the faceted crystalline dielectric material portion. The contoured channel region increases the distance that charge carriers travel relative to a separation distance between the source region and the drain region.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Pouya Hashemi, Ali Khakifirooz
  • Publication number: 20150123206
    Abstract: The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.
    Type: Application
    Filed: August 4, 2014
    Publication date: May 7, 2015
    Inventors: Cheng-Chou HUNG, Tung-Hsing LEE, Bernard Mark TENBROEK, Rong-Tang CHEN
  • Patent number: 8987822
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshikazu Kondo, Hideyuki Kishida
  • Publication number: 20150076604
    Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A channel region is epitaxially grown from a physically exposed surface of the crystalline insulator layer. The channel region has a uniform thickness that can be less than the thickness of the source region and the drain region, and is epitaxially aligned to the crystalline insulator layer.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Anirban Basu, Pouya Hashemi, Ali Khakifirooz
  • Patent number: 8975730
    Abstract: A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 10, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Didier Dutartre, Michel Marty, Sebastien Jouan
  • Patent number: 8901657
    Abstract: Embodiments include but are not limited to apparatuses and systems including an integrated capacitor. An integrated capacitor may include a substrate, a first capacitor plate having four edges, and a second capacitor plate overhanging the four edges of the first capacitor plate and disposed over the first capacitor plate such that the first capacitor plate is disposed between the second capacitor plate and the substrate.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: December 2, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Oleh Krutko, Larry Witkowski
  • Publication number: 20140312425
    Abstract: FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.
    Type: Application
    Filed: April 22, 2013
    Publication date: October 23, 2014
    Applicant: Interantional Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan
  • Patent number: 8860029
    Abstract: A photoelectric conversion element including a first gate electrode, a first gate insulating layer, a crystalline semiconductor layer, an amorphous semiconductor layer, an impurity semiconductor layer, a source electrode and a drain electrode in contact with the impurity semiconductor layer, a second gate insulating layer covering a region between the source electrode and the drain electrode, and a second gate electrode over the second gate insulating layer. In the photoelectric conversion element, a light-receiving portion is provided in the region between the source electrode and the drain electrode, the first gate electrode includes a light-shielding material and overlaps with the entire surface of the crystalline semiconductor layer and the amorphous semiconductor layer, the second gate electrode includes a light-transmitting material and overlaps with the light-receiving portion, and the first gate electrode is electrically connected to the source electrode or the drain electrode is provided.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsudoi Nagi, Koji Dairiki
  • Patent number: 8853781
    Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8836033
    Abstract: Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: September 16, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Silai Krishnaswamy, Joseph Payne, Jeffrey Hartman
  • Patent number: 8624321
    Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa, Hiromichi Godo, Hidekazu Miyairi
  • Patent number: 8581243
    Abstract: A bottom gate type thin-film transistor constituted of at least a substrate, a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode. At an interface between the gate electrode and the gate insulating layer, the interface has a difference between hill tops and dale bottoms of unevenness in the vertical direction, of 30 nm or less.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: November 12, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Takahashi, Ryo Hayashi, Masafumi Sano
  • Patent number: 8531000
    Abstract: An SOI wafer including: a supporting substrate 1; a BOX layer 2 provided above the supporting substrate 1, the BOX layer 2 being formed by a thermal oxidization; a gettering layer 3 provided immediately on the BOX layer 2 and mainly composed of a silicon which contains one or more of oxygen, carbon and nitrogen and contains at least oxygen; and an S layer 4 in which semiconductor devices are to be formed, the S layer 4 being mainly composed of a monocrystalline silicon.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: September 10, 2013
    Assignee: Panasonic Corporation
    Inventor: Kenji Yoneda
  • Patent number: 8525342
    Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: September 3, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Arvind Chandrasekaran, Brian Henderson
  • Patent number: 8519397
    Abstract: A photoelectric conversion element including a first gate electrode, a first gate insulating layer, a crystalline semiconductor layer, an amorphous semiconductor layer, an impurity semiconductor layer, a source electrode and a drain electrode in contact with the impurity semiconductor layer, a second gate insulating layer covering a region between the source electrode and the drain electrode, and a second gate electrode over the second gate insulating layer. In the photoelectric conversion element, a light-receiving portion is provided in the region between the source electrode and the drain electrode, the first gate electrode includes a light-shielding material and overlaps with the entire surface of the crystalline semiconductor layer and the amorphous semiconductor layer, the second gate electrode includes a light-transmitting material and overlaps with the light-receiving portion, and the first gate electrode is electrically connected to the source electrode or the drain electrode is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsudoi Nagi, Koji Dairiki
  • Patent number: 8513720
    Abstract: A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contact with the active MOS layer. A channel region is interposed between the S/D regions. The TFT includes a gate electrode, and a gate dielectric interposed between the channel region and the gate electrode. The active MOS layer may be ZnOx, InOx, GaOx, SnOx, or combinations of the above-mentioned materials. The active MOS layer also includes a primary dopant such as H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, or combinations of the above-mentioned dopants. The active MOS layer may also include a secondary dopant.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 20, 2013
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Gregory S. Herman, Jer-shen Maa, Kanan Puntambekar, Apostolos T. Voutsas
  • Publication number: 20130154007
    Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8466012
    Abstract: Hybrid bulk finFET and SOI finFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having SOI finFET and bulk finFET devices includes the following steps. A wafer is provided having an active layer separated from a substrate by a BOX. Portions of the active layer and BOX are removed in a second region of the wafer so as to expose the substrate. An epitaxial material is grown in the second region of the wafer templated from the substrate. Fins are etched in the active layer and in the epitaxial material using fin lithography hardmasks. Gate stacks are formed covering portions of the fins which serve as channel regions of the SOI finFET/bulk finFET devices. An epitaxial material is grown on exposed portions of the fins which serves as source and drain regions of the SOI finFET/bulk finFET devices.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20130105898
    Abstract: After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Applicant: International Business Machines Corporation
    Inventors: Geng Wang, Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi
  • Patent number: 8395158
    Abstract: The present invention relates to a semiconductor device including a thin film transistor comprising a microcrystalline semiconductor which forms a channel formation region and includes an acceptor impurity element, and to a manufacturing method thereof. A gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor layer which is formed over the gate insulating film and is formed of a microcrystalline semiconductor, a second semiconductor layer which is formed over the first semiconductor layer and includes an amorphous semiconductor, and a source region and a drain region which are formed over the second semiconductor layer are provided in the thin film transistor. A channel is formed in the first semiconductor layer when the thin film transistor is placed in an on state.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Patent number: 8390026
    Abstract: An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with the associated channel region, and the heterojunction region can lie along a surface of a semiconductor layer closer to a substrate than an opposing surface of the substrate. The electronic device can also include an n-channel transistor, and the subthreshold carrier depth of the p-channel and n-channel transistors can have approximately a same value as compared to each other. A process of forming the electronic device can include forming a compound semiconductor layer having an energy band gap greater than approximately 1.2 eV.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: March 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Ted R. White
  • Patent number: 8389995
    Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: March 5, 2013
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S.)
    Inventors: Guillaume Saint-Girons, Ludovic Largeau, Gilles Patriarche, Philippe Regreny, Guy Hollinger
  • Patent number: 8378414
    Abstract: By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 19, 2013
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Volker Dudek, Michael Graf
  • Patent number: 8373230
    Abstract: Systems and methods are disclosed for fabricating a semiconductor device, includes implanting one or more regions on a semiconductor wafer; performing a layer transfer onto a carrier; and transferring from said carrier to a target wafer.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: February 12, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Isreal Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
  • Patent number: 8362563
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshikazu Kondo, Hideyuki Kishida
  • Patent number: 8350267
    Abstract: A high-speed flat panel display has thin film transistors in a pixel array portion in which a plurality of pixels are arranged and a driving circuit portion for driving the pixels of the pixel array portion, which have different resistance values than each other or have different geometric structures than each other. The flat panel display comprises a pixel array portion where a plurality of pixels are arranged, and a driving circuit portion for driving the pixels of the pixel array portion. The thin film transistors in the pixel array portion and the driving circuit portion have different resistance values in their gate regions or drain regions than each other, or have different geometric structures than each other. One thin film transistor has a zigzag shape in its gate region or drain region or has an offset region.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: January 8, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Bon Koo, Ji-Yong Park, Sang-Il Park, Ki-Yong Lee, Ul-Ho Lee
  • Publication number: 20120205744
    Abstract: Embodiments of the invention provide SOI body-contacted transistors that can be used for high frequency analog and digital circuits. In accordance with certain embodiments of the invention, the SOI transistor gate can have an “I” shape, similar to the shape of the gate of a floating body SOI transistor. However, a body region is provided that extends perpendicular to the width direction of the gate and is contacted at an end of the extended body region. To form such a body contact structure, a source/drain implant block mask and silicide block mask are used during the formation of the source/drain regions. The source/drain implant block mask and silicide block mask can be formed on the same region, but the silicide block mask can allow for the body contact portion at the end of the extended body region to be silicided during the siliciding of the source/drain regions.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 16, 2012
    Inventors: Kenneth K. O, Chieh-Lin Wu
  • Patent number: 8241997
    Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8227866
    Abstract: A semiconductor substrate having an SOI layer is provided. Between an SOI layer and a glass substrate, a bonding layer is provided which is formed of one layer or a plurality of layers of phosphosilicate glass, borosilicate glass, and/or borophosphosilicate glass, using organosilane as one material by a thermal CVD method at a temperature of 500° C. to 800° C.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tetsuya Kakehata
  • Patent number: 8217488
    Abstract: A method for enhancing light extraction efficiency of GaN light emitting diodes is disclosed. By cutting off a portion from each end of bottom of a sapphire substrate or forming depressions on the bottom of the substrate and forming a reflector, light beams emitted to side walls of the substrate can be guided to the light emitting diodes.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: July 10, 2012
    Assignee: Walsin Lihwa Corporation
    Inventors: Shiue-Lung Chen, Jeng-Guo Feng, Jang-Ho Chen, Ching-Hwa Chang Jean
  • Patent number: 8217498
    Abstract: Methods and apparatus for producing a gallium nitride semiconductor on insulator structure include: bonding a single crystal silicon layer to a transparent substrate; and growing a single crystal gallium nitride layer on the single crystal silicon layer.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: July 10, 2012
    Assignee: Corning Incorporated
    Inventors: Rajaram Bhat, Kishor Purushottam Gadkaree, Jerome Napierala, Linda Ruth Pinckney, Chung-En Zah
  • Publication number: 20120132994
    Abstract: Embodiments of the present invention relate generally to semiconductor devices and, more particularly, to a structure for high-voltage (HV) semiconductor-on-insulator (SOI) devices and methods for their formation. In one embodiment, the invention provides a semiconductor-on-insulator (SOI) device comprising: a substrate; an insulator layer atop the substrate; a polysilicon layer atop the insulator layer; a device layer atop the polysilicon layer, the device layer comprising: a P-well; an N-well; and an undoped silicon region between the P-well and the N-well; and a trench isolation adjacent one of the P-well and the N-well and extending through the device layer and the polysilicon layer to the insulator layer.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William F. Clark, JR., Yun Shi
  • Patent number: 8138010
    Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: March 20, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Steven Radigan