Abstract: The present disclosure provides a touch-sensing electrode structure, which includes a plurality of touch-sensing electrodes. Each of the touch-sensing electrodes includes a main body and a connecting portion connected to an end of the main body; wherein the width of the connecting portion is not less than a half width of the end of the main body. The touch-sensing electrode structure also includes a plurality of signal-transmitting wires, each of which includes a head portion and a tail wire connected to the head portion. The head portions of the signal-transmitting wires is superimposed on the connecting portions and electrically connected to the connecting portions respectively. Furthermore, a method of manufacturing the above touch-sensing electrode structure is also provided.

Abstract: A silicon controlled rectifier (SCR) circuit is configured to shunt electrostatic discharge (ESD) current from a node to a reference voltage. The SCR circuit includes a first bipolar PNP transistor having a first emitter connected to the node, a first base, and a first collector. A second bipolar NPN transistor has a second collector sharing a first region with the first base, a second base sharing a second region with the first collector, and an emitter electrically connected to the reference voltage. A guard region is configured and arranged to delay triggering of the SCR circuit in response to an ESD event by impeding current flow in the second region.

Abstract: Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device.

Abstract: There is provided a solid-state image pickup device that includes a functional region provided with an organic film, and a guard ring surrounding the functional region.

Abstract: An electrostatic protection circuit includes a first transistor connected to an external terminal, a second transistor that is connected in series to the first transistor and that is in a normally OFF state. The electrostatic protection circuit includes a third transistor that is connected between a power source line and a gate of the first transistor, and a fourth transistor that is connected between the power source line and the gate of the first transistor in the opposite direction to the third transistor.

Abstract: An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer on a lower surface of the n-type drift layer. A FWD includes the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer. A p-type well is formed on the upper surface of the n-type drift layer in a wiring region and a termination region. A wiring is formed on the p-type well in the wiring region. The p-type well has a higher impurity concentration and is deeper than the p-type anode layer. The p-type well is not formed directly above the n-type cathode layer and is separate from a region directly above the n-type cathode layer.

Abstract: The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.

Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.

Abstract: A semiconductor device includes a semiconductor body including a first trench extending into the semiconductor body from a first surface and a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench. The other one of the anode region and the cathode region includes a first semiconductor region directly adjoining the one of the anode region and the cathode region from outside of the first trench, thereby constituting a pn junction. The semiconductor device further includes a conducting path through a sidewall of the first trench.

Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

Abstract: A method for preparing a non-reference transistor test structure having multiple terminals is disclosed. The method may include when an intended application of the non-reference transistor test structure is not for monitoring a plasma-involved charging, employing a protection mechanism by placing the MOSFET-based gated diode at a first metal layer, wherein the first metal layer is a lowermost metal layer, and when the intended application of the non-reference transistor test structure is for monitoring a plasma-involved charging, placing a charging monitoring antenna at a second metal layer; and employing the protection mechanism by placing a MOSFET-based gated diode at one metal layer above the second metal layer.

Abstract: A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at an etching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type.

Abstract: A semiconductor device including an electrostatic discharge (ESD) protection circuit includes an input port, a logic circuit receiving an input signal applied to the input port and generating an output signal based on the input signal, and an ESD protection circuit adjusting a level of the input signal when the level of the input signal exceeds a predetermined range.

Abstract: An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, a first N-doped section comprising a deep N-well structure, a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well. The ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure and forming a part of the second P-doped section of the thyristor structure.

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

Abstract: A display substrate includes a base substrate including a display area in which signal lines and pixels are arranged and a peripheral area surrounding the display area, pads disposed in the peripheral area and receiving an electrical signal, fan-out lines connecting the pads and the signal lines, and static electricity breakup circuits comprising a breakup line that crosses the fan-out lines, and static electricity prevention circuits respectively connected to the fan-out lines. Parts of the static electricity prevention circuits are connected to adjacent fan-out lines and are commonly connected to the one of the breakup lines through a common contact part.

Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and has a second conductive type. The source region is disposed in the doped well and has the second conductive type, wherein the source region is separated from the drain region. The doped region is disposed in the doped well between the drain region and the source region, wherein the doped region has the first conductive type and is in contact with the doped well and the source region. The guard ring is disposed in the doped well and has the first conductive type.

Abstract: In an embodiment, an electronic device comprises a shared electrical over-stress (EOS) protection circuit. The shared EOS protection circuit may be coupled between a power input terminal and ground terminal to provide an EOS current path from the power input terminal to the ground terminal, and coupled between the output terminal and the ground terminal to provide an EOS current path from the output terminal to the ground terminal. The electronic device may also include a power interruption mitigation circuit to provide power to the electronic device during interruptions or fluctuations in external power.

Abstract: A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.

Abstract: A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.

Abstract: A semiconductor device includes a first semiconductor layer; an insulation member layer formed on the first semiconductor layer; a transistor disposed in an upper portion of the insulation member layer; a first interlayer insulation film covering the transistor; a layered member including a wiring layer formed on the first interlayer insulation film and a second interlayer insulation film; and a first penetrating electrode penetrating through the insulation member layer, the first interlayer insulation film, and the layered member. The first penetrating electrode is electrically connected only to the first semiconductor layer.

Abstract: A motor control system includes an inverter and a plurality of current sensors each positioned in-line between the inverter and a phase coil of the motor. Each current sensor measures the current provided to each phase coil of the motor and provides a signal indicative of each phase current to a controller. In some embodiments, the currents sensors are provided as one or more current sense integrated circuits. A protection circuit protects the current sense integrated circuit from ground bounce by coupling a diode and an opposite facing Zener diode in series between the power supply pin and the ground pin of the integrated circuit.

Abstract: Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

Abstract: An electro-static discharge (ESD) protection device includes a first PN diode, a second PN diode and a silicon controlled rectifier (SCR). The first PN diode and the second PN diode are coupled in series between a pad and a ground voltage to provide a first discharge current path. The SCR is coupled between the pad and the ground voltage to provide a second discharge current path. The SCR has a PNPN structure.

Abstract: An ESD clamp circuit includes a power supply, a ground supply, an ESD detection transistor, a capacitor having a first terminal connected to the power supply and a second terminal connected to a gate of the ESD detection transistor, and a first resistor connected in series with the capacitor between the power and ground supplies. The ESD clamp circuit also includes a clamp transistor having a first terminal connected to the power supply and a second terminal connected to the ground terminal, an inverter having an input connected to a first terminal of the ESD detection transistor and an output connected to the gate of the clamp transistor, a feedback transistor connected across the inverter, and a second resistor having a first terminal connected to the gate of the clamp transistor and to a second terminal to the ground supply.

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

Abstract: A semiconductor device is disclosed, including a plurality of gate rings formed on a substrate and concentrically surrounding a first doped region formed in the substrate. The gate rings are equipotentially interconnected by at least a connecting structure. A second doped region is formed in the substrate, exposed from the space between adjacent gate rings. A third doped region is formed in the substrate adjacent to the outer perimeter of the outermost gate ring. The first doped region, the third doped region and the gate rings are electrically biased and the second doped regions are electrically floating.

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

Abstract: An electrostatic discharge device includes a substrate. A deep doped well of a first conductive type is disposed in the substrate. A drain doped well of the first conductive type is disposed in the substrate above the deep doped well. An inserted doping well of a second conductive type is disposed in the drain doped well, in contact with the deep doped well. A drain region of the first conductive type is in the drain doped well and above the inserted doping well. An inserted drain of the second conductive type is on the inserted doping well and surrounded by the drain region. A source doped well of the second conductive type is disposed in the substrate, abut the drain doped well. A source region is disposed in the source doped well. A gate structure is disposed on the substrate between the drain region and the source region.

Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

Abstract: An ESD protection semiconductor device includes a substrate, a first isolation structure disposed in the substrate, a gate disposed on the substrate and overlapping a portion of the first isolation structure, a source region formed in the substrate at a first side of the gate, and a drain region formed in the substrate at a second side of the gate opposite to the first side. The substrate and the drain region include a first conductivity type, the source region includes a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other.

Abstract: A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having a primary surface and having a sensor therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein. The second semiconductor layer is formed at a same side of the primary surface of the first semiconductor layer. The device further includes an insulating layer formed between the first semiconductor layer and the second semiconductor layer. The insulating layer is disposed on the primary surface of the first semiconductor layer and surrounds the circuit element, and includes a charge-attracting semiconductor pattern of the first conductivity type that is disposed near the circuit element so as to attract electrical charges generated in the insulating layer.

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region formed therein, and a plurality of insulating elements respectively formed therein. The plurality of insulating elements is respectively formed in a portion of the semiconductor layer between the first, second and third doped regions. The intrinsic region is formed at least in the semiconductor layer between one of the second and third regions and the other one of the second and third regions or between one of the second and third regions and the first region. The first doped region is formed with a first conductivity type, and the second and third doped regions are formed with a second conductivity type opposite to the first conductivity type.

Abstract: There is provided a solid-state image pickup device that includes a functional region provided with an organic film, and a guard ring surrounding the functional region

Abstract: An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region.

Abstract: A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes a first isolation layer on the first surface of the semiconductor body and a first electrostatic discharge protection structure on the first isolation layer. The first electrostatic discharge protection structure has a first terminal and a second terminal. A second isolation layer is provided on the electrostatic discharge protection structure. A gate contact area on the second isolation layer is electrically coupled to the first terminal of the first electrostatic discharge protection structure. An electric contact structure is arranged in an overlap area between the gate contact area and the semiconductor body. The electric contact structure is electrically coupled to the second terminal of the first electrostatic discharge protection structure and electrically isolated from the gate contact area.

Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate and spaced apart from the first well, a gate formed on the substrate and positioned in between the first well and the second well, a drain region formed in the first well, a source region formed in the second well, a first doped region formed in the first well and adjacent to the drain region, and a second doped region formed in the first well and spaced apart from both the first doped region and the gate. The first well, the drain region, and the source region include a first conductivity type, the second well, the first doped region and the second doped region include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A semiconductor device includes a first conductive type first main electrode region, a first conductive type drift region which makes contact with the first main electrode region, a first conductive type second main electrode region which makes contact with the drift region, a second conductive type well region which is provided in a part of a surface layer portion of the drift region and to which a reference potential is applied, and a first conductive type potential extracting region which is provided in a surface layer portion of the well region and to which the reference potential is applied. The well region serves as a base region which controls a current flowing between the potential extracting region and the drift region. Thus, it is possible to provide a novel semiconductor device which is high in reliability while the increase of the chip size can be suppressed.

Abstract: A super-junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer, a field insulator, a floating electrode layer, an isolation layer, and at least one transistor structure. The drift layer includes a plurality of n-type and p-type pillars alternately arranged in parallel to form a super-junction structure. An active region, a termination region and a transition region located therebetween are defined in the drift layer. The field insulator disposed on a surface of the drift layer covers the termination region and a portion of the transition region. The floating electrode layer disposed on the field insulator partially overlaps with the termination region. The transistor structure includes a source conductive layer extending from the active region to the transition region and superimposed on a portion of the floating electrode layer. The source conductive layer is isolated from the floating electrode layer by the isolation layer.

Abstract: The present disclosure generally relates to an apparatus for a three terminal nonvolatile memory cell. Specifically, a three terminal nonvolatile bipolar junction transistor. The bipolar junction memory device includes a collector layer, a base layer disposed on the collector layer, an emitter layer disposed on the base layer, and a conductive anodic filament extending from the collector layer to the base layer. As current is applied to the transistor and a voltage is applied between P-N junction of the collector layer and the base layer, a conductive anodic filament (CAF) forms. The CAF is non-volatile and short circuits the reverse-biased P-N junction barrier thus keeping the device in a low-resistive state. Removing the CAF switches the device back to a high resistive state. Thus, a new type of semiconductor device advantageously combines computation and memory to form a flux-linkage modulated memory cell.

Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

Abstract: An object is at least one of a longer data retention period of a memory circuit, a reduction in power consumption, a smaller circuit area, and an increase in the number of times written data can be read to one data writing operation. The memory circuit has a first field-effect transistor, a second field-effect transistor, and a rectifier element including a pair of current terminals. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of the pair of current terminals of the rectifier element is electrically connected to a source or a drain of the second field-effect transistor.

Abstract: A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a polysilicon layer over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an insulating layer over the polysilicon layer, and performing a planarizing operation to remove the insulating layer except for a portion of the insulating layer formed in the depression, thereby defining a protective island; patterning the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; and etching the polysilicon layer to remove the dummy gate structure, wherein the protective island prevents the polysilicon resistor from being removed.

Abstract: The present invention provides a display panel, a manufacturing method thereof, and a display device. The display panel is divided into display areas and non-display areas, and comprises an upper base plate and a lower base plate which is aligned with the upper base plate to form a cell, a control structure and a display structure are arranged in the display area on the lower base plate, a sensing structure is further arranged in the display area on the upper base plate and/or the lower base plate, the sensing structure and the display structure are correspondingly arranged, and a stabilizer sub-structure is arranged in the sensing structure.

Abstract: An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.