Abstract: An allowable current amount of a ballast resistance is increased without increasing the width of the ballast resistance. At least one of resistances included in a ballast resistance has a first resistance and a second resistance. The first resistance extends in a first direction (X direction in FIG. 1) in which current flows in a protection element. The second resistance element is coupled in parallel to the first resistance element and extends in the first direction. The second resistance element and the first resistance element are located on the same straight line.

Abstract: A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps.

Abstract: A flat display panel is provided. The flat display panel includes a substrate, a first driving line, a second driving line, and an ESD protection circuit. The ESD protection circuit includes a first crossing line, a second crossing line, and a first ESD protection device. The first crossing line crosses over the first driving line in a first crossing place. The second crossing line crosses over the second driving line in a second crossing place. The first ESD protection device is electrically connected to the first crossing line and to the second crossing line. Therefore, the flat display panel can avoid current leakage occurring when the first crossing place or the second crossing place is damaged.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state.

Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.

Abstract: An ESD protection device is provided, which includes a P-type doped region, an N-type doped region, a first P+ doped region, a first N+ doped region, a second N+ doped region and a third N+ doped region. The N-type doped region is located in the P-type doped region. The first P+ doped region connected to a pad is located in the N-type doped region. A part of the first N+ doped region is located in the N-type doped region and the residue part thereof is located in the P-type doped region. The second and the third N+ doped regions are located in the P-type doped region and outside the N-type doped region, and are respectively electrically connected to a first power rail and a second power rail. In addition, the second N+ doped region is located between the first and the third N+ doped regions.

Abstract: A device (10) to detect and measure static electric charge (q) on an object (100) being positioned in a distance (r.) from an input electrode (11) of the device (10) comprises at least one MOS field transistor (20). The input electrode (11) is connected with the gate electrode (21) of the MOS-FET (20) to detect said electrical charge. The MOS-FET (20) can comprise a gate oxide layer underneath the gate (21) and over the source (22) and drain (23) areas having a sufficient thickness to allow the MOS field transistor (20) to withstand several kilovolts (kV) of voltage and to avoid the loss of charges by tunnel effect due to the high potential of the gate electrode during ESD events.

Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.

Abstract: A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.

Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

Abstract: The present invention relates to a semiconductor device which includes a photoelectric conversion layer; an amplifier circuit amplifying an output current of the photoelectric conversion layer and including two thin film transistors; a first terminal supplying a high-potential power supply voltage; a second terminal supplying a low-potential power supply voltage; an electrode electrically connecting the two thin film transistors and the photoelectric conversion layer; a first wiring electrically connecting the first terminal and a first thin film transistor which is one of the two thin film transistors; and a second wiring electrically connecting the second terminal and a second thin film transistor which is the other of the two thin film transistors. In the semiconductor device, the value of voltage drop of the first wiring and the second wiring are increased by bending the first wiring and the second wiring.

Abstract: An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.

Abstract: An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

Abstract: A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.

Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

Abstract: An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

Abstract: A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.

Abstract: To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner, wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element.

Abstract: The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.

Abstract: The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.

Abstract: The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.

Abstract: A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type.

Abstract: An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

Abstract: A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.

Abstract: A touch panel including a substrate, a plurality of first sensing series, and a plurality of second sensing series is provided. The first sensing series and the second sensing series are disposed on the substrate. The first sensing series extend along a first direction and are electrically insulated from each other. Each of the first sensing series includes a plurality of first sensing pads and a plurality of first bridge portions connected between the first sensing pads. The second sensing series extend along a second direction and are electrically insulated from each other. Each of the second sensing series includes a plurality of second sensing pads and a plurality of second bridge portions connected between the second sensing pads. Each of the first bridge portions and one of the second bridge portions are intersected, and at least one of the second bridge portions has at least one electrostatic discharge tip.

Abstract: A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; a well region, a first N+ diffusion region, a first P+ diffusion region, a second N+ diffusion region, a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the well region and semiconductor substrate; a third N+ diffusion region, positioned in another side of the DTSCR and across the well region and the semiconductor substrate; a first gate, positioned above the semiconductor substrate between the first P+ diffusion region and the third P+ diffusion region, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the well region between the second N+ diffusion region and the third N+ diffusion region, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.

Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.

Abstract: In a conventional semiconductor device, protection of a to-be-protected element from a surge voltage is difficult because the to-be-protected element is turned on before a protection element due to variations in manufacturing conditions. In a semiconductor device of the present invention, a protection element and a MOS transistor have part of their structures formed under common conditions. N type diffusion layers of the protection element and the MOS transistor are formed in the same process, while the N type diffusion layer of the protection element has a larger diffusion width than the N type diffusion layer of the MOS transistor. With this structure, when a surge voltage is applied to an output terminal, the protection element is turned on before the MOS transistor, and thereby the MOS transistor is protected from an avalanche current.

Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.

Abstract: An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.

Abstract: The electronic device comprises an ESD device (20) for protection against electrostatic discharge and provided with suitable protection elements (22) in combination with an integrated circuit (10). The integrated circuit (10) is particularly a so-called bridging circuit or driver circuit for external devices such as SIM cards, memory sticks, USB busses or 12C busses. The ESD device (20) is provided with a chip scale package in that the bumps (40) can be placed on a printed circuit board directly. The integrated circuit (10) is stacked on the ESD device (20).

Abstract: A circuit with electrostatic discharge protection is described. The circuit includes an output driver transistor with an extended drain contact region. The circuit also includes a distinct device configured to provide electrostatic discharge protection for the output driver transistor. The distinct device includes an electrostatic discharge protection transistor with an extended drain region.

Abstract: An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed SCR terminals, and a second drain structure with distributed drain diffused regions and SCR terminals. An MOS gate between the centralized drain diffused region and a source diffused region is shorted to the source diffused region. A process of forming the integrated circuit having the SCRMOS transistor is also disclosed.

Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

Abstract: An integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal. The RESURF region is the same conductivity type as the drift region and is more heavily doped than the drift region. An SCRMOS transistor with a RESURF region around the drain region and SCR terminal. A process of forming an integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate. The ESD protection circuit may further comprise a first terminal to connect the isolation region to a first electrical node, and a second terminal to connect the second doped region to a second electrical node. The first electrical node may have a higher voltage level than the second electrical node, and the gate and backgate may be coupled to the second terminal.

Abstract: A liquid crystal panel comprises a temperature sensor (1) formed on a glass substrate (11). The temperature sensor (1) includes two junction structures (2) and (5). The junction structure (2) is formed such that two different semiconductor films (3) and (4) are joined together. The junction structure (5) is formed such that two different semiconductor films (6) and (7) are joined together. The liquid crystal panel outputs divided voltage between the voltage applied to the junction structure (2) and the voltage applied to the junction structure (5) as the voltage depending on the temperature of the liquid crystal panel. As the result, the liquid crystal panel comprising the temperature sensor (1) of simple structure and high performance is provided.

Abstract: The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The exemplary semiconductor chip of the present invention includes an internal circuit and a first electrode pad electrically connected to a ground bus line of the first semiconductor chip in a region where an electrode pad, which gives and receives electric signals required for an operation of the internal circuit, cannot be provided.

Abstract: A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second P+ diffusion region and the third P+ diffusion region, for use as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first N+ diffusion region and the third N+ diffusion region, for use as an N-type trigger node to receive a second trigger current or a second trigger voltage.

Abstract: The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.