Combined With Bipolar Transistor Patents (Class 257/370)
  • Patent number: 10090200
    Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P? type first epitaxial layer formed on the buried layer, a P? type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 2, 2018
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Yanjie Lian, Daping Fu, Ji-Hyoung Yoo
  • Patent number: 10090340
    Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 10079278
    Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 10074716
    Abstract: An isolation structure formed in a semiconductor substrate of a first conductivity type includes a region of a second conductivity type opposite to the first conductivity type. The region of the second conductivity type is saucer-shaped and has a floor portion substantially parallel to the top surface of the substrate and a sloped sidewall portion. The sloped sidewall portion extends downward from the top surface of the substrate at an oblique angle and merges with the floor portion. The floor portion and the sloped sidewall portion together form an isolated pocket of the substrate.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: September 11, 2018
    Assignees: SKYWORKS SOLUTIONS (HONG KONG) LIMITED, ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
    Inventors: Wai Tien Chan, Donald Ray Disney, Richard K. Williams
  • Patent number: 10074649
    Abstract: An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: September 11, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stephane Monfray, Gaspard Hiblot
  • Patent number: 10062774
    Abstract: A semiconductor device includes a plurality of gate trenches formed in a semiconductor layer; a gate electrode filled via a gate insulating film in the plurality of gate trenches; an n+-type emitter region, a p-type base region, and an n?-type drift region disposed laterally to each gate trench; a p+-type collector region on a back surface side of the semiconductor layer; a plurality of emitter trenches formed between the gate trenches adjacent to each other; a buried electrode filled via an insulating film in the plurality of emitter trenches; and a p-type floating region formed between the plurality of emitter trenches. The p-type floating region is formed deeper than the p-type base region, and includes an overlap portion. The n+-type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 28, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10043872
    Abstract: A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 7, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 9984196
    Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih Ming Yang, Yi-Kan Cheng
  • Patent number: 9972244
    Abstract: A display device includes: a plurality of light-emitting elements, each light-emitting element having a light-emitting unit and a driving circuit for driving the light-emitting unit. The driving circuit at least includes (A) a drive transistor having source/drain regions, a channel forming region, and a gate electrode, (B) a video signal write transistor having source/drain regions, a channel forming region, and a gate electrode, and (C) a capacitive unit. In the drive transistor, (A-1) one of the source/drain regions is connected to the corresponding current supply line, (A-2) the other region of the source/drain regions is connected to the light-emitting unit and connected to one end of the capacitive unit, and forms a second node, and (A-3) the gate electrode is connected to the other region of the source/drain regions of the video signal write transistor and connected to the other end of the capacitive unit, and forms a first node.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: May 15, 2018
    Assignee: Sony Corporation
    Inventors: Junichi Yamashita, Yusuke Onoyama, Tetsuo Minami, Naobumi Toyomura, Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: 9922980
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming a diamond film on the substrate, etching the diamond film to form a first trench that extends to the substrate, epitaxially growing a first semiconductor material in the first trench to form a first semiconductor fin structure, and removing an upper portion of the diamond film to expose an upper portion of the first semiconductor fin structure.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 20, 2018
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 9899437
    Abstract: A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: February 20, 2018
    Assignee: INTELLECTUAL VENTURES II LLC
    Inventor: Won-Ho Lee
  • Patent number: 9865792
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Patent number: 9824965
    Abstract: An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: November 21, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Qian Tao, Boon Keat Tan, Richard Lum Kok Keong
  • Patent number: 9793256
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: October 17, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 9793372
    Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Jan Hoentschel, Nigel Chan, Sven Beyer
  • Patent number: 9793182
    Abstract: A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies AG
    Inventor: Francisco Javier Santos Rodriguez
  • Patent number: 9773734
    Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Gurtej S. Sandhu
  • Patent number: 9773784
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: September 26, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chieh-Chih Chen, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 9768282
    Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a high doping concentration at a junction with the base and at least one grading in which doping concentration increases away from the base. In some embodiments, the high doping concentration can be at least about 3×1016 cm?3. According to certain embodiments, the collector includes two gradings. Such bipolar transistors can be implemented, for example, in power amplifiers.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 19, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Peter J. Zampardi, Jr.
  • Patent number: 9712165
    Abstract: A semiconductor device includes: a first power source (PS1) pad supplied with a PS1 voltage; a PS1 line connected to the PS1 pad; a first ground line (G1); an output circuit operated using the PS1 voltage; a second power source (PS2) pad supplied with a PS2 voltage; a PS2 line connected to the PS2 pad; a second ground line (G2); a signal line connected to an output end of the output circuit; an input circuit connected to the signal line at an input end receiving a signal from the output end and operated using the PS2 voltage; a main protection circuit unit providing discharge routes between the PS1 pad and G1, G1 and G2, and G2 and the PS2 pad; and a sub protection circuit unit. The output circuit includes: a circuit element arranged between the PS1 line and the signal line and able to function as a resistive element.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: July 18, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Mototsugu Okushima
  • Patent number: 9698044
    Abstract: A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: July 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alex Kalnitsky, Chih-Wen Yao, Jun Cai, Ruey-Hsin Liu, Hsiao-Chin Tuan
  • Patent number: 9691865
    Abstract: A high frequency semiconductor device includes a stacked body, a gate electrode, a source electrode and a drain electrode. The gate electrode includes a bending gate part and a straight gate part. The bending gate part is extended in a zigzag shape and has first and second outer edges. The source electrode includes a bending source part and a straight source part. The bending source part has an outer edge spaced by a first distance from the first outer edge of the bending gate part along a normal direction. The drain electrode includes a bending drain part and a straight drain part. The bending drain part has an outer edge spaced by a second distance from the second outer edge of the bending gate part along the normal direction.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 27, 2017
    Assignee: Kabushiki Kaishi Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 9679963
    Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 13, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Dmitri Alex Tschumakow, Erhard Landgraf, Claus Dahl, Steffen Rothenhaeusser
  • Patent number: 9634129
    Abstract: An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and the gate trench and electrically isolating the gate trench from an electrically conductive layer. A contact opening in the electrically insulative layer extends into the emitter trench and the electrically conductive layer electrically couples with the emitter trench therethrough. A P surface doped (PSD) region and an N surface doped (NSD) region are each located between the electrically conductive layer and a plurality of semiconductor layers of the IGBT and between the gate trench and the emitter trench. The electrically conductive layer electrically couples to the plurality of semiconductor layers through the PSD region and/or the NSD region.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: April 25, 2017
    Assignee: SEMICONDUCTOR COMPONENT INDUSTRIES, LLC
    Inventor: Takumi Hosoya
  • Patent number: 9627521
    Abstract: A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has a central shallower portion and a peripheral deeper portion. An inner sidewall of the trench is semiconductor material of the peripheral deeper portion of the floating P-well. On the other side of the trench is a P type body region involving a plurality of deeper portions and a plurality of shallower portions. Each deeper portion extends to the trench such that some parts of the outer sidewall of the trench are semiconductor material of these deeper P-body portions. Other parts of the outer sidewall of the trench are semiconductor material of the shallower P-body portions. A shallow N+ emitter region is disposed at the top of the outer sidewall. The IGBT has fast turn off and enhanced on state conductivity modulation.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: April 18, 2017
    Assignee: IXYS Corporation
    Inventor: Vladimir Tsukanov
  • Patent number: 9595948
    Abstract: A semiconductor device has a drive unit outputting a first drive signal to a first electrode and a second drive signal to a second electrode, an instruction signal generation unit generating an instruction signal as a basis of the drive signals and a control unit outputting a first control signal as a basis of the first drive signal and a second control signal as a basis of the second drive signal, based on the instruction signal to control the drive unit. The control unit synchronizes the first control signal with the instruction signal, delays a turning-on timing of the second control signal by a predetermined time relative to the instruction signal and determines a turning-off timing of the second control signal based on a previous pulse width of the instruction signal.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: March 14, 2017
    Assignee: DENSO CORPORATION
    Inventor: Hironori Akiyama
  • Patent number: 9595500
    Abstract: A semiconductor device includes: a semiconductor chip having a switching element and multiple pads electrically connected to the switching element; and multiple lead terminals electrically connected to the respective pads. The multiple lead terminals include a control terminal used for control of on/off operation of the switching element, and a main terminal into which a main current flows when the switching element is in an on state. A coupling coefficient k falls within a range of ?3%?k?2%, where the coupling coefficient k is defined by a parasitic inductance Lg in a current path of a control current flowing in the control terminal, a parasitic inductance Lo in a current path of the main current, and a mutual inductance Ms of the parasitic inductances Lg and Lo.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: March 14, 2017
    Assignee: DENSO CORPORATION
    Inventor: Kenji Kouno
  • Patent number: 9548421
    Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: January 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9548298
    Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 17, 2017
    Assignee: TEXAS INSTUMENTS INCORPORATED
    Inventors: Weidong Tian, YuGuo Wang, Tathagata Chatterjee, Rajni J. Aggarwal
  • Patent number: 9543403
    Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hanyi Ding, Vibhor Jain, Qizhi Liu
  • Patent number: 9530693
    Abstract: A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: December 27, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jong Il Kim
  • Patent number: 9531466
    Abstract: A diversity reception circuit obtains a synthesized output based on signals received at a plurality of antennas. The diversity reception circuit includes a plurality of PLLs outputting respective local oscillation signals; a plurality of mixers converting respective received radio frequency signals to low frequency signals; and a switch circuit selecting any one of outputs of the PLLs and supplying the selected output to at least one of the mixers.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 27, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Atsushi Ohara, Yoshifumi Hosokawa, Yoshihiro Okumura
  • Patent number: 9508708
    Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kamel Benaissa
  • Patent number: 9502409
    Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Chih Chieh Yeh, Ken-Ichi Goto, Zhiqiang Wu
  • Patent number: 9437691
    Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each include a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 6, 2016
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy
  • Patent number: 9437772
    Abstract: Methods of manufacture of advanced heterojunction transistors and transistor lasers, and their related structures, are described herein. Other embodiments are also disclosed herein.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: September 6, 2016
    Inventor: Matthew H. Kim
  • Patent number: 9431398
    Abstract: According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: August 30, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Thomas Kuenemund
  • Patent number: 9419118
    Abstract: A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has a central shallower portion and a peripheral deeper portion. An inner sidewall of the trench is semiconductor material of the peripheral deeper portion of the floating P-well. On the other side of the trench is a P type body region involving a plurality of deeper portions and a plurality of shallower portions. Each deeper portion extends to the trench such that some parts of the outer sidewall of the trench are semiconductor material of these deeper P-body portions. Other parts of the outer sidewall of the trench are semiconductor material of the shallower P-body portions. A shallow N+ emitter region is disposed at the top of the outer sidewall. The IGBT has fast turn off and enhanced on state conductivity modulation.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 16, 2016
    Assignee: IXYS Corporation
    Inventor: Vladimir Tsukanov
  • Patent number: 9397164
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Patent number: 9397192
    Abstract: A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 19, 2016
    Assignee: SK Hynix Inc.
    Inventor: Joon Seop Sim
  • Patent number: 9379109
    Abstract: An integrated circuit device having improved radiation immunity is described. The integrated circuit device comprises an n-type wafer having a first surface and a second surface; a p-type epitaxial layer formed on the first surface of the n-type wafer, the p-type epitaxial wafer having first elements storing charge; and an n-well formed in the p-type epitaxial layer, the n-well having second elements storing charge; wherein the n-type wafer is positively biased to attract excess minority carriers in the p-type epitaxial layer. A method of improving radiation immunity in an integrated circuit is also described.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: June 28, 2016
    Assignee: XILINX, INC.
    Inventors: James Karp, Michael J. Hart
  • Patent number: 9356512
    Abstract: A communication device, such as a smart phone, includes an envelope tracking power supply. The envelope tracking power supply is configured for direct connection to a supply voltage. The direct connection may be made without connection through an intermediate voltage regulator, such as a low drop out regulator. The supply voltage may be a relatively high battery voltage, for example, that would normally result in greater than permissible voltage limits on the transistors used in conventional envelope tracking power supplies.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 31, 2016
    Assignee: Broadcom Corporation
    Inventors: Debopriyo Chowdhury, Ali Afsahi
  • Patent number: 9324705
    Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: April 26, 2016
    Assignee: MEDIATEK INC.
    Inventors: Ching-Chung Ko, Tung-Hsing Lee
  • Patent number: 9306042
    Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 9306021
    Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-jong Chung, David Seo, Seong-jun Park, Kyung-eun Byun, Hyun-jae Song, Hee-jun Yang, Jin-seong Heo
  • Patent number: 9293525
    Abstract: A semiconductor device includes a high voltage isolation structure having a double RESURF structure. The high voltage isolation structure separates a low potential region from a high potential region. The high voltage isolation structure has an annular strip shape in a plan view and includes a straight portion and a corner portion which is connected to the straight portion. In the high voltage isolation structure, a p-type RESURF region is formed in a surface layer of a front surface of a substrate in an n-type well region along the outer circumference of the n-type well region. In the corner portion, the total amount of impurities per unit area in the RESURF region is less than that in the straight portion.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 22, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akihiro Jonishi, Masaharu Yamaji
  • Patent number: 9281056
    Abstract: A static random access memory (SRAM) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The SRAM further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The SRAM further includes a pre-discharge circuit connected to the bit line and to the bit line bar, wherein the pre-discharge circuit includes at least two n-type transistors. The SRAM further includes cross-coupled transistors connected to the bit line and to the bit line bar, wherein each transistor of the cross-coupled transistors is an n-type transistor. The SRAM further includes a write multiplexer connected to the bit line and to the bit line bar, wherein the write multiplexer includes two p-type transistors.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Ping-Wei Wang
  • Patent number: 9274982
    Abstract: A switch circuit for switching between a first storage and a second storage. The switch circuit includes a switch, first and second control circuits, a switch control chip, and a processing chip. When the second control circuit transmits power from a power supply to the first storage, the first control circuit connects the power supply to the first storage, and connects the second control circuit to the processing chip the first storage regardless of the state of the switch. When the second control circuit transmits power from the power supply to the second storage, the first control circuit connects the power supply to the second storage, and connects the processing chip to the second storage regardless of the state of the switch.
    Type: Grant
    Filed: August 12, 2012
    Date of Patent: March 1, 2016
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Jian-Ping Deng
  • Patent number: 9276095
    Abstract: A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess that extends from an upper surface of the fourth semiconductor region and reaches the second semiconductor region with penetrating the fourth semiconductor region and the third semiconductor region; a control electrode, which is arranged on the insulation film on a side surface of the recess and faces the third semiconductor region; a first main electrode, which is electrically connected to the first semiconductor region, and a second main electrode, which is electrically connected to the fourth semiconductor region, wherein a ratio of a width of the recess to a width of the third semiconductor region contacting the second main electrode is 1 or larger.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: March 1, 2016
    Assignee: Sanken Electric Co., LTD.
    Inventors: Kazuko Ogawa, Satoshi Kawashiri
  • Patent number: 9209095
    Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. Fin hardmasks are formed on the wafer. A dummy gate is formed on the wafer, over the fin hardmasks. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer and the dummy gate is removed selective to the dielectric filler layer so as to form a trench in the filler layer. Fins are patterned in the wafer using the fin hardmasks exposed within the trench, wherein the fins will serve as a base region of the bipolar transistor device. The fins are recessed in the base region. The base region is re-grown from an epitaxial SiGe, Ge or III-V semiconductor material. A contact is formed to the base region.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight