Complementary Transistors In Wells Of Opposite Conductivity Types More Heavily Doped Than The Substrate Region In Which They Are Formed, E.g., Twin Wells Patents (Class 257/371)
  • Patent number: 7964918
    Abstract: A gate electrode of one of an nFET and a pFET includes a metal-containing layer in contact with a gate insulating film and a first silicon-containing layer formed on the metal-containing layer, and a gate electrode of the other FET includes a second silicon-containing layer in contact with a gate insulating film and a third silicon-containing layer formed on the second silicon-containing layer. The first silicon-containing layer and the third silicon-containing layer are formed by the same silicon-containing material film.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Kenshi Kanegae, Takayuki Yamada
  • Patent number: 7964894
    Abstract: An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: June 21, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
  • Publication number: 20110140202
    Abstract: A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 16, 2011
    Inventors: Yoon-Moon PARK, Se-Jun Park, Suk-Kang Sung, Keon-Soo Kim, Jung-Dal Choi, Choong-Ho Lee, Jin-Hyun Shin, Seung-Wook Choi, Dong-Hoon Jang
  • Patent number: 7960802
    Abstract: A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: June 14, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, James Joseph Chambers
  • Patent number: 7956422
    Abstract: A semiconductor device, a method for fabricating the same, and a transformer circuit using the same are disclosed. The semiconductor device includes a trench metal oxide semiconductor (MOS) transistor for switching a load of current supplied from a power source, and a boost controller for controlling driving of the trench MOS transistor, the boost controller being formed with the trench MOS transistor on a single semiconductor device to form an integrated structure. In this structure, the physical space of the semiconductor device is reduced, thereby reducing the size of a DC-DC transformer circuit using the semiconductor device. It is possible to obtain finely-adjusted output values by controlling values of the ripple current and ripple voltage. A desired operational stability according to a variation in temperature can also be secured.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: June 7, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Byung Tak Jang
  • Publication number: 20110089497
    Abstract: A method for manufacturing a semiconductor device includes: forming an isolation region for defining a plurality of active regions in a silicon substrate; doping p-type impurities in at least one of the plurality of active regions to form a p-type well; forming an NMOS gate electrode traversing the p-type well via a gate insulating film; implanting n-type impurity ions into the p-type well on both sides of the NMOS gate electrode to form n-type extension regions; forming an NMOS gate side wall spacer on side walls of the NMOS gate electrode; implanting n-type impurity ions into the p-type well outside the NMOS gate side wall spacers to form n-type source/drain regions; forming a nickel silicide layer in surface regions of the n-type source/drain regions; and implanting Al ions the said n-type source/drain regions to dope Al in the nickel silicide layer surface regions.
    Type: Application
    Filed: December 9, 2010
    Publication date: April 21, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Hidenobu Fukutome
  • Patent number: 7929321
    Abstract: A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T2 and T3 passes through a channel region of the depletion mode MOSFET instead of a built-in diode D2 of the low-side MOSFET transistor. The depletion mode MOSFET further includes trench gates surrounded by body regions with channel regions immediately adjacent to vertical sidewalls of the trench gates wherein the channel regions formed as depletion mode channel regions by dopant ions having electrical conductivity type opposite from a conductivity type of the body regions.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 19, 2011
    Assignee: Force-Mos Technology Corp
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7928512
    Abstract: A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: April 19, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Lang
  • Patent number: 7923786
    Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: An L. Steegen, Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert Wong
  • Patent number: 7923805
    Abstract: Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: ChanSam Chang, Shigenobu Maeda, HeonJong Shin, ChangBong Oh
  • Patent number: 7910957
    Abstract: A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: March 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Junichi Mitani, Satoshi Nakai, Kazushi Fujita
  • Patent number: 7911003
    Abstract: A semiconductor integrated circuit device including a semiconductor substrate and a MOS transistor having a source diffusion region and a drain diffusion region formed in the semiconductor substrate. A well is formed in the semiconductor substrate. A back gate diffusion region is defined in the vicinity of the source diffusion region or the drain diffusion region. The back gate diffusion region is of a conductivity type that is the same as that of the source diffusion region or the drain diffusion region. A potential control layer, arranged in the semiconductor substrate or under the well, controls the potential at the semiconductor substrate or the well.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kazutaka Takeuchi
  • Patent number: 7911005
    Abstract: A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing arsenic and phosphorus as impurities; and a second transistor formed in a logic region, and having a second source/drain region containing at least arsenic as an impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by phosphorus and is deeper than the junction depth of the second source/drain region.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: March 22, 2011
    Assignee: RENESAS Electronics Corporation
    Inventor: Hiroki Shirai
  • Patent number: 7906800
    Abstract: A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: March 15, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 7902020
    Abstract: A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from th
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: March 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Il-Yong Park
  • Patent number: 7888745
    Abstract: An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Marwan H. Khater, Andreas D. Stricker, Bradley A. Orner, Mattias E. Dahlstrom
  • Patent number: 7888200
    Abstract: In some aspects, a method of forming a memory circuit is provided that includes (1) forming a two-terminal memory element on a substrate between a gate layer and a first metal layer of the memory circuit; and (2) forming a CMOS transistor on the substrate, the CMOS transistor for programming the two-terminal memory element. Numerous other aspects are provided.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: February 15, 2011
    Assignee: Sandisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 7884426
    Abstract: Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Kenichi Yoda
  • Patent number: 7884424
    Abstract: An architecture of the layout of the MTCMOS standard cell designed for low power consumption is supplemented so that the pick-up cells are included in the power line of the MTCMOS cell. Therefore, when the logic circuit is constructed using the library layout of the MTCMOS cell in which the related pick-up cells are not included, pick-up cells consisting of only the ends of the pick-up cells are not needed every 50 ?m during the placement of the MTCMOS standard cell. The flexibility of the cell placement may thereby be improved. In addition, since additional space for the pick-up cells is not required, the size of the MTCMOS may be reduced, saving space on the semiconductor substrate.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Dong-Hun Kim
  • Publication number: 20110024847
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Application
    Filed: October 11, 2010
    Publication date: February 3, 2011
    Inventors: NAOZUMI MORINO, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Patent number: 7882476
    Abstract: Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of the number of transistors to be switched at the same timing in the temporarily designed circuit, the sizes of transistors, the transition probability, and the appearance probability. It is determined whether the estimated change in the substrate potential is within a reference value. If the estimated change in the substrate potential has exceeded the reference value, standard cells with a well potential fixing active region (2T-11, 2T-21, 2T-31 and 2T-41) are read from the library and placed in a region where the estimated change in the substrate potential exceeds the reference value. Thereafter, automatic layout wiring is done again, thereby forming a circuit.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: February 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhito Itaka, Koichi Kinoshita, Takeshi Sugahara
  • Patent number: 7875511
    Abstract: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Liu Yaocheng, Ricardo A. Donaton, Kern Rim
  • Patent number: 7872312
    Abstract: A semiconductor device includes a first gate electrode formed in a first region on a semiconductor substrate with a first gate insulating film sandwiched therebetween; and a second gate electrode formed in a second region on the semiconductor substrate with a second gate insulating film sandwiched therebetween. The first gate insulating film includes a first high dielectric constant insulating film with a first nitrogen concentration and the second gate insulating film includes a second high dielectric constant insulating film with a second nitrogen concentration higher than the first nitrogen concentration.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: January 18, 2011
    Assignee: Panasonic Corporation
    Inventor: Hisashi Ogawa
  • Patent number: 7868392
    Abstract: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RP?, RP?) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN?, RP?) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 11, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Francois Tailliet
  • Patent number: 7868391
    Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Phil Christopher Felice Paone, David P. Paulsen, John E. Sheets, II, Kelly L. Williams
  • Patent number: 7868390
    Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: January 11, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Pei-Yu Chou, Shih-Fang Tzou, Jiunn-Hsiung Liao
  • Patent number: 7863653
    Abstract: A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same crystalline orientation. The device further includes a graded germanium layer on the first silicon layer, wherein the graded germanium layer contacts a spacer and the first silicon layer and does not contact the oxide layer. A lower portion of the graded germanium layer comprises a higher concentration of germanium than an upper portion of the graded germanium layer, wherein a top surface of the graded germanium layer lacks germanium.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Henry K. Utomo, Judson R. Holt, Haining S. Yang
  • Patent number: 7863688
    Abstract: Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: January 4, 2011
    Inventors: Mike Pelham, James B. Burr
  • Patent number: 7859062
    Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: December 28, 2010
    Inventors: Kleanthes G. Koniaris, Robert Paul Masleid, James B. Burr
  • Patent number: 7847616
    Abstract: A balanced input inverter circuit includes a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output, a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential, a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor, a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit, a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor, and a second diode connected between the second power source potential and a second power source terminal of the sec
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: December 7, 2010
    Assignee: Fujitsu Limited
    Inventor: Yasuhiro Hashimoto
  • Patent number: 7843012
    Abstract: The CMOS transistor of the present invention includes deep halo doped regions in the substrate, which can avoid the occurrence of latch-up. In addition, the fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: November 30, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Ming-I Chen, Fang-Mei Chao
  • Patent number: 7843227
    Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: November 30, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Masanori Isoda
  • Patent number: 7838960
    Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: November 23, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Masaaki Abe, Hidehiko Yajima, Takemi Yonezawa, Fumikazu Komatsu, Mitsuaki Sawada
  • Patent number: 7838908
    Abstract: A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Unoh Kwon, Siddarth A. Krishnan, Takashi Ando, Michael P. Chudzik, Martin M. Frank, William K. Henson, Rashmi Jha, Yue Liang, Vijay Narayanan, Ravikumar Ramachandran, Keith Kwong Hon Wong
  • Patent number: 7829954
    Abstract: In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the source by a gate, and an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the gate. The integrated circuit structure also comprises a second complementary MOS device comprising a dual drain extension structure.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: November 9, 2010
    Assignee: Intersil Americas Inc.
    Inventor: James Douglas Beasom
  • Patent number: 7821075
    Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: October 26, 2010
    Assignee: Avolare 2, LLC
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 7821076
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: April 12, 2009
    Date of Patent: October 26, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Patent number: 7816739
    Abstract: A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type/n-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third semiconductor layers are formed in the second semiconductor layer and have a depth reaching an inner part of the first semiconductor layer. In case that the second and third semiconductor layers are n-type and p-type, respectively, a lattice constant of the second semiconductor layer is less than that of the third semiconductor layer. In case that the second and third semiconductor layers are p-type and n-type, respectively, the lattice constant of the second semiconductor layer is greater than that of the third semiconductor layer. A first gate electrode is formed on the second semiconductor layer.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: October 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirohisa Kawasaki
  • Patent number: 7816742
    Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: October 19, 2010
    Inventors: Kleanthes G. Koniaris, Robert Paul Masleid, James B. Burr
  • Patent number: 7812374
    Abstract: A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction; and a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction, wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: October 12, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuyuki Tamura, Ken Suzuki, Katsuhiro Ootani
  • Patent number: 7812402
    Abstract: In the upper surface of a p? substrate, an n-type impurity region is formed. In the upper surface of the n-type impurity region, a p-well is formed. Also in the upper surface of the n-type impurity region, a p+-type source region and a p+-type drain region are formed. In the upper surface of the p-well, an n+-type drain region and an n+-type source region are formed. In the p? substrate, an n+ buried layer having an impurity concentration higher than that of the n-type impurity region is formed. The n+ buried layer is formed in contact with the bottom surface of the n-type impurity region at a greater depth than the n-type impurity region.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 12, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazurnari Hatade
  • Patent number: 7804132
    Abstract: A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: September 28, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Yuichi Hirano
  • Patent number: 7786504
    Abstract: The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semico
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: August 31, 2010
    Assignee: Amazing Microelectronic Corp.
    Inventors: Wen-Yi Chen, Ryan Hsin-Chin Jiang, Ming-Dou Ker
  • Patent number: 7777279
    Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 17, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazunari Hatade, Hajime Akiyama, Kazuhiro Shimizu
  • Patent number: 7772070
    Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: August 10, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyasu Kitajima, Hiroshi Furuta, Toshikatsu Jinbo
  • Patent number: 7763944
    Abstract: The invention relates to a CMOS device (10) with an NMOST I and PMOST 2 having gate regions (1D,2D) comprising a compound containing both a metal and a further element. According to the invention the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and both comprise as the further element an element selected from the group comprising carbon, oxygen and the chalcogenides. Preferably both the first and second conducting material comprise a compound of molybdenum and carbon or oxygen. The invention also provides an attractive method of manufacturing such a device.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: July 27, 2010
    Assignee: NXP B.V.
    Inventors: Jacob C. Hooker, Robert Lander, Robertus Wolters
  • Patent number: 7763946
    Abstract: A semiconductor device includes: a substrate and a p-channel MIS transistor. The p-channel MIS transistor includes: an n-type semiconductor region formed in the substrate; p-type first source and drain regions formed at a distance from each other in the n-type semiconductor region; a first gate insulating film formed on the n-type semiconductor region between the first source region and the first drain region; and a first gate electrode formed on the first gate insulating film. The first gate electrode includes a first nickel silicide layer having a Ni/Si composition ratio of 1 or greater, and a silicide layer formed on the first nickel silicide layer. The silicide layer contains a metal having a larger absolute value of oxide formation energy than that of Si, and a composition ratio of the metal to Si is smaller than the Ni/Si composition ratio.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: July 27, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Tsuchiya, Masato Koyama
  • Patent number: 7759744
    Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: July 20, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Masayuki Terai
  • Patent number: 7759740
    Abstract: A deep n well capacitor. A deep n well is formed in an integrated circuit. The deep n well can be parasitically coupled to Vdd and ground. A reverse-biased diode depletion region forms between n type and p type material, creating a capacitor. The capacitor provides local, on-chip decoupling of power supplied to active transistor devices on the integrated circuit, enabling greater operating frequencies for the integrated circuit.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: July 20, 2010
    Inventors: Robert P. Masleid, James B. Burr
  • Patent number: RE41477
    Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: August 10, 2010
    Inventor: James D. Beasom