Abstract: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells wherein the layout of the trenched gate surrounding the transistor cells as closed cells having truncated corners or rounded corners. In an exemplary embodiment, the closed cells further includes a contact metal to contact a source and a body regions wherein the contact metal the trenched gate surrounding the transistor cell have a uniform space between them. In another exemplary embodiment, the semiconductor power device further includes a contact dopant region disposed below the contact metal to enhance an electrical contact between the metal contact and the source region and the body region, and the contact dopant region having substantially circular shape to achieve a uniform space between the contact dopant region and the trenched gate surrounding the closed cells.

Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Abstract: A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench.

Abstract: The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semico

Abstract: A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.

Abstract: A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

Abstract: The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.

Abstract: A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a cond

Abstract: Latch-up of CMOS devices (20, 20?) is improved by using a structure (40, 40?, 80) having electrically coupled but floating doped regions (64, 64?; 65, 65?) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64?; 65, 65?) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64?) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55?) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions.

Abstract: A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to a startup circuit of a switching-mode power supply, the multipurpose resistor serves as startup resistor for limiting the flow of rush current during the startup period of the switching-mode power supply.

Abstract: The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the <100> direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

Abstract: A metal oxide semiconductor field effect transistor includes a semiconductor substrate; a well region containing an impurity of a first conductivity type disposed on the semiconductor substrate, the well region including a source region and a drain region formed by adding an impurity of a second conductivity type, the source region and the drain region being separated from each other by a predetermined gap; an insulating film disposed on the surface of the well region in the gap between the source region and the drain region; and a gate electrode disposed on the insulating film. The well region is composed of an epitaxial layer, and the epitaxial layer includes an impurity layer of the first conductivity type having a different impurity concentration.

Abstract: In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated.

Abstract: Systems and methods for voltage distribution via epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises an epitaxial layer of a connectivity type disposed upon a wafer substrate of an opposite connectivity type.

Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a SRAM region; an N-type element region formed in the SRAM region on the semiconductor substrate and including N-type source/drain regions; a P-type element region formed in the SRAM region on the semiconductor substrate so as to be substantially parallel to the N-type element region and including P-type source/drain regions; P-type well contact connections and N-type well contact connections formed on both sides of the N-type and P-type element regions in a longitudinal direction outside the SRAM region on the semiconductor substrate, respectively; an element isolation region for isolating the N-type element region, the P-type element region, the P-type well contact connection and the N-type well contact connection; a P-type well continuously formed under the N-type element region and the P-type well contact connection in the semiconductor substrate, and an N-type well continuously formed under the P-type element re

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.

Abstract: Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.

Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

Abstract: The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner.

Abstract: An integrated circuit includes a substrate, a noise sensitive circuit, and a first low impedance guard ring. The substrate includes a well-doped blocking ring that at least partially surrounds the noise sensitive circuit. The noise sensitive circuit is fabricated on the substrate. The first low impedance guard ring is fabricated on the substrate to at least partially surround the well-doped blocking ring, wherein the first low impedance guard ring is operably coupled to a first circuit ground, wherein impedance of the first low impedance guard ring is substantially less than impedance of the well-doped blocking ring.

Abstract: The present invention discloses a coaxial transistor formed on a substrate, particularly a coaxial metal-oxide-semiconductor field-effect transistor (CMOSFET). The chips or substrates of the CMOSFETs can be stacked up and connected via through-holes to form a coaxial complementary metal-oxide-semiconductor field-effect transistor (CCMOSFET), which is both full-symmetric and full-complementarily, has a higher integration and is free of the latch-up problem.

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: A transponder device comprises an integrated CMOS circuit with a semiconductor substrate. A first rectifying diode (DS) is formed by the substrate diode of the CMOS circuit. A first MOS transistor structure (DR1) and a second MOS transistor structure (DR2) have their channels connected in series such that they function as a second rectifying diode, the cathode of the first rectifying diode being connected to the anode of the second rectifying diode. The first MOS transistor structure (DR1) and the second MOS transistor structure (DR2) are spaced from each other such that a distance between the two MOS transistor structures is large enough that a parasitic npn-structure formed within the substrate by the first and the second MOS structures has a negligible current gain.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, wherein the metal gate is formed of a metal nitride that contains Al or Si and includes upper and lower portions where the content of Al or Si is relatively high and a central portion where the content of Al or Si is relatively low.

Abstract: A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

Abstract: A semiconductor device comprising: a semiconductor substrate; an n-type MIS transistor which is formed on the semiconductor substrate and has a first metal gate electrode and a first polycrystalline silicon layer formed on the first metal gate electrode; a p-type MIS transistor which is formed on the semiconductor substrate and has a second metal gate electrode and a second polycrystalline silicon layer, the second metal gate electrode containing at least one metallic element different from that of the first metal gate electrode, and the second polycrystalline silicon layer being formed on the second metal gate electrode and having the same conductivity type as that of the first polycrystalline silicon layer.

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p? substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

Abstract: A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

Abstract: The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin.

Abstract: A method of fabricating an electrical structure with increased charge carrier mobility is provided. The method includes forming an N-type field effect transistor (nFET) device and a P-type field effect transistors (pFET) device on a semiconductor substrate; forming a compressive stress film over said nFET device for exerting tensile stress in a first channel associated with said nFET device; and forming a tensile stress film over said pFET device for exerting compressive stress in a second channel associated with said pFET. The method further includes forming at least one shallow region between a first gate associated with said nFET and a second gate associated with said pFET for generating conductive stresses in said first and second channels.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.

Abstract: An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a supply voltage node and a power output node of the integrated circuit device, and the N-MOS bypass transistor is coupled between the power output node and a reference node of the integrated circuit device. The gate driver circuit responds to a pulse-width-modulated (PWM) control signal by outputting an active-low drive-enable signal to a gate terminal of the P-MOS power transistor and an active-high bypass-enable signal to a gate terminal of the N-MOS bypass transistor during respective, non-overlapping intervals.

Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.

Abstract: Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.

Abstract: A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract: A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).

Abstract: A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.