With Means To Prevent Latchup Or Parasitic Conduction Channels Patents (Class 257/372)
  • Patent number: 7326977
    Abstract: An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the surface of the semiconductor body by a distance d.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: February 5, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: Nathan Bluzer, Donald R. Lampe
  • Patent number: 7323753
    Abstract: To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is connected to the output of the NMOS, to shift the output of the NMOS for boosting. Then, a back gate of the NMOS is connected, via a PMOS in an on state, to the power source. With this structure, the PMOS provides a resistor component when the output terminal short-circuits.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: January 29, 2008
    Assignee: Sanyo Electric Co. Ltd.
    Inventors: Kazuo Henmi, Nobuyuki Otaka
  • Patent number: 7309898
    Abstract: A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: December 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Steven Howard Voldman
  • Patent number: 7304354
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: December 4, 2007
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 7282771
    Abstract: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped region is placed under semiconductor devices of the first polarity and under the well region contact region. Additionally, the structure may further include a deep trench (DT) structure and trench isolation (TI) structure to further improve latchup robustness.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 7271453
    Abstract: A structure of a semiconductor device and method for fabricating the same is disclosed. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: September 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Hussein I. Hanafi, Edward J. Nowak
  • Patent number: 7271452
    Abstract: An analog switch has a first circuit and a second circuit. The first circuit has an NMOS and PMOS connected in series, and the second circuit has a PMOS and NMOS connected in series. The first and second circuits are provided in parallel between an input terminal and output terminal of the analog switch. The gate of each NMOS is connected to a terminal to which a first clock signal is supplied, and the gate of each PMOS is connected to another terminal to which a second clock signal is supplied. The second clock signal is a reversal of the first clock signal. When the analog switch is set to the OFF state and a voltage that is above the supply potential is applied to the input terminal, the NMOSs become reverse-biased diodes. Therefore, an off leak current is not produced.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: September 18, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Mitsuru Arai
  • Patent number: 7268400
    Abstract: A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Delbert R. Cecchi, Toshiharu Furukawa, Jack Allan Mandelman
  • Patent number: 7205614
    Abstract: A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: April 17, 2007
    Assignee: Faraday Technology Corp.
    Inventors: Sheng-Tai Young, Te-Sun Wu, Tsung-Yuan Lee, Chih-Kang Chiu
  • Patent number: 7196393
    Abstract: A drain diffusion layer 11b includes a low impurity concentration region 5a and a high impurity concentration region 5b, and the low impurity concentration region 5a is located on the channel region side. An impurity layer 7 having an opposite conductivity type to the drain diffusion layer 11b is formed in the channel region, at a position away from the low impurity concentration region 5a by a distance T. Alternatively, the low impurity concentration region 5a and the impurity layer 7 are located so as to contact each other. Still alternatively, a border impurity layer is provided between the low impurity concentration region 5a and the impurity layer 7. Thus, a semiconductor device including a high voltage transistor capable of suppressing the reduction of the electric current driving capability and performing stable driving, and a method for fabricating the same, can be provided.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: March 27, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuhiro Suzuki, Minoru Morinaga, Yukihiro Inoue
  • Patent number: 7190034
    Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: March 13, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazunari Hatade, Hajime Akiyama, Kazuhiro Shimizu
  • Patent number: 7180142
    Abstract: The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc radius of a curved portion (portion where a line is brought to arcuate form) formed inside the pattern for the bent active region. By defining and designing the pattern interval, the curved portion of the active region do not overlap the gate pattern, and the difference between a device characteristic and a designed value can be prevented from increasing.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: February 20, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Koichi Kishiro
  • Patent number: 7176527
    Abstract: A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insulator, and has at least one MOSFET element. The MOSFET element includes a source region; a drain region which is opposed to the source region; a body region disposed between the source and drain regions; a gate region positioned on or close to a surface of the body region, so as to form an electrically conducting channel in the body region; and an extracting region being in contact with both of the body region and the source region. The extracting region has a conductivity type which is the same as a conductivity type of the body region and has a concentration higher than that of the body region.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: February 13, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Koichi Fukuda
  • Patent number: 7145191
    Abstract: The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: December 5, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 7112856
    Abstract: A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one embodiment of the present invention, one of the source or drain regions includes a first-concentration impurity region formed under the sidewall spacer. The semiconductor device further includes a silicide layer formed within the well region wherein at least a part of the silicide layer contacts a portion of the well region to bias the well region. A method of manufacturing the semiconductor device is also provided.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: September 26, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Sik Cho, Gyu-Chul Kim, Hoo-Sung Cho
  • Patent number: 7098512
    Abstract: Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: August 29, 2006
    Assignee: Transmeta Corporation
    Inventors: Mike Pelham, James B. Burr
  • Patent number: 7091564
    Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takehiro Hasegawa
  • Patent number: 7067883
    Abstract: A lateral high-voltage junction device for over-voltage protection of an MOS circuit includes a substrate having a first junction region separated from a second junction region by a substrate region. An MOS gate electrode overlies the substrate region and is separated therefrom by a gate dielectric layer. Sidewall spacers reside adjacent to opposing sides of the MOS gate electrode and overlie the substrate region. The substrate region is defined by a junction-free semiconductor region between the first and second junction regions. An input protection circuit employs the lateral high-voltage junction device to transfer voltage transients to a ground node.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: June 27, 2006
    Assignee: Lattice Semiconductor Corporation
    Inventor: Stewart Logie
  • Patent number: 7060566
    Abstract: An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: June 13, 2006
    Assignee: Infineon Technologies AG
    Inventor: Thomas Vogelsang
  • Patent number: 7057238
    Abstract: A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the semiconductor substrate; a channel silicon layer arranged under the gate insulating layer to operate as a channel for connecting sources and drains; and buried junction isolation insulating layers under the channel silicon layer. The buried junction isolation insulating layers isolate source/drain junction regions of a MOS transistor, so that a short circuit in a bulk region under the channel of a transistor due to the high-integration of the device can be prevented.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: June 6, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-young Kim, Ki-nam Kim
  • Patent number: 7038281
    Abstract: A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: May 2, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Motoi Ashida, Takashi Terada
  • Patent number: 7012309
    Abstract: The invention relates to an integrated CMOS circuit comprising, in a semiconductor substrate (1) with a first type of conductivity, a casing (2) of a second type of retrograde-doped conductivity, the end of said casing being covered by an inter-casing insulating region (4). The components contained in said casing are separated from each other by means of intra-casing insulating regions (6,7). The first insulating elements (15) of the second type of high-level doping conductivity extend under each intra-casing insulating region. A second region (21) of the second type of high-level doping conductivity partially extends under the inter-casing insulator beyond the periphery of each casing.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: March 14, 2006
    Assignee: STMicroelectronics S.A.
    Inventor: Rosalia Germana
  • Patent number: 7009257
    Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: March 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-pil Kim, Beom-jun Jin, Hyoung-joon Kim, Byeong-yun Nam
  • Patent number: 7009255
    Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: March 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nak-Jin Son, Ji-Young Kim
  • Patent number: 6995432
    Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: February 7, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 6995435
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor. The voltage potential may be provided to a diffusion region in the well regions with transistors.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: February 7, 2006
    Assignee: Intel Corporation
    Inventor: Mark E. Schuelein
  • Patent number: 6979908
    Abstract: A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also include an electrostatic discharge device formed in the substrate. The electrostatic discharge device is at least partially formed beneath the bond pad. The I/O module also includes an I/O buffer formed in the substrate. The I/O buffer is connected to the bond pad. The I/O buffer provides communication between the bond pad and circuitry formed in the substrate. The circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: December 27, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: U-Ming Ko
  • Patent number: 6972466
    Abstract: Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: December 6, 2005
    Assignee: Altera Corporation
    Inventors: Minchang Liang, Yow-Juang Liu, Fangyun Richter
  • Patent number: 6967381
    Abstract: In order to improve the robustness against electrostatic discharge, when power source terminal and ground terminal are open, of a semiconductor device having a first, a second and a third inverter that are connected in a cascade arrangement, the semiconductor device is provided not only with a first input protection circuit for guiding positive electrostatic discharges, that are applied from outside to a signal input terminal, to a power source line, and a second input protection circuit for guiding negative electrostatic discharges, that are applied from outside to the signal input terminal, to a ground line, but also an internal protection circuit for guiding electrostatic discharges that have been guided by the first input protection circuit to the power source line and flow from a P-channel MOS transistor in the second inverter towards the third inverter, to the ground line.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: November 22, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Tatehara, Norihide Kinugasa
  • Patent number: 6967380
    Abstract: A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Chung H. Lam, James A. Slinkman
  • Patent number: 6963113
    Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: November 8, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Ting Cheong Ang, Sang Yee Loong, Shyue Fong Quek, Jun Song
  • Patent number: 6956266
    Abstract: A method and structure for an integrated circuit comprising a substrate of a first polarity; a trench structure in the substrate; a well region of a second polarity abutting the trench structure; and a heavily doped region of the second polarity abutting the trench structure, wherein the heavily doped region is adapted to suppress latch-up in the integrated circuit, wherein the heavily doped region comprises a sub-collector region, and wherein the trench structure comprises a deep trench structure or a trench isolation structure. The integrated circuit further comprises a p+ anode in the well region and a n+ cathode in the well region, wherein the integrated circuit is configured as a latchup robust p-n diode. In another embodiment, the integrated circuit further comprises a p+ anode in the well region; a n+ cathode in the well region; and a gate structure over the p+ anode and n+ cathode.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: October 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Steven H. Voldman, Anne E. Watson
  • Patent number: 6946710
    Abstract: A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and align to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the P-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: September 20, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lyndon R. Logan, James A. Slinkman
  • Patent number: 6936898
    Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: August 30, 2005
    Assignee: Transmeta Corporation
    Inventors: Mike Pelham, James B. Burr
  • Patent number: 6921950
    Abstract: In order to improve the robustness against electrostatic discharge, when power source terminal and ground terminal are open, of a semiconductor device having a first, a second and a third inverter that are connected in a cascade arrangement, the semiconductor device is provided not only with a first input protection circuit for guiding positive electrostatic discharges, that are applied from outside to a signal input terminal, to a power source line, and a second input protection circuit for guiding negative electrostatic discharges, that are applied from outside to the signal input terminal, to a ground line, but also an internal protection circuit for guiding electrostatic discharges that have been guided by the first input protection circuit to the power source line and flow from a P-channel MOS transistor in the second inverter towards the third inverter, to the ground line.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: July 26, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Tatehara, Norihide Kinugasa
  • Patent number: 6909150
    Abstract: An integrated circuit having improved isolation includes a first circuit section formed in a substrate and a second circuit section formed in the substrate, the second circuit section being spaced laterally from the first circuit section. The integrated circuit further includes an isolation buried layer formed under at least a portion of the first circuit section, and a conductive layer formed on a surface of the substrate and electrically coupled to the buried layer and to a voltage reference, the conductive layer reducing an effective lateral resistance of the buried layer, whereby an isolation between the first and second circuit sections is increased. A second isolation buried layer can be formed under at least a portion of the second circuit section as well to provide further isolation between the first and second circuit sections.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: June 21, 2005
    Assignee: Agere Systems Inc.
    Inventor: Paul C. Davis
  • Patent number: 6878595
    Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: April 12, 2005
    Assignee: Full Circle Research, Inc.
    Inventor: James P Spratt
  • Patent number: 6864543
    Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N?S and/or a second drain layer N?D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: March 8, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
  • Patent number: 6864547
    Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a channel region located in a semiconductor substrate and a trench located adjacent a side of the channel region. The semiconductor device further includes an isolation structure located in the trench, and a source/drain region located over the isolation structure.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: March 8, 2005
    Assignee: Agere Systems Inc.
    Inventors: John A. Michejda, Ian Wylie
  • Patent number: 6864539
    Abstract: A semiconductor integrated circuit device has a MISFET and a body biasing circuit. The MISFET has a source electrode and a drain electrode of a first conductivity type and a gate electrode, and the MISFET is formed in a well of a second conductivity type. The body biasing circuit generates a voltage in the well by passing a prescribed current in a forward direction into a diode which is formed from the well and the source electrode of the MISFET.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: March 8, 2005
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Koichiro Ishibashi, Takahiro Yamashita
  • Patent number: 6849907
    Abstract: An electrostatic discharge (ESD) protection device. The ESD protection device includes a first parasitic bipolar transistor, a second parasitic bipolar transistor, a third parasitic bipolar transistor and a fourth parasitic bipolar transistor formed over a substrate. A first longitudinal doped region is formed between the first parasitic bipolar transistor and the second parasitic bipolar transistor. Similarly, a second longitudinal doped region is formed between the third parasitic bipolar transistor and the fourth parasitic bipolar transistor. A guard ring circumscribes the substrate. An isolation region is formed inside the guard ring. All collectors of the parasitic bipolar transistors are connected to an anode terminal. The guard ring, the first/second longitudinal doped regions and all emitters of the parasitic bipolar transistors are connected to a cathode terminal.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: February 1, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Tung-Yang Chen, Tien-Hao Tang
  • Patent number: 6833592
    Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: December 21, 2004
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Joo-Hyong Lee
  • Patent number: 6822298
    Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: November 23, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
  • Patent number: 6818957
    Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: November 16, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takehiro Hasegawa
  • Patent number: 6815777
    Abstract: A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: November 9, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Junichi Karasawa, Kunio Watanabe
  • Patent number: 6815780
    Abstract: A semiconductor component includes a semiconductor substrate (210) having a first conductivity type, a semiconductor epitaxial layer (220) having the first conductivity type located over the semiconductor substrate, a first semiconductor device (110) and a second semiconductor device (130) located in the semiconductor epitaxial layer and including, respectively, a first semiconductor region (120) and a second semiconductor region (140), both having the second conductivity type, an ohmic contact region (150) in the semiconductor epitaxial layer having the first conductivity type and located between the first and second semiconductor devices, and at least one electrically insulating trench (160, 360) located in the semiconductor epitaxial layer and circumscribing at least the first semiconductor device. The semiconductor epitaxial layer has a doping concentration lower than a doping concentration of the semiconductor substrate.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: November 9, 2004
    Assignee: Motorola, Inc.
    Inventors: Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose, Todd C. Roggenbauer
  • Patent number: 6806522
    Abstract: The invention provides a CMOS image sensor that can decrease the influence of the noise charge on the OB cells that determine the darkness level and can prevent the deterioration of the image quality. A region that absorbs the noise charge in a substrate is formed at the periphery of the cell array portion. As in the photodiode, a PN junction is formed in the noise charge absorption region, and one end thereof is connected to a power source voltage. This noise charge absorption region is formed between the cell array portion and the peripheral circuit portion.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: October 19, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Hiroaki Ohkubo
  • Patent number: 6800908
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor. The voltage potential may be provided to a diffusion region in the well regions with transistors.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: October 5, 2004
    Assignee: Intel Corporation
    Inventor: Mark E. Schuelein
  • Patent number: 6791147
    Abstract: A semiconductor memory device has a peripheral circuit area and a memory cell area on a main surface thereof. The semiconductor memory device includes a first well formed in the peripheral circuit area, a second well of a first conductivity type formed in the memory cell area, a third well of a second conductivity type formed in the memory cell area, and a device isolation structure formed in the memory cell area for isolating an element formed in the second well from an element formed in the third well. The second well of the first conductivity type has a depth shallower than a depth of the first well. The third well of the second conductivity type is equal in depth to the second well. The second and third wells are formed down to a level lower than the device isolation structure.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: September 14, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Junichi Karasawa, Kunio Watanabe, Takeshi Kumagai
  • Patent number: 6787858
    Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: September 7, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Moaniss Zitouni, Edouard D. de Frésart, Richard J. De Souza, Xin Lin, Jennifer H. Morrison, Patrice Parris