Combined With Bipolar Transistor Patents (Class 257/378)
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Patent number: 8963253Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.Type: GrantFiled: October 23, 2012Date of Patent: February 24, 2015Assignee: Macronix International Co., Ltd.Inventors: Hsin-Liang Chen, Shuo-Lun Tu
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Patent number: 8946018Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.Type: GrantFiled: August 21, 2012Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi
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METHODS OF FORMING BIPOLAR DEVICES AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH BIPOLAR DEVICES
Publication number: 20150001634Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Jerome Ciavatti, Roderick Miller, Marc Tarabbia -
Patent number: 8921945Abstract: The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 ?m. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.Type: GrantFiled: June 15, 2009Date of Patent: December 30, 2014Assignee: X-Fab Semiconductor Foundries AGInventor: Ralf Lerner
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Patent number: 8907450Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.Type: GrantFiled: November 9, 2011Date of Patent: December 9, 2014Assignee: QUALCOMM IncorporatedInventors: Changhan Yun, Chengjie Zuo, Chi Shun Lo, Jonghae Kim, Mario F. Velez
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Patent number: 8901669Abstract: A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method.Type: GrantFiled: July 27, 2012Date of Patent: December 2, 2014Assignee: NXP, B.V.Inventors: Hans Mertens, Johannes Theodorus Marinus Donkers, Evelyne Gridelet, Tony Vanhoucke, Petrus Hubertus Cornelis Magnee
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Patent number: 8901611Abstract: Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.Type: GrantFiled: October 2, 2013Date of Patent: December 2, 2014Assignee: Skyworks Solutions, Inc.Inventors: Peter J. Zampardi, Jr., Hsiang-Chih Sun
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Patent number: 8872222Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.Type: GrantFiled: February 24, 2012Date of Patent: October 28, 2014Assignee: Macronix International Co., Ltd.Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
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Patent number: 8860144Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.Type: GrantFiled: June 14, 2013Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune, Wataru Saito, Syotaro Ono
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Patent number: 8853775Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.Type: GrantFiled: September 9, 2013Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kazutoshi Nakamura, Hideaki Ninomiya, Tomoko Matsudai, Yuichi Oshino
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Patent number: 8847278Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.Type: GrantFiled: January 16, 2012Date of Patent: September 30, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Manabu Takei, Yusuke Kobayashi
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Patent number: 8836042Abstract: A semiconductor device includes an IGBT, a constant voltage circuit, and protection Zener diodes. The IGBT makes/breaks a low-voltage current flowing in a primary coil. The constant voltage circuit and the protection Zener diodes are provided between an external gate terminal and an external collector terminal. The constant voltage circuit supplies a constant gate voltage to the IGBT to thereby set a saturation current value of the IGBT to a predetermined limiting current value. The IGBT has the saturation current value in a limiting current value range of the semiconductor device.Type: GrantFiled: August 11, 2009Date of Patent: September 16, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Katsunori Ueno
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Patent number: 8829650Abstract: A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.Type: GrantFiled: January 4, 2013Date of Patent: September 9, 2014Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.Inventors: Donghua Liu, Jun Hu, Wenting Duan, Wensheng Qian, Jing Shi
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Patent number: 8829609Abstract: An insulated gate semiconductor device, comprising: a semiconductor body having a front side and a back side opposite to one another; a drift region, which extends in the semiconductor body and has a first type of conductivity and a first doping value; a body region having a second type of conductivity, which extends in the drift region facing the front side of the semiconductor body; a source region, which extends in the body region and has the first type of conductivity; and a buried region having the second type of conductivity, which extends in the drift region at a distance from the body region and at least partially aligned to the body region in a direction orthogonal to the front side and to the back side.Type: GrantFiled: July 26, 2012Date of Patent: September 9, 2014Assignee: STMicroelectronics S.r.l.Inventors: Donato Corona, Giovanni Samma Trice, Sebastiano Amara, Salvatore Pisano, Antonio Giuseppe Grimaldi
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Patent number: 8803244Abstract: A semiconductor device includes a first conductivity type base formed on a surface of a substrate, a second conductivity type emitter formed on a surface of the base, a second conductivity type doped region which, along with accepting a first type of carrier from the emitter, injects the first type of carrier into the base, and is arranged to be spaced apart on the surface of the base from the emitter, and a second conductivity type collector which is formed on an opposite side to the emitter and the doped region, interposing the base.Type: GrantFiled: October 19, 2012Date of Patent: August 12, 2014Assignee: Sony CorporationInventor: Hideki Mori
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Patent number: 8786024Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.Type: GrantFiled: April 15, 2011Date of Patent: July 22, 2014Assignees: Yoshitaka Sugawara, Fuji Electric Co., Ltd.Inventor: Yoshitaka Sugawara
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Patent number: 8754484Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.Type: GrantFiled: August 15, 2013Date of Patent: June 17, 2014Assignee: Texas Instruments IncorporatedInventors: Hiroshi Yasuda, Berthold Staufer
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Patent number: 8749017Abstract: Aspects of the invention are related to a semiconductor device including a first conductivity type n-type drift layer, a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer, and a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer. The invention can also include a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer.Type: GrantFiled: March 23, 2011Date of Patent: June 10, 2014Assignee: Fuji Electric Co., LtdInventor: Hong-fei Lu
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Publication number: 20140124871Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.Type: ApplicationFiled: January 22, 2014Publication date: May 8, 2014Applicant: MEDIATEK INC.Inventors: Ching-Chung Ko, Tung-Hsing Lee
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Publication number: 20140097472Abstract: Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.Type: ApplicationFiled: October 2, 2013Publication date: April 10, 2014Applicant: SKYWORKS SOLUTIONS, INC.Inventors: Peter J. Zampardi, JR., Hsiang-Chih Sun
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Publication number: 20140084380Abstract: In accordance with an embodiment, an integrated circuit has a first transistor made of a plurality of first transistor segments disposed in a well area, and a second transistor made of at least one second transistor segment. Drain regions of the plurality of first transistor segments and the at least one second transistor segment are coupled to a common output node. The at least one second transistor segment is disposed in the well area such that an electrostatic discharge pulse applied to a common output node homogenously triggers parasitic bipolar devices coupled to each drain region of the plurality of first transistor segments and the drain region of the at least one second transistor segment.Type: ApplicationFiled: September 25, 2012Publication date: March 27, 2014Applicant: INFINEON TECHNOLOGIES AGInventor: Krzysztof Domanski
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Patent number: 8669621Abstract: A semiconductor device includes a first insulated gate field effect transistor, a second insulated gate field effect transistor, a bipolar transistor, a first element isolation structure formed on a main surface above a pn junction formed between an emitter region and a base region, a second element isolation structure formed on the main surface above a pn junction formed between the base region and a collector region, and a third element isolation structure formed on the main surface opposite to the second element isolation structure relative to the collector region, in which the semiconductor device further includes a bipolar dummy electrode formed on at least one of the first element isolation structure, the second element isolation structure and the third element isolation structure and having a floating potential.Type: GrantFiled: June 24, 2010Date of Patent: March 11, 2014Assignee: Renesas Electronics CorporationInventor: Keiichi Yamada
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Patent number: 8653606Abstract: It is intended to provide a semiconductor device capable to improve a controllability of dv/dt by a gate drive circuit during a turn-on switching period, while maintaining a low loss and a high breakdown voltage. Trench gates are disposed so as to have narrow distance regions and wide distance regions, wherein each of the narrow distance regions is provided with a channel region, and each of the wide distance regions is provided with trenches, each trench having an electrode electrically connected to the emitter electrode. In this manner, even if a floating-p layer is removed, it is possible to reduce a feedback capacity and maintain a breakdown voltage.Type: GrantFiled: June 27, 2013Date of Patent: February 18, 2014Assignee: Hitachi, Ltd.Inventor: Masaki Shiraishi
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Patent number: 8653556Abstract: A vertical semiconductor device includes a semiconductor body, and first and second contacts on opposite sides of the semiconductor body. A plurality of regions are formed in the semiconductor body including, in a direction from the first contact to the second contact, a first region of a first conductivity type, a second region of a second conductivity type; and a third region of the first conductivity type. The third region is electrically connected to the second contact. A semiconductor zone of the second conductivity type and increased doping density is arranged in the second region. The semiconductor zone separates a first part of the second region from a second part of the second region. The semiconductor zone has a maximum doping density exceeding about 1016 cm?3 and a thickness along the direction from the first contact to the second contact of less than about 3 ?m.Type: GrantFiled: May 7, 2009Date of Patent: February 18, 2014Assignee: Infineon Technologies Austria AGInventors: Franz Josef Niedernostheide, Hans-Joachim Schulze
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Publication number: 20140035064Abstract: Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.Type: ApplicationFiled: August 3, 2012Publication date: February 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William F. CLARK, JR., Qizhi LIU, John J. Pekarik, Yun SHI, Yanli ZHANG
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Patent number: 8643118Abstract: Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.Type: GrantFiled: August 22, 2011Date of Patent: February 4, 2014Assignee: Skyworks Solutions, Inc.Inventors: Peter J Zampardi, Jr., Hsiang-Chih Sun
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Patent number: 8629509Abstract: High power insulated gate bipolar junction transistors are provided that include a wide band gap semiconductor bipolar junction transistor (“BJT”) and a wide band gap semiconductor MOSFET that is configured to provide a current to the base of the BJT. These devices further include a minority carrier diversion semiconductor layer on the base of the BJT and coupled to the emitter of the BJT, the minority carrier diversion semiconductor layer having a conductivity type opposite the conductivity type of the base of the BJT and forming a heterojunction with the base of the BJT.Type: GrantFiled: September 10, 2009Date of Patent: January 14, 2014Assignee: Cree, Inc.Inventors: Sei-Hyung Ryu, Qingchun Zhang
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Publication number: 20130341729Abstract: Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage.Type: ApplicationFiled: June 20, 2011Publication date: December 26, 2013Inventors: Digh Hisamoto, Shinichi Saito, Akio Shima, Hiroyuki Yoshimoto
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Patent number: 8614489Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.Type: GrantFiled: September 13, 2012Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: John B. Campi, Shunhua Thomas Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Publication number: 20130328130Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.Type: ApplicationFiled: August 15, 2013Publication date: December 12, 2013Applicant: Texas Instruments IncorporatedInventors: Hiroshi YASUDA, Berthold STAUFER
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Patent number: 8581347Abstract: Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.Type: GrantFiled: July 22, 2010Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Der-Chyang Yeh, Li-Weng Chang, Hua-Chou Tseng, Chih-Ping Chao
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Patent number: 8574982Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.Type: GrantFiled: February 25, 2010Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Karl Robert Erickson, David Paul Paulsen, John Edward Sheets, II, Kelly L. Williams
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Patent number: 8569840Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: GrantFiled: February 10, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Publication number: 20130277753Abstract: A BiCMOS device structure, method of manufacturing the same and design structure thereof are provided. The BiCMOS device structure includes a substrate having a layer of semiconductor material upon an insulating layer. The BiCMOS device structure further includes a bipolar junction transistor structure formed in a first region of the substrate having an extrinsic base layer formed at least partially from a portion of the layer of semiconductor material.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William F. Clark, JR., Qizhi Liu, Robert Mark Rassel, Yun Shi
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Publication number: 20130270649Abstract: A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.Type: ApplicationFiled: April 9, 2013Publication date: October 17, 2013Applicant: STMicroelectronics SAInventors: Alain Chantre, Pascal Chevalier, Gregory Avenier
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Patent number: 8546939Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).Type: GrantFiled: December 29, 2006Date of Patent: October 1, 2013Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Tomonori Tanoue, Sakae Kikuchi, Toshifumi Makino, Takeshi Sato, Tsutomu Kobori, Yasunari Umemoto, Takashi Kitahara
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Patent number: 8536655Abstract: Even in the case where negative current flows in a semiconductor device, the potential of a semiconductor substrate is prevented from becoming lower than the potential of a deep semiconductor layer which is a component of a circuit element, and a parasitic element is prevented from operating, which accordingly prevents malfunction of the semiconductor device. The semiconductor device includes the n-type semiconductor substrate, a power element, the circuit element, and an external circuit. The external circuit includes a power supply, a resistive element having one end connected to the power supply, and a diode having its anode electrode connected to the other end of the resistive element and its cathode electrode connected to the ground. To the other end of the resistive element, a semiconductor layer is connected.Type: GrantFiled: June 27, 2012Date of Patent: September 17, 2013Assignee: Mitsubishi Electric CorporationInventors: Koji Yamamoto, Atsunobu Kawamoto
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Patent number: 8502345Abstract: Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region.Type: GrantFiled: January 27, 2011Date of Patent: August 6, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Michio Nemoto, Souichi Yoshida
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Patent number: 8486755Abstract: Magnetic field sensors and associated methods of manufacturing the magnetic field sensors include molded structures to encapsulate a magnetic field sensing element and an associated die attach pad of a lead frame and to also encapsulate or form a magnet or a flux concentrator.Type: GrantFiled: December 5, 2008Date of Patent: July 16, 2013Assignee: Allegro Microsystems, LLCInventors: Virgil Ararao, Nirmal Sharma, Raymond W. Engel, Jay Gagnon, John Sauber, William P. Taylor, Elsa Kam-Lum
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Patent number: 8482082Abstract: An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode.Type: GrantFiled: September 22, 2011Date of Patent: July 9, 2013Assignee: Nuvoton Technology CorporationInventor: Ming-Fang Lai
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Patent number: 8482081Abstract: A high-performance semiconductor apparatus which can be easily introduced into the MOS process, reduces the leakage current (electric field strength) between the emitter and the base, and is insusceptible to noise or surge voltage, and a manufacturing method of the semiconductor apparatus. The emitter 111 is formed by performing the ion implantation twice by using the conductive film (109) as a mask. The second emitter area (111b) is formed by ion implantation of a low impurity density impurity ion, and the first emitter area (111a) is formed by ion implantation of a high impurity density impurity ion. As a result, the low impurity density second emitter area is formed in the circumference of the emitter 111, which lowers the electric field strength, and reduces the leakage current. Also the conductive film is connected with the emitter electrode (116), which makes the apparatus insusceptible to noise.Type: GrantFiled: November 30, 2010Date of Patent: July 9, 2013Assignee: Panasonic CorporationInventor: Mitsuo Tanaka
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Patent number: 8455953Abstract: A sinker layer is in contact with a first conductivity-type well and a second conductivity-type drift layer, respectively, and is separated from a first conductivity-type collector layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: GrantFiled: January 31, 2011Date of Patent: June 4, 2013Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Patent number: 8445970Abstract: The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate.Type: GrantFiled: September 16, 2011Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shine Chung
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Patent number: 8441075Abstract: A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted.Type: GrantFiled: February 18, 2010Date of Patent: May 14, 2013Assignee: Hitachi, Ltd.Inventors: Katsumi Ishikawa, Kazutoshi Ogawa
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Publication number: 20130105911Abstract: A semiconductor device includes a first conductivity type base formed on a surface of a substrate, a second conductivity type emitter formed on a surface of the base, a second conductivity type doped region which, along with accepting a first type of carrier from the emitter, injects the first type of carrier into the base, and is arranged to be spaced apart on the surface of the base from the emitter, and a second conductivity type collector which is formed on an opposite side to the emitter and the doped region, interposing the base.Type: ApplicationFiled: October 19, 2012Publication date: May 2, 2013Applicant: SONY CORPORATIONInventor: SONY CORPORATION
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Patent number: 8432015Abstract: A semiconductor device (2) includes: a FLR (65) that is disposed on a semiconductor substrate so as to divide the semiconductor substrate into an inner region and an outer region; a first bonding pad (24a to 24d) that is disposed in the inner region and is connected to an external circuit by a wire (14a to 14d) whose one end is connected to the external circuit; and a second bonding pad (26a to 26d) that is disposed in the outer region and on which the other end of the wire is bonded.Type: GrantFiled: September 12, 2008Date of Patent: April 30, 2013Assignee: Toyota Jidosha Kabushiki KaishaInventor: Hiroaki Tanaka
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Publication number: 20130093023Abstract: A semiconductor device includes a first insulated gate field effect transistor, a second insulated gate field effect transistor, a bipolar transistor, a first element isolation structure formed on a main surface above a pn junction formed between an emitter region and a base region, a second element isolation structure formed on the main surface above a pn junction formed between the base region and a collector region, and a third element isolation structure formed on the main surface opposite to the second element isolation structure relative to the collector region, in which the semiconductor device further includes a bipolar dummy electrode formed on at least one of the first element isolation structure, the second element isolation structure and the third element isolation structure and having a floating potential.Type: ApplicationFiled: June 24, 2010Publication date: April 18, 2013Applicant: Renesas Electronics CorporationInventor: Keiichi Yamada
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Publication number: 20130075829Abstract: An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Applicant: NUVOTON TECHNOLOGY CORPORATIONInventor: Ming-Fang LAI
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Publication number: 20130075741Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: ALPHA AND OMEGA SEMICONDUCTOR INC.Inventors: Shekar Mallikarjunaswamy, François Hébert
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Patent number: 8405157Abstract: The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.Type: GrantFiled: March 26, 2008Date of Patent: March 26, 2013Assignee: X-FAB Semiconductor Foundries AGInventors: Thomas Uhlig, Felix Fuernhammer, Christoph Ellmers