Contact Of Refractory Or Platinum Group Metal (e.g., Molybdenum, Tungsten, Or Titanium) Patents (Class 257/383)
  • Patent number: 10629492
    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Patent number: 10615078
    Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 7, 2020
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., LAM RESEARCH CORPORATION
    Inventors: Georges Jacobi, Vimal K. Kamineni, Randolph F. Knarr, Balasubramanian Pranatharthiharan, Muthumanickam Sankarapandian
  • Patent number: 10615281
    Abstract: A semiconductor device includes a plurality of semiconductor layers formed on a plurality of fin structures, an epitaxial layer formed on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, a gate structure formed on the plurality of semiconductor layers, and a wrap around contact formed on the epitaxial layer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas Jean Loubet
  • Patent number: 10573724
    Abstract: A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10535606
    Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 14, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Takashi Ando, Hiroaki Niimi, Tenko Yamashita
  • Patent number: 10403552
    Abstract: Methods herein may include forming trenches in a stack of layers atop a substrate, and forming a gate dielectric within the trenches. Methods may further include forming a first work function (WF) metal atop the gate dielectric, and forming a capping layer over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches. The first WF metal may be removed from just a first trench of the trenches, and a second WF metal is then formed over the stack of layers, wherein the second WF metal is formed atop the gate dielectric within the first trench. An angled ion etch may then be performed to recess the gate dielectric and the second WF metal within the first trench, and to recess the gate dielectric and the first WF metal within a second trench. A gate metal may then be formed within the trenches.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 3, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Patent number: 10374038
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I Kuo, Chii-Horng Li, Chia-Ling Chan, Li-Li Su, Yi-Fang Pai, Wei Te Chiang, Shao-Fu Fu, Wei Hao Lu
  • Patent number: 10340219
    Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seul Ki Hong, Heon Jong Shin, Hwi Chan Jun, Min Chan Gwak
  • Patent number: 10217868
    Abstract: Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Zuoguang Liu, Chun W. Yeung
  • Patent number: 10170573
    Abstract: A semiconductor device includes a substrate, a metal gate on the substrate, and a first inter-layer dielectric (ILD) layer around the metal gate. A top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate. A mask layer is disposed in the recessed region. A void is formed in the mask layer within the recessed region. A second ILD layer is disposed on the mask layer and the first ILD layer. A contact hole extends into the second ILD layer and the mask layer. The contact hole exposes the top surface of the metal gate and communicates with the void. A conductive layer is disposed in the contact hole and the void.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: January 1, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ting Chiang, Jie-Ning Yang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, I-Fan Chang, Jui-Ming Yang, Wen-Tsung Chang
  • Patent number: 10109494
    Abstract: A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 23, 2018
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventor: Simon Ruffell
  • Patent number: 10032399
    Abstract: A system and method for determining and applying characterization correlation curves for aging effects on an organic light organic light emitting device (OLED) based pixel is disclosed. A first stress condition is applied to a reference pixel having a drive transistor and an OLED. An output voltage based on a reference current is measured periodically to determine an electrical characteristic of the reference pixel under the first predetermined stress condition. The luminance of the reference pixel is measured periodically to determine an optical characteristic of the reference pixel. A characterization correlation curve corresponding to the first stress condition including the determined electrical and optical characteristic of the reference pixel is stored. The stress condition of an active pixel is determined and a compensation voltage is determined by correlating the stress condition of the active pixel with curves of the predetermined stress conditions.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 24, 2018
    Assignee: Ignis Innovation Inc.
    Inventors: Gholamreza Chaji, Javid Jaffari, Arokia Nathan
  • Patent number: 10026824
    Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Andre Labonte, Ruilong Xie, Lars Liebmann, Nigel Cave, Guillaume Bouche
  • Patent number: 10020400
    Abstract: Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Zuoguang Liu, Chun W. Yeung
  • Patent number: 9773441
    Abstract: A system and method for determining and applying characterization correlation curves for aging effects on an organic light organic light emitting device (OLED) based pixel is disclosed. A first stress condition is applied to a reference pixel having a drive transistor and an OLED. An output voltage based on a reference current is measured periodically to determine an electrical characteristic of the reference pixel under the first predetermined stress condition. The luminance of the reference pixel is measured periodically to determine an optical characteristic of the reference pixel. A characterization correlation curve corresponding to the first stress condition including the determined electrical and optical characteristic of the reference pixel is stored. The stress condition of an active pixel is determined and a compensation voltage is determined by correlating the stress condition of the active pixel with curves of the predetermined stress conditions.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 26, 2017
    Assignee: Ignis Innovation Inc.
    Inventors: Gholamreza Chaji, Javid Jaffari, Arokia Nathan
  • Patent number: 9741858
    Abstract: The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42).
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: August 22, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaowen Lv, Chihyu Su, Yanhong Meng, Wenlin Mei
  • Patent number: 9716226
    Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 25, 2017
    Assignee: Intel Corporation
    Inventors: F. Daniel Gealy, Andrea Gotti, Davide Colombo, Kuo-Wei Chang
  • Patent number: 9673293
    Abstract: Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 6, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Zuoguang Liu, Chun W. Yeung
  • Patent number: 9627510
    Abstract: A method for fabricating a semiconductor device comprises forming a dummy gate on a substrate; forming spacers at opposing sides of the dummy gate; depositing a sacrificial interlayer dielectric over the dummy gate; planarizing the interlayer dielectric to expose the dummy gate; removing the dummy gate; forming a replacement metal gate with a protective cap between the spacers and on the substrate to replace the removed dummy gate; removing the sacrificial interlayer dielectric; siliciding exposed areas of the substrate adjacent to the replacement metal gate; depositing a final interlayer dielectric over the replacement metal gate and the exposed silicided areas; and forming vias through the final interlayer dielectric to the silicided areas.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Sivananda K. Kanakasabapathy
  • Patent number: 9543515
    Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: F. Daniel Gealy, Andrea Gotti, Davide Colombo, Kuo-Wei Chang
  • Patent number: 9502307
    Abstract: An approach to forming a semiconductor structure with improved negative bias temperature instability includes forming an interfacial layer on a semiconductor substrate with an nFET and a pFET. The approach includes depositing a gate dielectric layer on the interfacial layer. Additionally, the approach includes an nFET work function metal layer deposited on the interfacial layer. Additionally, the approach includes removing the nFET work function metal from an area above the pFET and depositing a pFET work function metal layer on a portion of the exposed gate dielectric layer where the portion of the exposed gate dielectric layer is over the pFET. Furthermore, the approach includes depositing a gate metal on the pFET work function metal layer where the gate metal is deposited in an environment with a fluorine containing gas followed by an anneal in a reducing environment.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan
  • Patent number: 9419083
    Abstract: A field effect transistor structure having a semiconductor having a source region, a drain region, and a gate contact region disposed between the source region and the drain region; and a gate electrode having a stem section extending from a top section of the gate electrode to, and in Schottky contact with, the gate contact region. The stem section has an upper portion terminating at the top portion of the gate electrode and a bottom portion narrower than the upper portion, the bottom portion terminating at the gate contact region. The bottom portion of the stem has a step between the upper portion of the stem section and the bottom portion of the stem section in only one side of the stem section. The step of the stem section provides an asymmetric field plate for the field effect transistor.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: August 16, 2016
    Assignee: Raytheon Company
    Inventors: John P. Bettencourt, Eduardo M. Chumbes
  • Patent number: 9418908
    Abstract: A wafer processing method includes a first correction step of measuring a distance “a” between a first cut groove previously formed by a first cutting unit and a division line for the next cut groove, and correcting an actual index amount by using a deviation “b” of the first cutting unit equivalent to the difference between the distance “a” and a proper index amount of the first cutting unit, and a second correction step of forming a measurement groove by using a second cutting unit along the division line for the next cut groove, measuring a distance “c” between the first cut groove and the measurement groove, and correcting an actual index amount of the second cutting unit by using a deviation “d” equivalent to the difference between the distance “c” and a proper index amount of the second cutting unit during the cutting step.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: August 16, 2016
    Assignee: DISCO CORPORATION
    Inventors: Makoto Tanaka, Xin Lu, Sax Liao
  • Patent number: 9412659
    Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 9, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Hui Zang
  • Patent number: 9153446
    Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: October 6, 2015
    Assignee: SK Hynix Inc.
    Inventors: Se-Aug Jang, Hong-Seon Yang, Ja-Chun Ku, Seung-Ryong Lee
  • Patent number: 9111864
    Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya Hui Chang
  • Patent number: 9082850
    Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: July 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Na-Ra Kim, Seung-Hwan Kim, Sung-Hee Lee, Dae-Sin Kim, Ji-Young Kim, Dong-Soo Woo
  • Patent number: 9059134
    Abstract: A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located thereon. Each gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ravikumar Ramachandran, Ramachandra Divakaruni, Ying Li
  • Patent number: 9041154
    Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 26, 2015
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Chien-An Yu, Chih-Huang Wu
  • Patent number: 9035395
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: May 19, 2015
    Assignee: MONOLITH SEMICONDUCTOR, INC.
    Inventors: Kevin Matocha, Kiran Chatty, Larry Rowland, Kalidas Chatty
  • Publication number: 20150129976
    Abstract: A semiconductor device includes a substrate, an epi-layer, an etch stop layer, an interlayer dielectric (ILD) layer, a silicide layer cap and a contact plug. The substrate has a first portion and a second portion neighboring to the first portion. The etch stop layer is disposed on the second portion. The ILD layer is disposed on the etch stop layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the ILD layer.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Chih-Fu Chang, Jen-Pan Wang
  • Publication number: 20150115354
    Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Winfried Kaindl, Franz Hirler, Armin Willmeroth
  • Patent number: 9013002
    Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: David James Spry
  • Publication number: 20150102422
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.
    Type: Application
    Filed: November 24, 2014
    Publication date: April 16, 2015
    Inventors: Xiuyu Cai, Ruilong Xie, Ali Khakifirooz, Kangguo Cheng
  • Patent number: 8994118
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: March 31, 2015
    Assignee: Monolith Semiconductor, Inc.
    Inventors: Kevin Matocha, Kiran Chatty, Larry Rowland, Kalidas Chatty
  • Patent number: 8981495
    Abstract: A transistor includes a substrate, a gate over the substrate, a source and a drain over the substrate on opposite sides of the gate, a first silicide on the source, and a second silicide on the drain. Only one of the drain or the source has an unsilicided region adjacent to the gate to provide a resistive region.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Lee-Wee Teo, Ming Zhu
  • Patent number: 8981565
    Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Dong-Ick Lee, Ahmet Serkan Ozcan, Zhen Zhang
  • Patent number: 8946007
    Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
  • Publication number: 20150008532
    Abstract: A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Inventor: Manoj Mehrotra
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Publication number: 20140346611
    Abstract: A semiconductor device may include a voltage supply unit suitable for supplying a voltage, a first conductive line coupled to the voltage supply unit, a second conductive line formed over the first conductive line, a voltage contact plug formed over the second conductive line, a voltage transmission line formed over the voltage contact plug, and a switching element suitable for switching the voltage transferred from the voltage transmission line.
    Type: Application
    Filed: October 24, 2013
    Publication date: November 27, 2014
    Applicant: SK hynix Inc.
    Inventor: Sung Lae OH
  • Patent number: 8883654
    Abstract: The present arrangement provides a method of treating an oxidized layer of metal nitride, including oxidizing a layer (2) of metal oxide at the surface of a first layer (1) of nitride of said metal using a plasma of an oxidizing species with an oxidation number that is greater than that of oxygen in order to form a metallic layer (3) of a compound based on said metal; and reducing the metallic layer (3) formed in step i) using a plasma of hydrogen and nitrogen to form a second layer (4) of nitride of said metal.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: November 11, 2014
    Assignee: Altis Semiconductor
    Inventors: Michel Aube, Pierre De Person
  • Patent number: 8860147
    Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Howard Tigelaar, Victor Sutcliffe
  • Patent number: 8847325
    Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 30, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • Patent number: 8823088
    Abstract: A semiconductor device includes a first region and a second region, a buried gate arranged in the first region, and an oxidation prevention barrier surrounding the first region.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Se-Aug Jang
  • Patent number: 8816449
    Abstract: An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: August 26, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corp., Semiconductor Manufacturing International (Beijing) Corp.
    Inventor: Tzu-Yin Chiu
  • Patent number: 8816439
    Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: August 26, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 8796772
    Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Jeng-Ya D. Yeh, Peter J. Vandervoorn, Walid M. Hafez, Chia-Hong Jan, Curtis Tsai, Joodong Park
  • Patent number: 8786026
    Abstract: A semiconductor device, comprising a substrate, a plurality of polysilicon portions formed on the substrate, wherein the polysilicon portions are spaced apart from each other, a plurality of source/drain regions formed in the substrate between adjacent polysilicon portions, and a dielectric layer formed on the polysilicon portions and on the source/drain regions, wherein the dielectric layer includes a cavity filled with conductive material to form a contact area, the contact area overlapping part of a source/drain region and part of a polysilicon portion to electrically connect the polysilicon portion with the source/drain region, and wherein part of the contact area extends below an upper surface of the substrate to contact an implant region with the same doping as the source/drain region. The implant region is next to the source/drain region and includes part of a channel region in the substrate under the polysilicon portion.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mukyeng Jung, No Young Chung, Kyung Woo Kim
  • Patent number: RE45060
    Abstract: The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lee-Wee Teo, Ming Zhu, Hui-Wen Lin, Bao-Ru Young, Harry-Hak-Lay Chuang