With Means To Reduce Parasitic Capacitance Patents (Class 257/386)
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Publication number: 20090020830Abstract: Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).Type: ApplicationFiled: October 9, 2007Publication date: January 22, 2009Inventors: Brent A. Anderson, Andres Bryant, William F. Clark, JR., Edward J. Nowak
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Publication number: 20080308878Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262).Type: ApplicationFiled: October 31, 2007Publication date: December 18, 2008Inventor: Constantin Bulucea
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Publication number: 20080251858Abstract: A field effect transistor having a T- or ?-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.Type: ApplicationFiled: May 19, 2008Publication date: October 16, 2008Inventors: Ho Kyun AHN, Jong Won LIM, Jae Kyoung MUN, Hong Gu JI, Woo Jin CHANG, Hea Cheon KIM
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Publication number: 20080224233Abstract: An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the source region with a channel (5) therefrom, —an active gate (8) overlying the channel and insulated from the channel by a first dielectric material (9) forming the gate oxide of the IGFET device, —a dummy gate (10) positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.Type: ApplicationFiled: October 12, 2005Publication date: September 18, 2008Applicant: ACCOInventor: Denis Masliah
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Patent number: 7420241Abstract: A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode anType: GrantFiled: November 21, 2005Date of Patent: September 2, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Takamitsu Ishihara
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Patent number: 7420260Abstract: A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region.Type: GrantFiled: May 6, 2005Date of Patent: September 2, 2008Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Tae-hun Kwon, Cheol-joong Kim, Young-sub Jeong
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Publication number: 20080197423Abstract: A device comprises a first means for separating a conductive layer from a semiconductor substrate and a second means for reducing a voltage dependent capacitive coupling between the conductive layer and the semiconductor substrate.Type: ApplicationFiled: February 15, 2007Publication date: August 21, 2008Applicant: Infineon Technologies AGInventor: Klaus-Guenter Oppermann
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Publication number: 20080191250Abstract: A transistor having an electrode layer that can reduce or prevent a coupling effect, a fabricating method thereof, and an image sensor having the same are provided. The transistor includes a semiconductor substrate and a well of a first conductivity type formed on the semiconductor substrate. A heavily-doped first impurity region of a first conductivity type surrounds an active region defined in the well. Heavily-doped second and third impurity regions of a second conductivity type are spaced apart from each other in the active region an define a channel region interposed therebetween. A gate is formed over the channel region to cross the active region. The gate overlaps at least a portion of the first impurity region and receives a first voltage. An electrode layer is formed between the semiconductor substrate and the gate, such that the electrode layer overlaps a portion of the first impurity region contacting the channel region and receives a second voltage.Type: ApplicationFiled: December 21, 2007Publication date: August 14, 2008Inventors: Kang-Bok Lee, Jong-Cheol Shin
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Publication number: 20080185662Abstract: A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.Type: ApplicationFiled: April 3, 2008Publication date: August 7, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Haining Yang
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Publication number: 20080111197Abstract: A MISFET includes source/drain regions each including a plurality of divided substrate regions divided by intervening insulation films, and a selectively-grown silicon layer formed on the divided substrate regions and intervening insulation film to electrically couple together the divided substrate regions. The resultant MISFET has a reduced junction capacitance across the p-n junction of the source/drain regions, to improve the operation speed of the MISFET.Type: ApplicationFiled: November 2, 2007Publication date: May 15, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Noriaki MIKASA
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Patent number: 7335956Abstract: A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor device, without occupying an extra layout area.Type: GrantFiled: February 11, 2005Date of Patent: February 26, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-You Chen, Chung-Long Chang, Chih-Ping Chao, Chun-Hong Chen
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Patent number: 7288817Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.Type: GrantFiled: January 12, 2005Date of Patent: October 30, 2007Assignee: Micron Technology, Inc.Inventors: Werner Juengling, Richard H. Lane
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Patent number: 7282772Abstract: Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.Type: GrantFiled: January 11, 2006Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7233515Abstract: An integrated memory arrangement based on resistive memory cells that can be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having an electrical additional capacitance that increases its capacitance, and to a production method.Type: GrantFiled: August 23, 2005Date of Patent: June 19, 2007Assignee: Infineon Technologies AGInventor: Thomas Rohr
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Patent number: 7205618Abstract: A semiconductor device includes a silicon substrate, a channel region formed in a surface of the silicon substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, first gate side walls formed on the gate insulating film to sandwich the gate electrode in a gate length direction, second gate side walls which sandwich the gate electrode and the first gate side wall, first diffused layers formed on the surface of the silicon substrate to sandwich the channel region, second diffused layers which sandwich the channel region and the first diffused layer and have a larger depth than that of the first diffused layer, and low resistance layers which are formed between the first diffused layer and the second gate side wall and contain nitride, boride or carbide of Ti, Zr, Hf or Ta.Type: GrantFiled: February 8, 2005Date of Patent: April 17, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Akira Nishiyama, Yuuichi Kamimuta
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Patent number: 7161199Abstract: A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.Type: GrantFiled: August 24, 2004Date of Patent: January 9, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Jian Chen, Michael A. Mendicino, Vance H. Adams, Choh-Fei Yeap, Venkat R. Kolagunta
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Patent number: 7119393Abstract: A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type region forming a channel therein. A floating gate is disposed above and insulated from the channel. A control gate is disposed above and insulated from the floating gate. An isolation trench disposed in the p-type region and surrounding the source and drain regions, the isolation trench extending down into the n-type region. The substrate, the n-type region and the p-type region each biased such that the p-type region is fully depleted.Type: GrantFiled: July 28, 2003Date of Patent: October 10, 2006Assignee: Actel CorporationInventor: John McCollum
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Patent number: 7115957Abstract: A transistor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain.Type: GrantFiled: November 9, 2001Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Chandra Mouli
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Patent number: 7034347Abstract: There is provided a charge detecting device that can convert an accumulated charge to a voltage at a low voltage and a high efficiency, and has a large dynamic range of an output voltage and satisfactory linearity of a conversion efficiency. The charge detecting device includes a charge accumulating portion including a low concentration N-type (N?) layer 108 formed in a P-type well 101 and a high concentration N-type (N+) layer formed between the N? layer and a principal surface. The N+ layer is connected to an input terminal of an amplifying transistor of an output circuit, and after a reverse bias is applied to the N+ layer during discharging of the accumulated charge, the entire N? layer is depleted at least until a saturated charge is accumulated.Type: GrantFiled: March 3, 2004Date of Patent: April 25, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshihiro Kuriyama
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Patent number: 7023059Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.Type: GrantFiled: March 1, 2004Date of Patent: April 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Darin A. Chan, Simon Siu-Sing Chan, Jeffrey P. Patton, Jacques J. Bertrand
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Patent number: 6995434Abstract: A semiconductor device capable of suppressing increase of the capacitance while suppressing a thin-line effect of a silicide film is obtained. This semiconductor device comprises a first silicon layer formed on a semiconductor substrate through a gate insulator film with an upper portion and a lower portion larger in width than a central portion for serving as a gate electrode and a first silicide film formed on the first silicon layer for serving as the gate electrode.Type: GrantFiled: September 29, 2003Date of Patent: February 7, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Ryosuke Usui, Kazuhiro Sasada
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Patent number: 6992355Abstract: The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.Type: GrantFiled: September 2, 2003Date of Patent: January 31, 2006Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 6951621Abstract: The invention relates to a method for forming a product sensor, and a product sensor. The product sensor is formed on a substrate and provided with at least one electric circuit comprising at least one capacitor and at least one coil. At least part of the electric circuit is formed by evaporating a first metallization layer at least at the electric circuit in the product sensor.Type: GrantFiled: September 19, 2002Date of Patent: October 4, 2005Assignee: Rafsec OyInventor: Marko Hanhikorpi
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Patent number: 6906419Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.Type: GrantFiled: June 19, 2001Date of Patent: June 14, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Nitta, Yoshiaki Fukuzumi, Yusuke Kohyama
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Patent number: 6891232Abstract: A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.Type: GrantFiled: January 30, 2003Date of Patent: May 10, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Kiyotaka Miyano, Kazuya Ohuchi, Ichiro Mizushima
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Patent number: 6891223Abstract: Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.Type: GrantFiled: March 19, 2003Date of Patent: May 10, 2005Assignee: Infineon Technologies AGInventors: Joachim Krumrey, Franz Hirler, Ralf Henninger, Martin Pölzl, Walter Rieger
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Patent number: 6864547Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a channel region located in a semiconductor substrate and a trench located adjacent a side of the channel region. The semiconductor device further includes an isolation structure located in the trench, and a source/drain region located over the isolation structure.Type: GrantFiled: June 15, 2001Date of Patent: March 8, 2005Assignee: Agere Systems Inc.Inventors: John A. Michejda, Ian Wylie
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Patent number: 6815771Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.Type: GrantFiled: October 25, 2002Date of Patent: November 9, 2004Assignee: Kawasaki Microelectronics, Inc.Inventor: Yoshitaka Kimura
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Patent number: 6806172Abstract: Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.Type: GrantFiled: April 5, 2001Date of Patent: October 19, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Christy Mei-Chu Woo, Eric N. Paton, Susan Tover
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Patent number: 6794722Abstract: A p−−-type impurity layer is provided at a position located below n−-type impurity layers which are to become the drain of a MOSFET. Although the p−−-type impurity layer is of the same conductivity type as a semiconductor substrate, the p−−-type impurity layer is lower in doping level than the semiconductor substrate. The p−−-type impurity layer is formed so as to be joined to an n−-type impurity layer and such that the dosage of p-type impurity (i.e., the amount of included impurity) becomes higher with increasing distance from the thus-formed junction. The dosage of the area located in the vicinity of the junction is made lower, thereby rendering a depletion layer easy to spread when a drain voltage is applied. Thus, capacitance Cds developing between the drain and the substrate is reduced, and the operating speed of the MOSFET increases.Type: GrantFiled: December 10, 2002Date of Patent: September 21, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Koichi Fujita
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Patent number: 6787862Abstract: The present invention relates to a gas insulated gate field effect transistor and a fabricating method thereof which provides an improved insulator between the gate and the source-drain channel of a field effect transistor. The insulator is a vacuum or a gas filled trench. As compared to a conventional MOSFET, the gas insulated gate device provides reduced capacitance between the gate and the source/drain region, improved device reliability and durability, and improved isolation from interference caused by nearby electric fields. The present invention includes the steps of forming a doped source region and drain region on a substrate, forming a gate, forming a gaseous gate insulating trench and forming terminals upon the gate, the source region and the drain region. A plurality of the devices on a single substrate may be combined to form an integrated circuit.Type: GrantFiled: December 19, 2002Date of Patent: September 7, 2004Inventor: Mark E. Murray
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Patent number: 6787841Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.Type: GrantFiled: August 29, 2003Date of Patent: September 7, 2004Assignee: Hitachi, Ltd.Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
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Patent number: 6770929Abstract: A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.Type: GrantFiled: November 2, 2001Date of Patent: August 3, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Rana P. Singh, Paul A. Ingersoll
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Patent number: 6765268Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrodeType: GrantFiled: November 12, 2002Date of Patent: July 20, 2004Assignee: Renesas Technology CorpInventors: Hitoshi Akamine, Masashi Suzuki, Masao Yamane, Tetsuaki Adachi
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Patent number: 6756644Abstract: A MOSFET gate electrode is interrupted from extending across a common conduction region, thereby reducing gate capacitance. The reduced gate capacitance provides very low gate-to-drain charge, QGD, and very low gate-to-source charge, QGS. The gate electrode is supported by and is in effect or is actually interrupted by an oxide block over a common conduction area. The MOSFET can be formed by methods including: patterning oxide blocks on a substrate; providing gate electrode material in and over appropriate gaps between the oxide blocks; removing excess gate material; and forming oxide layers around the gate electrode material. Oxide blocks can alternately be patterned to permit gate electrodes to be formed directly between the oxide blocks. The reduced gate capacitance reduces switching delays while permitting minimum RDSON values.Type: GrantFiled: March 21, 2002Date of Patent: June 29, 2004Assignee: International Rectifier CorporationInventor: Jonathan Stout
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Patent number: 6740884Abstract: A radiation detector includes a top gate thin film transistor (TFT) including a source electrode, a drain electrode, a gate electrode, a first dielectric layer, and a second dielectric layer, wherein the second dielectric layer is extending over a surface of the first dielectric layer. The radiation detector also includes a capacitor that includes at least two electrodes and a dielectric layer. The capacitor dielectric layer is formed unitarily with the TFT second dielectric layer.Type: GrantFiled: April 3, 2002Date of Patent: May 25, 2004Assignee: General Electric CompanyInventors: Ji Ung Lee, Douglas Albagli, George Edward Possin, Ching-Yeu Wei
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Publication number: 20040061185Abstract: An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.Type: ApplicationFiled: September 27, 2002Publication date: April 1, 2004Inventors: Brian Doyle, Jack Kavalieros
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Patent number: 6696354Abstract: A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first thermal treatment is performed to make the portions of the metal layer react with the silicon in the gate and the source/drain to form a salicide. Then, any unreacted metal and the spacer are removed. An ion containing silicon is introduced into the source/drain. Finally, a second thermal treatment is performed.Type: GrantFiled: April 25, 2002Date of Patent: February 24, 2004Assignee: Silicon Integrated Systems Corp.Inventor: Chao-Yuan Huang
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Patent number: 6693335Abstract: A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.Type: GrantFiled: September 1, 1998Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Chandra Mouli
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Patent number: 6690062Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.Type: GrantFiled: March 19, 2003Date of Patent: February 10, 2004Assignee: Infineon Technologies AGInventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Poelzl
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Patent number: 6686059Abstract: A semiconductor device having a reduced overlap capacity between a gate electrode and extensions. Specifically, a stacked structure made up of a polysilicon film, tungsten silicide film, and silicon nitride film is partially formed in first and second regions of a silicon substrate, respectively. Sidewall oxide films are formed on side surfaces of the polysilicon films in the first and second regions, respectively. A width of the sidewall of the first structure is smaller than a width of the sidewall of the second structure such that an overlap amount between a second conductive layer and a second impurity region is smaller than an overlap amount between a first conductive layer and a first impurity region.Type: GrantFiled: September 24, 2001Date of Patent: February 3, 2004Assignee: Renesas Technology Corp.Inventor: Masayoshi Shirahata
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Patent number: 6686636Abstract: A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap.Type: GrantFiled: November 9, 2001Date of Patent: February 3, 2004Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Chandra Mouli
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Patent number: 6683355Abstract: A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap.Type: GrantFiled: November 9, 2001Date of Patent: January 27, 2004Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Chandra Mouli
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Patent number: 6680543Abstract: A semiconductor integrated circuit 10 includes a semiconductor substrate 1, an insulating layer 2 formed on the semiconductor substrate 1, and a bonding pad 3 formed on the insulating layer 2. The semiconductor substrate 1 has a region 4 facing the bonding pad 3 and a region 5 substantially surrounding at least a part of the region 4. The region 5 of the semiconductor substrate 1 is set substantially at an equipotential.Type: GrantFiled: September 9, 1999Date of Patent: January 20, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Jyoji Hayashi, Hiroshi Kimura, Hiroshi Shimomura
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Patent number: 6674117Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.Type: GrantFiled: July 27, 2001Date of Patent: January 6, 2004Assignee: Hitachi, Ltd.Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
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Patent number: 6639288Abstract: A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high adhesive strength to the gate insulating film is disposed. The polysilicon side wall (5) is brought into a close contact with the tungsten nitride (6b) on the side surface of the tungsten (6c). With this structure improved is adhesive strength of a metal wire or a metal electrode which is formed on an insulating film of a semiconductor device.Type: GrantFiled: June 19, 2000Date of Patent: October 28, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tatsuya Kunikiyo
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Patent number: 6639264Abstract: A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer. In addition, an integrated circuit structure is provided. The structure comprises a substrate having a gate dielectric layer on the substrate and a gate conductor on the substrate above the gate dielectric layer. The gate conductor further comprises an edge and a solid state source of fluorine in close proximity to the gate dielectric layer.Type: GrantFiled: December 11, 1998Date of Patent: October 28, 2003Assignee: International Business Machines CorporationInventor: Stephen K. Loh
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Patent number: 6633070Abstract: A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode and the silicon layers and contain respective voids.Type: GrantFiled: September 18, 2001Date of Patent: October 14, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Naruhisa Miura, Toshiyuki Oishi, Yuji Abe, Kohei Sugihara
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Patent number: 6630715Abstract: A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal level covers the full width of the device and takes current out of the source in a primarily vertical direction.Type: GrantFiled: October 1, 2001Date of Patent: October 7, 2003Assignee: International Business Machines CorporationInventors: Scott M. Parker, Steven J. Tanghe
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Patent number: 6603180Abstract: A semiconductor device having a large-area silicide layer and fabrication method is provided. A semiconductor device, consistent with one embodiment of the invention, includes a silicon substrate, a gate insulating layer disposed over the silicon substrate, a gate electrode disposed over the gate insulating layer, and at least one active region disposed adjacent the gate electrode. Formed over the active region and in contact with the insulating layer is a silicide layer. The active region may, for example, be a source/drain region. The silicide layer generally has a surface area which is larger than that of conventional silicide layers. This, for example, reduces the resistance of the active regions of the semiconductor device and enhances device performance.Type: GrantFiled: November 28, 1997Date of Patent: August 5, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Mark I Gardner, H. Jim Fulford