Abstract: A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. Spacers are formed around the gate structures, although little or no spacer forms around the isolation pad.

Abstract: A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.

Abstract: An IC isolation structure includes a recess disposed in a conductive layer having a surface portion. The recess has a side wall adjacent to the surface portion, and the isolation structure also includes an insulator disposed in the recess and overlapping the surface portion. Thus, if a transistor is disposed in the conductive layer adjacent to the recess side wall, the overlapping portion of the insulator increases the distance between the upper recess corner and the gate electrode. This increased distance reduces hump effects to tolerable levels.

Abstract: A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. Spacers are formed around the gate structures, although little or no spacer forms around the isolation pad.

Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: A semiconductor apparatus of the type includes a plurality of semiconductor devices arranged in a matrix and each having a principal electrode, an insulating layer coating the semiconductor devices, and a plurality of pixel electrodes (conductor film patterns) each disposed on the insulating film and connected to the principal electrode of semiconductor device through a contact hole formed in the insulating layer.

Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.

Abstract: A method is provided for forming a copper interconnect, the method including forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first copper structure in the first opening. The method also includes forming a sacrificial dielectric layer above the first dielectric layer and above the first copper structure, forming a second opening in the sacrificial dielectric layer above at least a portion of the first copper structure, and forming a second copper structure in the second opening, the second copper structure contacting the at least the portion of the first copper structure. The method further includes removing the sacrificial dielectric layer above the first dielectric layer and adjacent the second copper structure, and forming the copper interconnect by annealing the second copper structure and the first copper structure.

Abstract: Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolation partially surrounds each transistor so as to further electrically isolate the source and drain regions from the semiconductor body. Typically for a single transistor only one surface of each drain and source region make direct contact to the semiconductor body and these surfaces are on opposite sides of a channel region of each transistor. One method of fabrication of the source and drain regions is to form an isolating isolation region around active areas in which a transistor is to be formed in a semiconductor body. Trenches separated by portions of the body are then formed in the active areas in which transistors are to be formed. On bottom surfaces of the trenches are formed an electrically insulating layer.

Abstract: A semiconductor device includes a substrate, a plurality of active regions on the substrate, the active regions having recessed and elevated types and being alternatively in parallel with the substrate, respectively, and a plurality of first and second field insulating layers at field regions adjacent to the active regions, the first field insulating layer being parallel with the substrate and the second field insulating layer being perpendicular to the substrate.

Abstract: The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

Abstract: The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.

Abstract: A high-voltage element (H)to which a high gate voltage is applied, and a low-voltage element (L) to which a low gate voltage is applied, are formed in a semiconductor substrate (1). Bird's beaks (8, 18) are formed in gate insulating films (7, 17) by thermal oxidation. Since a gate electrode (9) of the element (H) has a shorter gate length than a gate electrode (19) of the element (L), the ratio of the bird's beak in the gate insulating films (7, 17) is small in the element (L) and large in the element (H). Therefore, the element (H) has a high breakdown voltage and less aged deterioration, leading to long lifetime. The element (L) has a high current driving capability to produce high-speed operation. Thus, long lifetime, high operation speed and easy manufacturing steps are realized at the same time.

Abstract: A read-only memory cell array has vertical MOS transistors formed on trench walls, and is programmed with a programming mask which covers only the areas at which a transistor is not to be produced. As a result, the word lines can be formed with minimum grid spacing and the risk of short-circuiting between adjacent word lines is eliminated by buried ploy stringers.

Abstract: N+ or P+ diffusions are formed in a lightly doped P type or N type starting wafer. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches between the P+ (or N+) diffusions. The trenches extend through the thin device layer to a predefined depth and are filled with a dielectric and with polysilicon to dielectrically insulate each of the tubs. At least one diffusion of each cell is connected to a diffusion of an adjacent cell to connect each of a predetermined number of the cells. The N+ or (P+) diffusions may be each enclosed by a ring shaped P+ or N+ contact diffusion. An MOS-gated device may be integrated into the same chip and may be a lateral or vertical MOSFET or a lateral or vertical IGBT.

Abstract: A method of fabricating a shallow trench isolation. A trench is formed in a substrate. An insulation plug is formed to fill the trench. The trench has an exposed upper portion above the substrate. A silicon spacer is formed on a side wall of the exposed upper portion. The silicon spacer is oxidized into a silicon oxide spacer.

Abstract: There is provided a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than a CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.

Abstract: This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure. The double gate-oxide structure includes a thick-oxide-layer covering walls of the trench below an upper portion of the trench and a thin-gate-oxide covering walls of the upper portion of the trench thus defining a champagne-glass shaped gate in the trench. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate surrounding a top portion of the trench. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate surrounding the trench and encompassing the source region.

Abstract: A high-voltage device. A first well region with a first conductive type is located in a substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.

Abstract: A silicon on insulator (SOI) wafer is formed with an unoxidized perforation in the insulating silicon dioxide buried oxide layer. A field effect transistor (FET) structure on the SOI wafer is located above the unoxidized perforation such that the unoxidized perforation provides for electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the FET includes masking a silicon wafer prior to an oxygen implantation process to form the unoxidized perforated buried oxide layer in the wafer.

Abstract: A programmable memory device having slot trenches (14). A plurality of floating gates (22) are separated from a surface of semiconductor body (10) by a gate dielectric (24). A plurality of slot trenches (14) isolate memory cells (12) from each other. Each of the slot trenches (14) extends below the surface of the semiconductor body (10) between adjacent floating gates (22). A control gate (20) extends over the floating gates (22) and a portion of each of the slot trenches (14).

Abstract: A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to define portions of the dielectric layers that will be removed in an etch step to create voids to the surface of the semiconductor substrate. Subsequently, epitaxially growth is employed to form active regions within the voids that were previously formed. Transistors are then formed in and on the active regions and are subsequently interconnected to form an integrated circuit.

Abstract: A trench DMOS device has a gate insulating layer on the bottom and sidewalls of the trench. The upper edges of the trench have an impurity injection region and are rounded. In addition, a first conductive layer is formed on the gate insulating layer, and a second conductive layer is formed on the first conductive layer and filled in the trench. The second conductive layer has different crystallization from the first conductive layer. As such the first conductive layer acts as a buffer between the gate insulating layer and the filled in second conductive layer. A method for fabricating a trench DMOS device includes the steps of forming an epitaxial layer on a semiconductor substrate. Then an impurity is injected into the epitaxial layer to form an impurity injection region. Then a trench is formed in the semiconductor substrate passing through the impurity injection region. Then a dry etching process is used to round the upper edges of the trench.

Abstract: A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.

Abstract: In a semiconductor device and a method of manufacturing the same, a dummy region which can suppress occurrence of a parasitic capacity can be provided for reducing a difference in level without increasing manufacturing steps in number. A semiconductor substrate is provided at its main surface with an isolation region formed by a trench, and a dummy region leaving the main surface is formed in the isolation region for the purpose of reducing an influence by the difference in level in a later step. The dummy region includes p- and n-type impurity regions each extending a predetermined depth from the surface. Since a pn junction occurs at the bottom of the impurity region, a depletion layer spreads in the pn junction, and thereby reduces a parasitic capacity between the dummy region and a conductive interconnection located in a crossing direction at a higher position.

Abstract: A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

Abstract: A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. As a result, the lateral width of the isolation structure may be decreased without significantly increasing the capacitance between those active areas. In an embodiment, a fabrication process for the trench isolation structure may include a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner is thermally grown upon the sidewalls and base of the trench. A layer of low K dielectric material is deposited across the oxide liner. A fill oxide is then formed upon the layer of dielectric material. The resulting trench isolation structure includes a low K dielectric material interposed between an oxide liner and a fill oxide.

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate, (b) a gate insulating film formed on the semiconductor substrate, (c) a gate electrode formed on the gate insulating film, (d) L-shaped insulating films each comprising a first portion vertically extending on a sidewall of the gate electrode, and a second portion horizontally extending on the semiconductor substrate, and (e) raised source and drain layers formed on the semiconductor substrate in selected areas so that the raised source and drain layers make contact only with an end surface of the second portion. In the semiconductor device, since the insulating films are formed L-shaped, it is possible to reduce an area at which the insulating films make contact with the raised source and drain layers when the raised source and drain layers are formed by selective epitaxial growth. This prevents formation of facets, resulting in improving fabrication yield of a semiconductor device.

Abstract: Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used to make electrical contact to ground. Electrical circuit elements in the top surface of the integrated circuit are selectively grounded or isolated by the choice of connection to a via or pedestal, respectively.

Abstract: An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).

Abstract: An integrated circuit device includes a substrate having a planar surface and isolating trenches etched from the substrate. The isolating trenches form edges and corners with the surface of the substrate. An oxide covers the surface and fills the isolating trenches. The oxide has a thickness at the edges and corners which is greater than its thickness in other areas of the surface of the substrate. Field effect transistors having gate electrodes disposed on the oxide over the edges and corners and over a portion of the other areas of the surface are formed. Formation of parasitic edge transistors is suppressed and thinning of the oxide at the trench edges and corners is prevented because the oxide at the edges and corners is raised with respect to the other areas of the surface, thereby elevating the gate electrode at the edge and corner.

Abstract: A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.

Abstract: A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

Abstract: A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material.

Abstract: In a nonvolatile semiconductor memory device, those sides of the gate insulating film and the floating gate electrode which oppose an inner side of a trench are oxidized to form an oxide film. The gate insulating film, the floating gate electrode, and that portion of semiconductor substrate which is near the gate insulating film oppose an insulator made of a first material buried in the trench via another insulator made of a second material difference from the first material buried in the trench. The first material has a low diffusability of impurities, and is, for example, silicon nitride, which effectively suppresses diffusion of impurities from the second material into the gate insulating film.

Abstract: A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.

Abstract: A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the proximal portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate.

Abstract: An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

Abstract: A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.

Abstract: A lateral MOS transistor is described, in particular, though not exclusively, a transistor of the lateral DMOS type, in which the drain is provided with a weakly doped drain extension (8) to increase the breakdown voltage. This drain extension is also present at the ends of the drain digits, so that the "hard" drain (5) does not continue up to the edge (7) of the active region (6), but is separated therefrom by an interposed region. These regions do not contribute to the transistor effect. To reduce parasitic input capacitances, which correspond to these non-active regions, the gate poly (9) is provided in the active portion of the transistor only and is replaced in the non-active portions by poly (22) which is connected through to the source (4, 16). This poly acts as a gate which is permanently at 0 V, so that leakage currents in the non-active regions are prevented.

Abstract: The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.

Abstract: A three-dimensional, deep-trench, high-density ROM and its manufacturing method are provided. The ROM device comprises a silicon substrate having a plurality of parallel trenches above it surface, wherein, between every two adjacent trenches, there is a higher region. During programming of the ROM device, deeper trenches are formed to define the OFF-state non-conducting memory cells, so that misalignment problems that lead to transistor cell leakage are prevented. The ROM device provides reduced breakdown of the source/drain regions as well.

Abstract: An integrated circuit arrangement having at least two components has in a substrate, an insulation structure (4', 5) between the components which covers at least one side of a trench (3) and is thicker at the bottom of the trench than at the neck of the trench. The components are in this case arranged in different planes on the substrate surface and on the trench bottom. The insulation structure effects vertical insulation between the components.

Abstract: A semiconductor device and a fabrication method thereof which are capable of achieving a lightly doped drain (LDD) construction and reducing a parasitic capacitance generated between an impurity area and a word line by forming a trench in a portion of a semiconductor substrate and forming impurity areas around the trenches, include a semiconductor substrate, a plurality of trenches formed in the semiconductor substrate, first impurity areas formed along the outer surfaces of the plurality of trenches, second impurity areas formed on the bottom surfaces of the first impurity areas along the outer surfaces of the trenches, an insulating film filled in the trenches, a gate insulating film formed at a regular interval on the substrate having the insulating film filled in the trenches, and a gate electrode formed on the gate insulating film.