Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure.

Abstract: A non-volatile memory device structure includes a first conductor extending in a first direction, a second conductor extending in a second direction approximately orthogonal to the first direction, an amorphous silicon material disposed in an intersection between the first and second conductors characterized by a first resistance upon application of a first voltage, wherein the first resistance is dependent on a conductor structure comprising material from the second conductor formed in a portion of the resistive switching material, and a layer of material configured in between the second conductor and the amorphous silicon material, wherein the layer maintains at least a portion the conductor structure in the amorphous silicon material, and wherein the layer inhibits conductor species from the portion of the conductor structure from migrating away from the second conductor when a second voltage having an amplitude less than the first voltage is applied.

Abstract: A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first wiring structure overlies the first dielectric material. The method forms a first electrode material overlying the first wiring structure and a resistive switching material comprising overlying the first electrode material. An active metal material is formed overlying the resistive switching material. The active metal material is configured to form an active metal region in the resistive switching material upon application of a thermal energy characterized by a temperature no less than about 100 Degree Celsius. In a specific embodiment, the method forms a blocking material interposing the active metal material and the resistive switching material to inhibit formation of the active metal region in the resistive switching material during the subsequent processing steps.

Abstract: In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.

Abstract: Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.

Abstract: Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell.

Abstract: A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer.

Abstract: A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.

Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.

Abstract: A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell.

Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

Abstract: A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers.

Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer formed on a semiconductor substrate on which a lower electrode is formed, and including a plurality of holes of which diameters are increased at a first height or higher, a variable resistance material layer formed on the lower electrode to a second height of each of the holes, and an upper electrode formed on the variable resistance material layer to be buried in each of the holes.

Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole, A variable resistance material layer may be formed in the second hole to contact the lower electrode and an upper electrode may be formed in the first hole to contact the variable resistance material layer.

Abstract: A variable resistance memory device includes a plurality of first conductive lines extended in a first direction, a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction, an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first side wall and a second sidewall facing each other and a bottom surface connecting the first sidewall and the second sidewall, and a variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench, wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively.

Abstract: In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.

Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.

Abstract: Provided are a variable resistive memory device and a method of fabricating the same. The variable resistive memory device includes an interlayer insulating film having an opening therein, the opening exposing a surface of a first electrode which is disposed at a bottom of the opening. A variable resistive layer is formed in the opening and a second electrode is formed on the variable resistive layer. The variable resistive layer has a sidewall that is separated from an inner side surface of the opening to define a gap between the sidewall of the variable resistive layer and the inner side surface of the opening.

Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material.

Abstract: A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2? ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x<3).

Abstract: Provided is a non-volatile programmable device including a first terminal, a first threshold switching layer connected to part of the first terminal, a phase change layer connected to the first threshold switching layer, a second threshold switching layer connected to the phase change layer, a second terminal connected to the second threshold switching layer, and third and fourth terminals respectively connected to a side portion of the phase change layer and the other side portion opposite to the side portion of the phase change layer.

Abstract: A magnetic memory with a memory layer having magnetization, the direction of magnetization of which changes according to information recorded therein; a reference layer having a fixed magnetization against which magnetization of the memory layer can be compared; a nonmagnetization layer between the memory layer and the reference layer; and an electrode on one side of the memory layer facing away from the reference layer, wherein, the memory device memorizes the information by reversal of the magnetization of the memory layer by a spin torque generated when a current flows between the memory layer, the nonmagnetization layer and the reference layer, and a heat conductivity of a center portion of the electrode is lower than a heat conductivity of surroundings thereof. The memory and reference preferably have vertical magnetizations.

Abstract: A PCRAM device and a method of manufacturing the same are provided. The PCRAM device includes a semiconductor substrate, and a PN diode formed on the semiconductor substrate and including a layer interposed therein to suppress thermal diffusion of ions.

Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.

Abstract: A memristor with a channel region in thermal equilibrium with a containing region. The channel region has a variable concentration of mobile ions. The containing region, formed of stoichiometric crystalline material, contains and is in thermal equilibrium with the channel region.

Abstract: A method of forming a non-volatile memory device includes providing a semiconductor substrate having a surface region, thereafter forming a first dielectric layer overlying, thereafter forming a first wiring material, thereafter forming amorphous silicon layer, and patterning and etching these layers to form first structures extending in a first direction and having a switching element. Thereafter, a method may include depositing a second dielectric layer overlying the first structures and having a dielectric surface region, forming an opening region in the second dielectric material to exposing part of the switching element, and depositing a silver material in the opening region, but not on the dielectric surface region.

Abstract: Methods for passivating a carbonic nanolayer (that is, material layers comprised of low dimensional carbon structures with delocalized electrons such as carbon nanotubes and nanoscopic graphene flecks) to prevent or otherwise limit the encroachment of another material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous carbonic nanolayer to fill in the voids within the porous carbonic nanolayer while one or more other material layers are applied over or alongside the carbonic nanolayer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the carbonic nanolayer) is used to form a barrier layer within a carbonic nanolayer. In other embodiments, carbon structures are combined with and nanoscopic particles to limit the porosity of a carbonic nanolayer.

Abstract: Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a resistance change film. The resistance change film is connected between the first electrode and the second electrode. An ion metal is introduced in a matrix material in the resistance change film. A concentration of the ion metal in a first region on the first electrode side of the resistance change film is higher than a concentration of the ion metal in a second region on the second electrode side of the resistance change film A layer made of only the ion metal is not provided in the memory device.

Abstract: Apparatus, devices, systems, and methods are described that include filamentary memory cells. Mechanisms to substantially remove the filaments in the devices are described, so that the logical state of a memory cell that includes the that includes the removable filament can be detected. Additional apparatus, systems, and methods are described.

Abstract: The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A memory device comprises a semiconductor substrate having a first type conductivity and a plurality of parallel trenches therein; a plurality of parallel common source lines having a second type conductivity opposite to the first type conductivity formed in the trench bottoms; a plurality of parallel gate electrodes formed on the trench sidewalls with a gate dielectric layer interposed therebetween, the gate electrodes being lower in height than the trench sidewalls; and a plurality of drain regions having the second type conductivity formed in top regions of the trench sidewalls, at least two of the drain regions being formed in each of the trench sidewalls and sharing a respective common channel formed in the each of the trench sidewalls and a respective one of the source lines.

Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

Abstract: Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.

Abstract: A hybrid circuit comprises a nitride-based transistor portion and a memristor portion. The transistor includes a source and a drain and a gate for controlling conductance of a channel region between the source and the drain. The memristor includes a first electrode and a second electrode separated by an active switching region. The source or drain of the transistor forms one of the electrodes of the memristor.

Abstract: A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.

Abstract: A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed.

Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

Abstract: A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

Abstract: A structure for a variable-resistance element using an electrochemical reaction. The structure limits a position at which metal cross-linking breaks to a position most preferred for cross-linking break: namely, a part of an ion conduction layer closest to a first electrode. Also provided is a method for manufacturing the variable-resistance element, which has a first electrode serving as a source for a metal ion(s), a second electrode which is less ionizable (i.e. has a higher redox potential) than the first electrode, and an ion conduction layer which is interposed between the first and second electrodes and can conduct the metal ion(s). There is a first region in the ion conduction layer, adjacent to the first electrode, having a diffusion coefficient that increases continuously towards the first electrode right upto contacting the first electrode.

Abstract: Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.

Abstract: A nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, and methods of forming the same. A nonvolatile memory element includes a first electrode layer formed on a substrate, a resistive switching layer formed on the first electrode layer, and a second electrode layer. The resistive switching layer comprises a metal oxide and is disposed between the first electrode layer and the second electrode layer. The elemental metal selected for each of the first and second electrode layers is the same metal as selected to form the metal oxide resistive switching layer. The use of common metal materials within the memory element eliminates the growth of unwanted and incompatible native oxide interfacial layers that create undesirable circuit impedance.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore and filling the pore. Due to the use of SbxSe100-x in the phase-change material layer, a higher-speed, lower-power consumption phase-change memory device than a GST memory device can be manufactured.