Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.

Abstract: There is disclosed a MIS field effect transistor, comprising a silicon substrate, an insulating film formed over the silicon substrate and containing silicon and at least one of nitrogen and oxygen, a metal oxynitride film formed on the insulating film and containing at least one kind of metal atom selected from the group consisting of zirconium, hafnium and a lanthanoide series metal, the metal oxynitride film containing nitrogen atom not bonding with the metal atom without metal-nitrogen bond at the density of higher than 1019/cm3, and a gate electrode formed on the metal oxynitride film.

Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a metal compound film directly or indirectly on a semiconductor substrate, forming a metal-containing insulating film consisting of a metal oxide film or a metal silicate film by oxidizing the metal compound film, and forming an electrode on the metal-containing insulating film.

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

Abstract: A semiconductor device includes a continuous doped substrate with a surface, a sulfur-based dielectric material layer positioned on the surface of the continuous doped substrate, a dielectric material layer positioned on the sulfur-based dielectric material layer, and a gate contact region positioned on the sulfur-based dielectric material layer. The continuous doped substrate includes silicon (Si) and the sulfur-based dielectric material includes a transition metal sulfide such as strontium zirconium sulfur (SrZrS), barium zirconium sulfur (BaZrS), strontium hafnium sulfur (SrHfS), barium hafnium sulfur (BaHfS), or the like. Further, the gate contact region includes a layer of one of strontium titanium sulfur (SrTiS), barium titanium sulfur (BaTiS), or the like positioned adjacent to the dielectric material layer.

Abstract: A non-volatile memory device includes a semiconductor substrate, a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a gate electrode. The tunneling insulating layer is on the substrate and has a first dielectric constant. The charge storage layer is on the tunneling insulating layer. The blocking insulating layer is on the charge storage layer and has a second dielectric constant which is greater than the first dielectric constant of the tunneling insulting layer. The gate electrode is on the blocking insulating layer, and at least a portion of the gate electrode adjacent to the blocking layer has a higher work-function than polysilicon.

Abstract: A method of fabricating a semiconductor device is disclosed. A wafer substrate is provided. A first silicon oxide layer is formed over the wafer substrate. A nitride layer is formed over the first silicon oxide layer using a low temperature deposition process. A second silicon oxide layer is formed over the nitride layer. The low temperature process can form a nitride layer for an oxide-nitride-oxide (ONO) dielectric structure at about a temperature of 700° C. By such a process, an ONO dielectric structure can be formed using a low temperature deposition process, which can reduce the thickness of the ONO dielectric structure.

Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

Abstract: Dual-bit nitride read only memory (NROM) cell with parasitic amplifier and method of fabricating and reading the same. A NROM cell comprises a semiconductor substrate with a first well region having a conductive type opposite that of the substrate disposed therein. A second well region having a conductive type opposite to the first well region is disposed in the first well region. A gate dielectric layer is disposed over portions of the second well region, wherein the gate dielectric layer comprises a nitride layer. A conductive layer is disposed on the gate dielectric layer to form a gate. And, a pair of first doped regions having a conductive type opposite to the second well region are symmetrically disposed in the second well region of both sides of the gate, wherein one of the first doped regions, the second well region and the first well region constitute a parasitic current amplifier.

Abstract: A metal target, at least the surface region of which has been oxidized, is prepared in a chamber. Then, a sputtering process is performed on the metal target with an inert gas ambient created in the chamber, thereby depositing a first metal oxide film as a lower part of a gate insulating film over a semiconductor substrate. Next, a reactive sputtering process is performed on the metal target with a mixed gas ambient, containing the inert gas and an oxygen gas, created in the chamber, thereby depositing a second metal oxide film as a middle or upper part of the gate insulating film over the first metal oxide film.

Abstract: A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.

Abstract: The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the material. The nitrogen is thermally annealed within the material to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the material. The invention also encompasses a method of forming a transistor device. A silicon-oxide-comprising layer is formed over a substrate. The silicon-oxide-comprising layer is exposed to nitrogen from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the layer. The nitrogen is thermally annealed within the layer to bond at least some of the nitrogen silicon proximate the nitrogen.

Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a metal compound film directly or indirectly on a semiconductor substrate, forming a metal-containing insulating film consisting of a metal oxide film or a metal silicate film by oxidizing the metal compound film, and forming an electrode on the metal-containing insulating film.

Abstract: A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifically, the inventive semiconductor structure includes a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, the patterned gate region includes at least a metallic gate electrode formed atop a polysilicon gate electrode; hanging sidewall spacers formed on an upper portion of the patterned gate region including the metallic gate electrode; and a thermal oxide layer formed on lower portions of patterned gate region including a portion of the polysilicon gate electrode, but not the metallic gate electrode.

Abstract: A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin

Abstract: A new multilayer dielectric film for improving dielectric constant and thermal stability of gate dielectrics is provided. The multilayer dielectric film comprises a first layer formed of a metal oxide material having a high dielectric constant, and a second layer formed on the first layer. The second layer is formed of a metal silicate material having a dielectric constant lower than the dielectric constant of the first layer. A semiconductor transistor incorporating the multilayer dielectric film is also provided.

Abstract: The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: In a ferroelectric transistor containing two source/drain zones with a channel region disposed there-between, a first dielectric intermediate layer containing Al2O3 is disposed on a surface of the channel region. A ferroelectric layer and a gate electrode are disposed above the first dielectric intermediate layer. The utilization of Al2O3 in the first dielectric intermediate layer results in the suppression of tunneling of compensation charges from the channel region into the first dielectric layer and thereby improves the time for data storage.

Abstract: It is an object of the present invention is to provide a technique for forming a dense insulating film of good quality that is applicable to a transistor made on a substrate weak against heat such as a glass and a semiconductor device that can realize high performance and high reliability using the technique. In the present invention a silicon oxide film is formed on a crystalline semiconductor film, which is formed on an insulating surface, by the sputtering method using silicon as a target by applying high-frequency power in an atmosphere containing oxygen or oxygen and a rare gas, a silicon nitride film is formed thereon by applying high-frequency power in an atmosphere containing nitrogen or nitrogen and a rare gas, and then, heat treatment of a stacked body of the crystalline semiconductor film, the silicon oxide film, and the silicon nitride film at a temperature higher than a temperature for forming the films is performed.

Abstract: A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).

Abstract: A self-aligned enhancement mode metal-sulfide-oxide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide-oxide gate insulating structure. The gallium sulfide-oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer.

Abstract: The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: The flash memory structure includes a substrate having trenches formed therein, a first dielectric layer and a first conductive layer are stacked on the substrate. Isolations are formed in the trenches and protruding over the surface of the substrate, wherein the first conductive layer is also protruded over the isolations. A second conductive layer is lying the surface of the first conductive layer and a second dielectric layer formed thereon. A third conductive layer is formed on the second dielectric layer. The floating gate is consisted of first conductive layer and the second conductive layer.

Abstract: A semiconductor memory and its manufacturing method enable high-integrated memory cell to be realized easily. The semiconductor memory according to the present invention has an impurity diffusion region with a second conductive type that is opposite to a first conductive type on a surface of a semiconductor substrate with the first conductive type. Further, the semiconductor memory has structure in which there are provided a floating gate electrode formed on the semiconductor substrate via a gate insulator, and a control gate electrode formed on the floating gate electrode via an interelectrode insulating film. Furthermore, there are provided the gate insulator on the surface of the semiconductor substrate with the exception of an impurity diffusion region, and a third insulating film with film thickness thicker than that of the gate insulator on the surface of the impurity diffusion region.

Abstract: ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: A method of forming a diffusion barrier layer in a semiconductor device is disclosed. A high-k gate dielectric layer is formed over a substrate. A silicon nitride barrier layer is subsequently formed over the high-k gate dielectric layer by reacting tetrachlorosilane with ammonia through a chemical vapor deposition process. The silicon nitride barrier layer substantially blocks diffusion of impurities from an ensuing overlying gate layer. A semiconductor device comprising the silicon nitride barrier layer, and a method of fabricating such a semiconductor device are also disclosed.

Abstract: A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

Abstract: A two-type gate process is suitable for forming a gate insulation film partially formed of a high dielectric film, for example, a titanium oxide film (gate insulation film of the internal circuit) having a relative dielectric constant larger than that of silicon nitride on a substrate, and a silicon nitride film is deposited on the titanium oxide film. The silicon nitride film will prevent oxidation of the titanium oxide film when the surface of the substrate is subjected to thermal oxidation in the next process step. Next, the silicon nitride film and the titanium oxide film on the I/O circuit region are removed, while the silicon nitride film and the titanium oxide film on the internal circuit region remain, and the substrate is subjected to thermal oxidation to form a silicon oxide film as a gate insulation film on the surface of the I/O circuit region.

Abstract: An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface. In one embodiment the gate dielectric is an oxynitride formed by an N2 plasma; and the oxynitride has top surface nitrogen concentration that is higher than a bottom surface nitrogen concentration. In a further aspect of the present invention, an integrated circuit includes a plurality of IGFETs, wherein various ones of the plurality of IGFETs have different gate dielectric thicknesses and compositions.

Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.

Abstract: A new method of forming shallow trench isolations without using CMP is described. A plurality of isolation trenches are etched through an etch stop layer into the semiconductor substrate leaving narrow and wide active areas between the trenches. An oxide layer is deposited over the etch stop layer and within the trenches using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein after the oxide layer fills the trenches, the deposition component is discontinued while continuing the sputtering component until the oxide layer is at a desired depth. In one method, the oxide layer overlying the etch stop layer in the wide active areas is etched away. The etch stop layer and oxide layer residues are removed to complete planarized STI regions.

Abstract: The present invention provides a method of fabricating a thermally stable polysilicon/high-k dielectric film stack utilizing a deposition method wherein Si-containing precursor gas which includes silicon and hydrogen is diluted with an inert gas such as He so as to significantly reduce the hydrogen content in the resultant polysilicon film. Semiconductor structures such as field effect transistors (FETs) and capacitors which include at least the thermally stable polysilicon/high-k dielectric film stack are also provided herein.

Abstract: A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.

Abstract: Disclosed is a semiconductor device having a double dielectric layer, wherein the double dielectric layer comprises a first dielectric layer having aluminum and a second dielectric layer, of which a dielectric constant is higher than that of the first dielectric layer, stacked on the first dielectric layer. Also disclosed are methods for fabricating the semiconductor device.

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: A memory cell which allows information to be written or erased electrically. The memory cell includes a gate insulation film including three layers, i.e., a first insulation layer, an electric charge accumulating layer and a second insulation layer and a gate electrode formed on the gate insulation film. The electric charge accumulating layer is composed of a silicon nitride film or silicon oxynitride film. The first and second insulation layers are composed of a silicon oxide film or silicon oxynitride film containing more oxygen composition than the electric charge accumulating layer. The thickness of the second insulation layer is more than 5 nm. The gate electrode is formed of a p-type semiconductor containing p-type impurity.

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

Abstract: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than {fraction (1/100)} of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved.

Abstract: A method of forming a capacitor and transistor are disclosed. Initially, a substrate having a semiconductor material on a first surface is provided. A layer of strontium nitride is then deposited over the first surface and a gate electrode formed over the strontium nitride. Source and drains are then formed in the first surface disposed laterally adjacent to the gate electrode to leave a channel under the gate electrode. A dielectric layer may be formed over the layer of strontium nitride prior to forming the gate electrode. The dielectric layer may include strontium, titanium, and oxygen. In one embodiment, the dielectric layer and the layer of strontium nitride are epitaxial layers. In another embodiment the layer of strontium nitride is formed by sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD). The dielectric layer may include strontium, oxygen, and nitrogen, such as strontium oxynitride formed by sputtering, CVD, or ALD.

Abstract: A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifically, the inventive semiconductor structure includes a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, the patterned gate region includes at least a metallic gate electrode formed atop a polysilicon gate electrode; hanging sidewall spacers formed on an upper portion of the patterned gate region including the metallic gate electrode; and a thermal oxide layer formed on lower portions of patterned gate region including a portion of the polysilicon gate electrode, but not the metallic gate electrode.

Abstract: The present invention provides a semiconductor device with a channel length of approximately 0.05 microns. A semiconductor device according to the present invention, and a method for producing such a semiconductor device, comprises a control gate, a first floating gate located in proximity to the control gate, and a second floating gate located in proximity to the control gate. The present invention allows the threshold voltage of the device to be adjusted to various levels. Additionally, the device according to the present invention can be used as a very effective nonvolatile memory device.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: To ensure sufficient electrical insulation between bit and word lines and realize excellent charge holding characteristic by suppressing undesirable bird's beak formation, a buried bit line type flash memory includes bit lines formed by ion-implanting impurities into a semiconductor substrate, said bit lines serving also as sources and drains, and word lines crossing said bit lines and serving also as gate electrodes. After the impurity ion implantation for forming the bit lines and annealing for activating the impurities, an ONO film having a three-layer structure of silicon oxide film/silicon nitride film/silicon oxide film is formed.