Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics.

Abstract: A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.

Abstract: The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect.

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate on a substrate, a source region at a first side of the gate, a first conductive type body region under the source region, a second conductive type drain region at a second side of the gate, a device isolation region in the substrate between the source region and the drain region and overlapping part of the gate, and a first buried layer extending in a direction from the source region to the drain region, the first buried layer under the body region, overlapping part of the device isolation region, and not overlapping the drain region.

Abstract: A first contact, a second impurity region, and a second low-concentration impurity region form a Schottky barrier diode. The second impurity region has the same impurity concentration as those of first impurity regions, and thus can be formed in the same process as forming the first impurity regions. In addition, the second low-concentration impurity region has the same impurity concentration as those of first low-concentration impurity regions, and thus can be formed in the same process as forming the first low-concentration impurity regions.

Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

Abstract: Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.

Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A silicon epitaxial layer is grown by a CVD method on the surface of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration. After that, a PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.

Abstract: A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.

Abstract: A FET includes a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective oxide thickness, the FET further having a channel region with at least two portions each having a different doping profile. A semiconductor manufacturing process produces a FET including a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective oxide thickness, the FET further having a channel region with at least two portions each having a different doping profile.

Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

Abstract: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component. For this purpose the trench structure has a base (7) and a wall area (8) and is filled with a material (9) with a relatively high dielectric constant (?r). The base area (7) of the trench structure (5) is provided with a heavily doped semiconductor material (11) of the same conductivity type as the lightly doped semiconductor body areas (17), and/or having a metallically conductive material (12).

Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.

Abstract: A semiconductor device includes a channel layer formed over a substrate, a gate formed over the channel layer, junction regions formed on both sides of the channel layer to protrude from the substrate, and a buried barrier layer formed between the channel layer and the junction regions.

Abstract: A transistor having a metal nitride layer pattern, etchant and methods of forming the same is provided. A gate insulating layer and/or a metal nitride layer may be formed on a semiconductor substrate. A mask layer may be formed on the metal nitride layer. Using the mask layer as an etching mask, an etching process may be performed on the metal nitride layer, forming the metal nitride layer pattern. An etchant, which may have an oxidizing agent, a chelate agent and/or a pH adjusting mixture, may perform the etching. The methods may reduce etching damage to a gate insulating layer under the metal nitride layer pattern during the formation of a transistor.

Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor substrate. A first source region and a first drain region are present in the semiconductor substrate on opposing sides of the gate structure. At least one spacer is present on the sidewalls of the gate structure. The at least one spacer includes a first spacer and a second spacer. The first spacer of the at least one spacer is in direct contact with the sidewall of the gate structure and is present over an entire width of the first source region and the first drain region. The second spacer of the at least one spacer extends from the first spacer of the at least one spacer and has a length that covers an entire length of a first source region and a first drain region.

Abstract: A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

Abstract: A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric.

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Abstract: A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening.

Abstract: In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.

Abstract: A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.

Abstract: The present invention discloses a semiconductor device, comprising a substrate, a gate stack structure on the substrate, a gate spacer structure at both sides of the gate stack structure, source/drain regions in the substrate and at opposite sides of the gate stack structure and the gate spacer structure, characterized in that the gate spacer structure comprises at least one gate spacer void filled with air. In accordance with the semiconductor device and the method for manufacturing the same of the present invention, carbon-based materials are used to form a sacrificial spacer, and at least one air void is formed after removing the sacrificial spacer, the overall dielectric constant of the spacer is effectively reduced. Thus, the gate parasitic capacitance is reduced and the device performance is enhanced.

Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

Abstract: A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A buck pick-up region adjoins the source feature in the at least one lightly doped region. The buck pick-up region has a second conductivity type.

Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.

Abstract: A nonvolatile semiconductor memory device in one embodiment includes a select gate switch transistor having a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second source/drain regions provided in the semiconductor substrate so as to face each other across the gate electrode. The first source/drain region includes a first n-type impurity layer and a second n-type impurity layer which has a higher impurity concentration and has a shallower depth than the first n-type impurity layer. The second source/drain region has a third n-type impurity layer which has a lower impurity concentration and has a shallower depth than the first n-type impurity layer and a fourth n-type impurity layer which has a higher impurity concentration and has a deeper depth than the third n-type impurity layer.

Abstract: A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Abstract: The present invention provides a transistor and a method for forming the same. The method includes: providing a semiconductor substrate having a semiconductor layer formed thereon, the semiconductor layer and the semiconductor substrate having different crystal orientations; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the semiconductor substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer, which is substantially flush with the dummy gate structure; removing the dummy gate structure and the semiconductor layer beneath the dummy gate structure, forming an opening in the interlayer dielectric layer and the semiconductor layer, the semiconductor substrate being exposed at a bottom of the opening; forming a metal gate structure in the opening. Saturation current of the transistor is raised, and performance of a semiconductor device is promoted.

Abstract: A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.

Abstract: The present invention provides a transistor and a method for forming the same. The method includes: providing a semiconductor substrate having a semiconductor layer formed thereon, the semiconductor layer and the semiconductor substrate having different crystal orientations; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the semiconductor substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer, which is substantially flush with the dummy gate structure; removing the dummy gate structure and the semiconductor layer beneath the dummy gate structure, forming an opening in the interlayer dielectric layer and the semiconductor layer, the semiconductor substrate being exposed at a bottom of the opening; forming a metal gate structure in the opening. Saturation current of the transistor is raised, and performance of a semiconductor device is promoted.

Abstract: A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration.

Abstract: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

Abstract: Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer.

Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

Abstract: It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and a DMOS transistor is formed in the P+W layer. The epitaxial layer and a drain region are insulated by the P+W layer. Therefore, it is possible to form both the DMOS transistor and other device element in a single confined region surrounded by an isolation layer. An N type FN layer is disposed on the surface region of the P+W layer beneath the gate electrode. An N+D layer, which is adjacent to the edge of the gate electrode of the drain layer side, is also formed. P type impurity layers (a P+D layer and a FP layer), which are located below the drain layer, are disposed beneath the contact region of the drain layer.

Abstract: A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement.

Abstract: The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

Abstract: A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

Abstract: The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.