Abstract: A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.

Abstract: A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.

Abstract: A phase change memory is manufactured by providing a substrate including a layer of phase-change material, forming a damascene pattern on the layer of phase-change material, and forming both a top electrode and a bit line in the damascene pattern.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.

Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.

Abstract: A method for preparing a Group 1a-1b-3a-6a material using a selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.

Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.

Abstract: A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed.

Abstract: A Bi—Se doped with Cu, p-type semiconductor, preferably used as an absorber material in a photovoltaic device. Preferably the semiconductor has at least 20 molar percent Cu. In a preferred embodiment, the semiconductor comprises at least 28 molar percent of Cu. In one embodiment, the semiconductor comprises a molar percentage of Cu and Bi whereby the molar percentage of Cu divided by the molar percentage of Bi is greater than 1.2. In a preferred embodiment, the semiconductor is manufactured as a thin film having a thickness less than 600 nm.

Abstract: The construction of this invention includes an active matrix substrate, an amorphous selenium layer, a high resistance layer, a gold electrode layer, an insulating layer and an auxiliary plate laminated in this order. In one aspect of the present invention, the insulating layer has an inorganic anion exchanger added thereto in order to provide a radiation detector which prevents void formation and pinhole formation in the amorphous semiconductor layer and carrier selective high resistance film, without accumulating electric charges on the auxiliary plate. The inorganic anion exchanger adsorbs chloride ions in the insulating layer, thereby preventing destruction of X-ray detector due to the chloride ions drawn to the gold electrode layer.

Abstract: A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity.

Abstract: It is aimed to provide a photoelectric conversion device having high adhesion between a first semiconductor layer and an electrode layer as well as high photoelectric conversion efficiency. A photoelectric conversion device comprises an electrode layer, a first semiconductor layer located on the electrode layer and comprising a chalcopyrite-based compound semiconductor of group I-III-VI and oxygen, and a second semiconductor layer located on the first semiconductor layer and forming a pn junction with the first semiconductor layer. In the photoelectric conversion device, the first semiconductor layer has a higher molar concentration of oxygen in a part located on the electrode layer side with respect to a center portion in a lamination direction of the first semiconductor layer than a molar concentration of oxygen in the whole of the first semiconductor layer.

Abstract: A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.

Abstract: An X-ray detector 1 includes: an X-ray conversion layer 17 which is made of amorphous selenium and absorbs incident radiation and generates charges; a common electrode 23 provided on a surface on the side on which radiation is made incident of the X-ray conversion layer 17; and a signal readout substrate 2 on which a plurality of pixel electrodes 7 for collecting charges generated by the X-ray conversion layer 17 are arrayed, and further includes: an electric field relaxation layer 13 provided between the X-ray conversion layer 17 and the signal readout substrate 2 and containing arsenic and lithium fluoride; a crystallization suppressing layer 11 provided between the electric field relaxation layer 13 and the signal readout substrate 2 and containing arsenic; and a first thermal property enhancement layer 15 provided between the electric field relaxation layer 13 and the X-ray conversion layer 17 and containing arsenic.

Abstract: A method for forming multiple layers in a single process chamber includes placing a substrate in the process chamber having multiple processing sources and iteratively forming a copper indium gallium selenium (CIGS) including forming multiple relatively thin CIGS layers including forming a copper indium gallium (CIG) layer on the substrate, the CIG layer having a thickness of between less than about 50 angstroms and about 200 angstroms, forming a selenium layer on the CIG layer, the selenium layer having a thickness of between less than about 50 angstroms and about 200 angstroms and heating the substrate, the CIG layer and the selenium layer. A processing chamber system is also disclosed.

Abstract: A gallium ink is provided, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; wherein the gallium ink is a stable dispersion. Also provided are methods of preparing the gallium ink and for using the gallium ink in the preparation of semiconductor films (e.g., in the deposition of a CIGS layer for use in photovoltaic devices).

Abstract: A method of making an inorganic light emitting layer includes combining a solvent for semiconductor nanoparticle growth, a solution of core/shell quantum dots, and semiconductor nanoparticle precursor(s); growing semiconductor nanoparticles to form a crude solution of core/shell quantum dots, semiconductor nanoparticles, and semiconductor nanoparticles that are connected to the core/shell quantum dots; forming a single colloidal dispersion of core/shell quantum dots, semiconductor nanoparticles, and semiconductor nanoparticles that are connected to the core/shell quantum dots; depositing the colloidal dispersion to form a film; and annealing the film to form the inorganic light emitting layer.

Abstract: A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms.

Abstract: Provided is an electronic component that includes a first bi-layer stack including a first silicon oxide layer and a first silicon nitride layer, a second bi-layer stack including a second silicon oxide layer and a second silicon nitride layer, and a convertible structure which is convertible between at least two states having different electrical properties, where the convertible structure is arranged between the first bi-layer stack and the second bi-layer stack.

Abstract: A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided.

Abstract: A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

Abstract: thermal management for large scale processing of CIS and/or CIGS based thin film is described. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, to at least initiate formation of a copper indium diselenide film.

Abstract: A selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.

Abstract: A selenium/Group Ib/Group 3a ink is provided, comprising, as initial components: (a) a selenium/Group Ib/Group 3a system which comprises a combination of, as initial components: a selenium; an organic chalcogenide component; a Group Ib containing substance; optionally, a bidentate thiol component; a Group 3a containing substance; and, (b) a liquid carrier component; wherein the selenium/Group Ib/Group 3a system is stably dispersed in the liquid carrier component. Also provided are methods of preparing the selenium/Group Ib/Group 3a ink and for using the selenium/Group Ib/Group 3a ink to deposit a selenium/Group Ib/Group 3a material on a substrate for use in the manufacture of a variety of chalcogenide containing semiconductor materials, such as, thin film transistors (TFTs), light emitting diodes (LEDs); and photoresponsive devices (e.g., electrophotography (e.g.

Abstract: A selenium ink comprising selenium stably dispersed in a liquid medium is provided, wherein the selenium ink is hydrazine free and hydrazinium free. Also provided are methods of preparing the selenium ink and of using the selenium ink to deposit selenium on a substrate for use in the manufacture of a variety of chalcogenide containing semiconductor materials, such as, thin film transistors (TFTs), light emitting diodes (LEDs); and photo responsive devices (e.g., electrophotography (e.g., laser printers and copiers), rectifiers, photographic exposure meters and photo voltaic cells) and chalcogenide containing phase change memory materials.

Abstract: Interfused nanocrystals including two or more materials, further including an alloy layer formed of the two or more materials. In addition, a method of preparing the interfused nanocrystals. In the interfused nanocrystals, the alloy layer may be present at the interface between the two or more nanocrystals, thus increasing the material stability. A material having excellent quantum efficiency in the blue light range may be synthesized.

Abstract: Ternary and quaternary Chalcopyrite CuInxGa1-xSySe2-y (CIGS, where 0?x and y?1) nanoparticles were synthesized from molecular single source precursors (SSPs) by a one-pot reaction in a high boiling solvent using salt(s) (i.e. NaCl as by-product) as heat transfer agent via conventional convective heating method. The nanoparticles sizes were 1.8 nm to 5.2 nm as reaction temperatures were varied from 150° C. to 190° C. with very high-yield. Tunable nanoparticle size is achieved through manipulation of reaction temperature, reaction time, and precursor concentrations. In addition, the method developed in this study was scalable to achieve ultra-large quantities production of tetragonal and quaternary Chalcopyrite CIGS nanoparticles.

Abstract: A bulk barium copper sulfur fluoride (BCSF) material can be made by combining Cu2S, BaS and BaF2, heating the ampoule between 400 and 550° C. for at least two hours, and then heating the ampoule at a temperature between 550 and 950° C. for at least two hours. The BCSF material may be doped with potassium, rubidium, or sodium. Additionally, a p-type transparent conductive material can comprise a thin film of BCSF on a substrate where the film has a conductivity of at least 1 S/cm. The substrate may be a plastic substrate, such as a polyethersulfone, polyethylene terephthalate, polyimide, or some other suitable plastic or polymeric substrate.

Abstract: An organic thin film transistor substrate includes a gate line formed on a substrate, a data line intersecting the gate line and defining a subpixel area, an organic thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and an organic semiconductor layer forming a channel between the source and drain electrodes, a passivation layer parallel with the gate line, for covering the organic semiconductor layer and peripheral regions of the organic semiconductor layer, and a bank insulating layer for determining the position of the organic semiconductor layer and the passivation layer.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: A wafer-scale x-ray detector and a method of manufacturing the same are provided. The wafer-scale x-ray detector includes: a seamless silicon substrate electrically connected to a printed circuit substrate; a chip array having a plurality of pixel pads formed on a central region thereof and a plurality of pin pads formed at edges thereof on the seamless silicon substrate; a plurality of pixel electrodes formed to correspond to the pixel pads; vertical wirings and horizontal wirings formed to compensate a difference of regions expanded towards the pixel electrodes from the pixel pads between the chip array and the pixel electrodes; a redistribution layer having an insulating layer to separate the vertical wirings and the horizontal wirings; and a photoconductor layer and a common electrode which cover the pixel electrodes on the redistribution layer.

Abstract: Provided are resistive random access memories (RRAMs) and methods of manufacturing the same. A RRAM includes a storage node including a variable resistance layer, a switching device connected to the storage node, and a protective layer covering an exposed part of the variable resistance layer. The protective layer includes at least one of aluminum oxide and titanium oxide. The variable resistance layer is a metal oxide layer.

Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

Abstract: A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.

Abstract: A phase-change memory device including a first contact region and a second contact region formed on a semiconductor substrate. A first insulating layer with a first contact hole and a second contact hole is disposed on the semiconductor substrate, exposing the first and second contact regions. A first conductive layer is disposed on the first insulating interlayer to fill the first and the second contact holes. A first protection layer pattern and a lower wiring protection pattern are disposed on the first conductive layer. A first contact with a first electrode and a second contact with a lower wiring are disposed so as to connect the first and second contact regions. A second protection layer with a second electrode is disposed on the first protection layer pattern and the lower wiring protection pattern. A via filled with a phase-change material is disposed between the first electrode and the second electrode.

Abstract: This magnetic device integrates a magneto-resistive stack, the stack comprising at least two layers made out of a ferromagnetic material, separated from each other by a layer of non-magnetic material; and means for causing an electron current to flow perpendicular to the plane of the layers, with at least one integrated nano-contact intended to inject the current into the magneto-resistive stack. The nano-contact is made in a bilayer composed of a solid electrolyte on which has been deposited a soluble electrode composed of a metal that has been at least partially dissolved in the electrolyte.

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.

Abstract: A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.

Abstract: Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.

Abstract: Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.

Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.

Abstract: A multi-layer storage node, resistive random access memory device and methods of manufacturing the same are provided. The resistive random access memory device includes a switching structure and a storage node connected to the switching structure. The storage node includes a lower electrode, a first layer, a second layer, and an upper electrode that may be sequentially stacked. The first layer may be formed on the lower electrode and includes at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te) and combinations thereof. The second layer may be formed on the first layer and includes at least one of copper (Cu), silver (Ag) and combinations thereof. The second layer may be formed of a material having an oxidizing power less than that of the first layer. The upper electrode may be formed on the second layer.

Abstract: Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.

Abstract: A method of forming a semiconductor device may comprise forming a memory portion, forming a carbon film, depositing insulation to at least partially cover the carbon film, and terminating patterned removal of the insulation at the carbon film during a fabrication process.

Abstract: The construction of this invention includes an active matrix substrate, an amorphous selenium layer, a high resistance layer, a gold electrode layer, an insulating layer and an auxiliary plate laminated in this order. In one aspect of the present invention, the insulating layer has an inorganic anion exchanger added thereto in order to provide a radiation detector which prevents void formation and pinhole formation in the amorphous semiconductor layer and carrier selective high resistance film, without accumulating electric charges on the auxiliary plate. The inorganic anion exchanger adsorbs chloride ions in the insulating layer, thereby preventing destruction of X-ray detector due to the chloride ions drawn to the gold electrode layer.

Abstract: A multi-level memory cell having a bottom electrode, a first dielectric layer, a plurality of memory material layers, a plurality of second dielectric layers, and an upper electrode is provided. The bottom electrode is disposed in a substrate. The first dielectric layer is disposed on the substrate and has an opening exposing the bottom electrode. The memory material layers are stacked on a sidewall of the first dielectric layer exposed by the opening and are electrically connected to the bottom electrode. The second dielectric layers are respectively disposed between every adjacent two memory material layers and are located on the sidewall of the first dielectric layer. The upper electrode is disposed on the memory material layers. A manufacturing method of the multi-level memory cell is further provided. A multi-bit data can be stored in a single memory cell, and both the process complexity and the cost are reduced.

Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.

Abstract: A photodiode includes a p-type semiconductor material and an n-type chalcogenide compound. The p-type semiconductor material and the n-type chalcogenide compound form a pn-junction.

Abstract: A phase change random access memory for actively removing residual heat and a method of manufacturing the same are presented. The phase change random access memory includes a semiconductor substrate, a phase change pattern, a heating electrode and a cooling electrode. The phase change pattern is on the semiconductor substrate. The heating electrode is electrically coupled to the phase change pattern for heating the phase change pattern. The cooling electrode is electrically coupled to the phase change pattern for removing residual heat from the phase change pattern.