Abstract: A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

Abstract: A photodetector includes a detector material having an upper layer, a lower layer, and at least one sidewall. Also included as part of the photodetector are a first contact electrically coupled to the detector material through the upper layer and a second contact electrically coupled to the detector material through the lower layer. Diffused into the sidewall by a passivation process is a dopant material operable to electrically isolate the first contact from the second contact via the sidewall. The dopant material is provided by a passivation layer deposited on the sidewall.

Abstract: A method for manufacturing a light-emitting device includes: providing first and second substrates each including a plurality of packages, the packages each having a recess and a light-emitting element mounted in the recess; performing potting by supplying a resin member containing particles of a fluorescent material into the recess of each of the packages of the first substrate; spreading the resin member in the recess of each of the packages of the first substrate; measuring a height of an upper surface of the resin member spread in the recess of at least one of the packages of the first substrate; and adjusting a quantity of the resin member to be supplied into the recess of each of the packages of the second substrate depending on the measured height of the upper surface of the resin member.

Abstract: Implementations of image sensors may include: a first die including a plurality of detectors adapted to convert photons to electrons; a second die including a plurality of transistors, passive electrical components, or both transistors and passive electrical components; a third die including analog circuitry, logic circuitry, or analog and logic circuitry. The first die may be hybrid bonded to the second die, and the second die may be fusion bonded to the third die. The plurality of transistors, passive electrical components, or transistors and passive electrical components of the second die may be adapted to enable operation of the plurality of detectors of the first die. The analog circuitry, logic circuitry, and analog circuitry and logical circuitry may be adapted to perform signal routing.

Abstract: The present invention relates to an improved cordierite glass-ceramic. In order to improve the materials properties, it is proposed that the glass-ceramic comprising SiO2, Al2O3, MgO and Li2O contains cordierite as main crystal phase and that a secondary crystal phase of the glass-ceramic comprises high-quartz solid solution and/or keatite solid solution. The invention further relates to a process for producing such a glass-ceramic and the use of such a glass-ceramic.

Abstract: A cut data generating apparatus configured to generate cut data for a cutting apparatus including a cut mechanism to cut a pattern from a workpiece, the cut data generating apparatus comprising: a controller, the controller being configured to control the cut data generating apparatus to: identify a size of an original pattern to be cut; judge whether the size of the original pattern identified is larger than a size of the workpiece; divide the original pattern into plural divided patterns smaller than the size of the workpiece in case the size of the original pattern is larger than the size of the workpiece; and generate cut data for cutting each of the divided patterns, determine whether at least one of the plural divided patterns divided falls within one workpiece along with another divided pattern, and generate cut data for cutting the divided patterns from one workpiece in case at least one of the divided patterns falls within one workpiece along with another divided pattern.

Abstract: An image sensor such as a backside illumination image sensor may be provided with analog circuitry, digital circuitry, and an image pixel array on a semiconductor substrate. Trench isolation structures may separate the analog circuitry from the digital circuitry on the substrate. The trench isolation structures may be formed from dielectric-filled trenches in the substrate that isolate the portion of the substrate having the analog circuitry from the portion of the substrate having the digital circuitry. The trench isolation structures may prevent digital circuit operations such as switching operations from negatively affecting the performance of the analog circuitry. Additional trench isolation structures may be interposed between portions of the substrate on which bond pads are formed and other portions of the substrate to prevent capacitive coupling between the bond pad structures and the substrate, thereby enhancing the high frequency operations of the image sensor.

Abstract: Provided is a flexible device, which includes a flexible substrate, a plurality of electrode lines provided on the flexible substrate and configured to contact the following anisotropic conductive film and then extend to a side of the flexible substrate, an anisotropic conductive film configured to contact the electrode line and laminated on the flexible substrate, a plurality of bumps provided on the anisotropic conductive film, and a circuit board having an electronic device provided at one side thereof and configured to contact the plurality of bumps.

Abstract: An image sensor may include optically black pixels for obtaining dark current measurements. The image sensor may include dummy pixels between the active pixel array and the optically black pixels. Light incident upon the dummy pixels may be redirected to the optically black pixels, causing inaccurate dark current measurements. Light-blocking structures may be provided in the dummy pixels to prevent light from reaching the optically black pixels. A grid of openings may be formed in the active pixel array and the dummy pixel area. The grid may be filled with color filters in the active area and light-blocking elements in the dummy pixel area. The dummy pixel area may include a single opening in the grid in which a single light-blocking element that covers multiple dummy pixel photodiodes is formed. Light-blocking structures in the dummy pixel area may extend over the optically black pixels.

Abstract: An imaging device, comprising: at least one unit pixel cell; and a voltage application circuit that generates at least two different voltages, each of the at least one unit pixel cell comprising: a photoelectric conversion layer having a first surface and a second surface being on a side opposite to the first surface, a pixel electrode located on the first surface, an auxiliary electrode located on the first surface, the auxiliary electrode being separated from the pixel electrode and electrically connected to the voltage application circuit, an upper electrode located on the second surface, the upper electrode opposing to the pixel electrode and the auxiliary electrode, a charge storage node electrically connected to the pixel electrode, and a charge detection circuit electrically connected to the charge storage node.

Abstract: A pixel structure of an image sensor and fabrication methods thereof are provided. The pixel structure includes a semiconductor substrate and plural pixel units disposed on the semiconductor substrate. The pixel units are electrically connected to each other, and each of the pixel units includes a light-sensitive region, a transfer gate and a protection layer. A terminal portion of the protection layer is covered by the transfer gate, and a width of the terminal portion of the protection layer is progressively decreased along a depthwise direction of the terminal portion of the protection layer. In the fabrication methods of the pixel structure, the protection layers of the pixel units are formed by doping with a tilt angle, so as to form the terminal portion of the protection layer.

Abstract: In an embodiment, a slim imager is disclosed. The slim imager includes a substrate including an aperture, an image sensor, and an optics unit. The image sensor is on a bottom side of the substrate, spans the aperture, and has an aperture-facing top surface. The optics unit is on a top side of the substrate, spans the aperture, and includes a transmissive optical element having an aperture-facing bottom surface. A volume partially bound by the aperture-facing top surface and the aperture-facing bottom surface has a refractive index less than 1.01 at visible wavelengths.

Abstract: A pixel cell has a photodiode, a transfer transistor, a reset transistor, a dynamic range enhancement capacitor, a capacitor control transistor, an amplifier transistor in a source follower configuration and a rolling shutter row select transistor and a readout circuit block. The photodiode, a transfer transistor, a reset transistor, dynamic range enhancement capacitor, capacitor control transistor, amplifier transistor and rolling shutter row select transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings.

Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.

Abstract: The present invention provides a method for forming bumps of a semiconductor package to suppress a final height difference between main bumps and support bumps that is caused by a height difference between areas of an underlying layer when viewed on a cross-section. The method may include forming first seed layer patterns and second seed layer patterns which are disposed in the areas and are separated from each other, over the underlying layer having the height difference. The method may include forming the main bumps and the support bumps of which final heights are the same when viewed on the cross-section in the areas, by performing electroplating through using, as electrodes, the first seed layer patterns and the second seed layer patterns which are disposed in the areas and are separated from each other, under different conditions in the areas.

Abstract: An imaging system with a pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor in a source follower configuration, and a readout circuit block. The photodiode, transfer transistor, reset transistor and source follower amplifier are part of an array disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

Abstract: A semiconductor device having a stacked structure formed by stacking a thinned first silicon substrate and a second silicon substrate supporting the first silicon substrate, wherein the first silicon substrate includes a first surface with a crystal surface orientation of (100) or (110) and a second surface opposite to the first surface, the second silicon substrate includes a third surface and a fourth surface that is opposite to the third surface and from which a silicon surface with a crystal surface orientation (111) is exposed, and wherein the semiconductor device is formed by etching silicon with a predetermined thickness in a direction from the first surface toward the second surface to make the first silicon substrate to be thinned, after bonding the first silicon substrate and the second silicon substrate in a state where the second surface and the third surface facing the second surface are bonded with each other.

Abstract: Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterning the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces.

Abstract: An integrated electronic device for detecting the composition of ultraviolet radiation includes a cathode region formed by a semiconductor material with a first type of conductivity. A first anode region and a second anode region are laterally staggered with respect to one another and are set in contact with the cathode region. The cathode region and the first anode region form a first sensor. The cathode region and the second anode region form a second sensor. In a spectral range formed by the UVA band and by the UVB band, the first and second sensors have, respectively, a first spectral responsivity and a second spectral responsivity different from one another.

Abstract: Embodiments related to the manufacturing of an imager device and an imager device are disclosed. Embodiments associated with methods of an imager device are also disclosed.

Abstract: A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

Abstract: A solar cell structure includes P-type and N-type doped regions. A dielectric spacer is formed on a surface of the solar cell structure. A metal layer is formed on the dielectric spacer and on the surface of the solar cell structure that is exposed by the dielectric spacer. A metal foil is placed on the metal layer. A laser beam is used to weld the metal foil to the metal layer. A laser beam is also used to pattern the metal foil. The laser beam ablates portions of the metal foil and the metal layer that are over the dielectric spacer. The laser ablation of the metal foil cuts the metal foil into separate P-type and N-type metal fingers.

Abstract: A pixel cell, a method for manufacturing the same and an image sensor including the same are provided. The pixel cell includes: a substrate; a photodiode, a pass transistor and a floating diffusion structure respectively formed on the substrate, in which the pass transistor is formed between the photodiode and the floating diffusion structure; and a PINNED structure, formed on the substrate and connected with the floating diffusion structure, in which a reset voltage of the floating diffusion structure is higher than a depletion voltage of the PINNED structure.

Abstract: A method of manufacturing a memory device includes providing a semiconductor substrate including a first region and a second region. The method includes forming a lower structure including interconnect lines and an etch stop layer in the second region. The method includes forming a multilayer structure on the lower structure. The method also includes forming a slit trench in the multilayer structure of the first region, a first plug hole exposing the etch stop layer of the second region therethrough, and a second plug hole exposing a portion of the interconnect lines of the second region therethrough.

Abstract: An imaging pixel may be operated in either a linear mode or a logarithmic mode. In the logarithmic mode, the voltage at a floating diffusion region may be proportional to the logarithm of the intensity of incident light. In order to enable correlated double sampling (CDS) in the logarithmic mode, a transistor may be provided that couples the photodiode to a bias voltage. When the transistor is turned off, the photodiode may be able to operate in a logarithmic mode. When the transistor is turned on, the floating diffusion region may be reset to a baseline voltage level. Images from the linear mode and the logarithmic mode may be combined to form high dynamic range images with flicker mitigation.

Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.

Abstract: A Mach-Zehnder modulator comprises first to third semiconductor structures provided on first to third areas of a primary surface of a conductive semiconductor region, respectively. The second semiconductor structure includes a semiconductor laminate and a first contact portion thereon. The third semiconductor structure includes the semiconductor laminate and a second contact portion thereon. The first and second contact portions constitute a contact layer. The second semiconductor structure has first and second waveguide sides. The first contact portion has an edge which terminates the contact layer and extends in a direction of a first reference plane on the top of the semiconductor laminate to reach the first waveguide side. The first reference plane and a top of the second semiconductor structure intersect with each other to define a line of intersection obliquely-crossed with an upper edge of the first waveguide side at a first angle different from a right angle.

Abstract: A vertical nitride semiconductor device includes an n-type aluminum nitride single-crystal substrate having an Si content of 3×1017 to 1×1020 cm?3 and a dislocation density of 106 cm?2 or less. An ohmic electrode layer is formed on an N-polarity side of the n-type aluminum nitride single-crystal substrate.

Abstract: A semiconductor chip is provided with first and second electrode pads, a first current detector, and a third electrode pad. The first and second electrode pads are both to be wire-bonded to a first lead terminal. The first current detector is connected between the first and second electrode pads. The third electrode pad is wire-bonded to a second lead terminal. A first closed circuit is configured by the first lead terminal, the first electrode pad, the first current detector, and the second electrode pad. An induced current flows through the first closed circuit when a current generating an induced electromotive force is applied to the third electrode pad. The first current detector is configured to output different values depending on whether the induced current exceeds a threshold value or not.

Abstract: A package structure includes a substrate and a package plate. A frame is formed of a seal glue arranged between the substrate and the package plate. An underfill is positioned inboard of the frame. The package plate has a spreading surface, and at least one groove is formed in a spreading path of the frame on the spreading surface of the package plate.

Abstract: Glass-ceramics exhibiting a Vickers indentation crack initiation threshold of at least 15 kgf are disclosed. These glass-ceramics may be ion exchangeable or ion exchanged. The glass-ceramics include a crystalline and amorphous phases generated by subjecting a thin precursor glass article to ceramming cycle having an average cooling rate in the range from about 10° C./minute to about 25° C./minute. In one or more embodiments, the crystalline phase may comprise at least 20 wt % of the glass-ceramics. The glass-ceramics may include ?-spodumene ss as the predominant crystalline phase and may exhibit an opacity ?about 85% over the wavelength range of 400-700 nm for an about 0.8 mm thickness and colors an observer angle of 10° and a CIE illuminant F02 determined with specular reflectance included of a* between ?3 and +3, b* between ?6 and +6, and L* between 88 and 97.

Abstract: An electronic module subassembly including a substrate. The substrate includes a bottom laminate, a middle laminate coupled to the bottom laminate, and a top laminate coupled to the middle laminate. The middle laminate has a plurality of web areas, each web area defining at least one hole. The defines a planar top surface and a plurality of open areas corresponding to and aligned with the plurality of web areas. First components have a first thickness. At least one first component is in each of the open areas. Second components have a second thickness relatively larger than the first thickness. At least one second component is in each of the open areas. The second components extend into the respective at least one hole of the web areas. Encapsulant fills in the open areas and the web areas.

Abstract: Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.

Abstract: A composite substrate configured for epitaxial growth of a semiconductor layer thereon is provided. The composite substrate includes multiple substrate layers formed of different materials having different thermal expansion coefficients. The thermal expansion coefficient of the material of the semiconductor layer can be between the thermal coefficients of the substrate layer materials. The composite substrate can have a composite thermal expansion coefficient configured to reduce an amount of tensile stress within the semiconductor layer at room temperature and/or an operating temperature for a device fabricated using the heterostructure.

Abstract: Provided is a solid-state image pickup apparatus including a crosstalk suppression mechanism included in each pixel arranged in a pixel array, the crosstalk suppression mechanism of a part of the pixels differing from that of other pixels in an effective area of the pixel array.

Abstract: Embodiments provide a light emitting device package including a first lead frame including a first contact area and a first exposed area, a second lead frame spaced apart from the first lead frame, the second lead frame including a second contact area and a second exposed area, a bottom portion located between the first contact area and the first exposed area, between the second contact area and the second exposed area, and between the first contact area and the second contact area, a light emitting device electrically connected to the first and second contact areas, and a package body having a cavity configured to expose the first and second contact areas, the first and second exposed areas, and the bottom portion, wherein the bottom portion has a thermal expansion coefficient greater than a thermal expansion coefficient of the first and second lead frames.

Abstract: An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.

Abstract: An electronic component has a circuit board with a main surface, a chip having a sensor facing the main surface, bump electrodes disposed between the main surface and the chip so as to be placed inside of the edges of the chip in a plan view of the main surface, a dam provided between the main surface and the chip so as to extend at least from the edges of the chip to outer positions of the bump electrodes in a plan view of the main surface, and an under-fill material provided at least in a clearance between the dam and the chip. Between the main surface and the sensor, a space is formed in a region enclosed by the bump electrodes in a plan view of the main surface. The under-fill material is disposed outside of the space in a plan view of the main surface.

Abstract: A solid-state imaging device includes: multiple micro lenses, which are disposed in each of a first direction and a second direction orthogonal to the first direction, focus the incident light into the light-receiving surface; with the multiple micro lenses of which the planar shape is a shape including a portion divided by a side extending in the first direction and a side extending in the second direction being disposed arrayed mutually adjacent to each of the first direction and the second direction; and with the multiple micro lenses being formed so that the depth of a groove between micro lenses arrayed in a third direction is deeper than the depth of a groove between micro lenses arrayed in the first direction, and also the curvature of the lens surface in the third direction is higher than the curvature of the lens surface in the first direction.

Abstract: Disclosed is a light emitting device package and a lighting system. The light emitting device package includes a body, a first lead frame on the body, a plurality of light emitting diodes on the first lead frame, and a molding member on the light emitting diodes. The distance between the light emitting diodes includes a distance equal to or less than a length of a first side of a first light emitting diode of the light emitting diodes.

Abstract: A light emitting device (10) comprises a body (12) of a semiconductor material having a first face (14) and at least one other face (16). At least one pn-junction (18) in the body is located towards the first face and is configured to be driven via contacts on the body into a light emitting mode. The other face (16) of the body is configured to transmit from the body light emitted by the at least one pn-junction (18) in the near infrared part of the spectrum and having wavelengths longer than 1 ?m.

Abstract: A photoconductive antenna that generates a terahertz wave by irradiation with a light pulse, includes: a carrier generation layer that has carriers formed therein by irradiation with the light pulse, and is constituted by a semi-insulating substrate; an insulating layer, located on the carrier generation layer, which is capable of transmitting the light pulse; and a first electrode and a second electrode, located above the carrier generation layer, which apply a voltage to the carrier generation layer, wherein the insulating layer is provided on a region which is irradiated with the light pulse between the first electrode and the second electrode in a plan view.

Abstract: An imager includes an emitter, an array of pixel elements, and driver logic. The emitter releases bursts of light pulses with pauses between bursts. Each element of the array has a finger gate biasable to attract charge to the surface, a reading node to collect the charge, and a transfer gate to admit such charge to the reading node and to deter such charge from being absorbed into the finger gate. The driver logic biases the finger gates with the modulated light pulses such that the finger gates of adjacent first and second elements cycle with unequal phase into and out of a charge-attracting state. To reduce the effects of ambient light on the imager, the driver logic is configured to bias the transfer gates so that the charge is admitted to the reading node only during the bursts and is prevented from reaching the reading node during the pauses.

Abstract: An integrated circuit device includes an integrated circuit substrate having an at least two piece package thereon. The package has a sealed cavity therein and a patterned metal inductor in the cavity. The inductor has at least a first terminal electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package, which may include a material selected from a group consisting of glass and ceramics, includes a base and a cap sealed to the base. The metal inductor includes a metal layer patterned on at least one of the cap and base of the package. The base may also include first and second electrically conductive vias therein, which are electrically connected to first and second terminals of the inductor.

Abstract: A printing circuit board includes: an insulator having an upper surface, a lower surface and an opening formed in the lower surface, and a trace having an upper surface, a lower surface and a side edge and received in said insulator. The upper surface of said trace is exposed out of the insulator and a portion of the lower surface of said trace is exposed by said opening for external connection.

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract: A solid-state imaging device which includes, a photoelectric conversion film provided on a second surface side which is the opposite side to a first surface on which a wiring layer of a semiconductor substrate is formed, performs photoelectric conversion with respect to light in a predetermined wavelength region, and transmits light in other wavelength regions; and a photoelectric conversion layer which is provided in the semiconductor substrate, and performs the photoelectric conversion with respect to light in other wavelength regions which has transmitted the photoelectric conversion film, in which input light is incident from the second surface side with respect to the photoelectric conversion film and the photoelectric conversion layer.

Abstract: An integrated circuit device in which an array of photodiodes are formed at the surface of a semiconductor substrate. A dielectric structure comprising multiple layers of dielectric is formed over the photodiodes. An array of color filters is formed over the photodiodes and within the dielectric structure. An interface between two layers of the dielectric structure is aligned with the bases of the color filters. The interface provides an etch stops that allows the depths of the trenches in which the color filters are formed to be well controlled.

Abstract: A solar cell structure includes P-type and N-type doped regions. A dielectric spacer is formed on a surface of the solar cell structure. A metal layer is formed on the dielectric spacer and on the surface of the solar cell structure that is exposed by the dielectric spacer. A metal foil is placed on the metal layer. A laser beam is used to weld the metal foil to the metal layer. A laser beam is also used to pattern the metal foil. The laser beam ablates portions of the metal foil and the metal layer that are over the dielectric spacer. The laser ablation of the metal foil cuts the metal foil into separate P-type and N-type metal fingers.