Light Patents (Class 257/431)
  • Patent number: 9000541
    Abstract: A photoelectric conversion device includes circuit portions disposed on a substrate, a first electrode electrically connected to one of the circuit portions, an optically transparent second electrode opposing the first electrode, and a photoelectric conversion portion disposed between the first electrode and the second electrode. The photoelectric conversion portion has a multilayer structure including a light absorption layer made of a p-type compound semiconductor film having a chalcopyrite structure, an amorphous oxide semiconductor layer, and a window layer made of an n-type semiconductor film.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: April 7, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Yasunori Hattori, Tomotaka Matsumoto, Tsukasa Eguchi
  • Patent number: 9000351
    Abstract: A resistor array is provided in an element array. A mean value of a characteristic-value distribution is associated with a median of combined resistance values obtained by the element array. An array of trimming information pieces corresponding to combined resistance values larger than the median is set in a descending order of ‘15’ to ‘8’ in decimal number, and an array of trimming information pieces corresponding to combined resistance values less than the median is set in an ascending order of ‘0’ to ‘7’ in decimal number. A circuit converts trimming information derived from the trimming information generation circuit to generate element selection information for selecting turn-off resistors to obtain combined resistance values from the resistor array. Thus, the number of melted-and-cut fuses involved in generation of trimming information associated within the range of “mean value±2?” in the distribution is reduced.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuo Noda, Takahiro Inoue
  • Patent number: 9000542
    Abstract: The present disclosure is directed to a device that includes a substrate and a sensor formed on the substrate. The sensor includes a chamber formed from a plurality of integrated cavities, a membrane above the substrate, the membrane having a plurality of openings, each opening positioned above one of the cavities, and a plurality of diamond shaped anchors positioned between the membrane and the substrate, the anchors positioned between each of the cavities. A center of each opening is also a center of one of the cavities.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Tien Choy Loh, Olivier Le Neel
  • Publication number: 20150091114
    Abstract: Provided herein is a novel stacked pixel design for image sensor applications. The stacked pixel designs may comprise a first and second wafer, wherein the first wafer is an elemental wafer comprising a photodiode and minimal additional components, such that material selection and processing steps of the first wafer may be optimized for the creation of a high quality photodiode. The second wafer comprises components necessary for the readout and reset of the photodiode on the first wafer.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 2, 2015
    Inventors: Barmak Mansoorian, Daniel Van Blerkom
  • Patent number: 8993950
    Abstract: In an embodiment, each of first and second pixel rows has pixels. A first transfer gate is arranged between the first and second pixel rows. Second transfer gates are arranged adjacently to odd-numbered pixels of the second pixel row, respectively. Third transfer gates are arranged adjacently to even-numbered pixels of the second pixel row, respectively. A first CCD register is arranged adjacently to the second transfer gates and third transfer gates. Fourth transfer gates are arranged adjacently to odd-numbered accumulation gates of the first CCD register. A second CCD register is arranged adjacently to the fourth transfer gates. An output portion converts transferred charges into a voltage signal. A clear gate controls draining of the charges accumulated in the first pixel row to a first drain portion. A switch gate controls draining of charges transferred in a row direction in the second CCD register to a second drain portion.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masao Takahashi
  • Patent number: 8994132
    Abstract: A photoelectric conversion element includes an insulating film, a first electrode, a light receiving layer, and a second electrode. The first electrode is formed on the insulating film and is made of titanium oxynitride. The light receiving layer is formed on the first electrode and includes an organic material. A composition of the first electrode just before forming the light receiving layer meets (1) a requirement that an amount of oxygen contained in the whole of the first electrode is 75 atm % or more of an amount of titanium, or (2) a requirement that in a range of from the substrate side of the first electrode to 10 nm or a range of from the substrate side of the first electrode to ? of the thickness of the first electrode, an amount of oxygen is 40 atm % or more of an amount of titanium.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: March 31, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Tetsuro Mitsui, Yuki Kuramoto
  • Patent number: 8994041
    Abstract: This photodiode array module includes a first semiconductor substrate 2 having a first photodiode array that is sensitive to light of a first wavelength band, a second semiconductor substrate 2? having a second photodiode array that is sensitive to light of a second wavelength band, and a third semiconductor substrate 3 which is formed with a plurality of amplifiers AMP and on which the first and second semiconductor substrates 2, 2? are placed side by side without overlapping, and which connects each photodiode to the amplifier AMP via a bump. In adjacent end portions of the first semiconductor substrate 2 and the second semiconductor substrate 2?, stepped portions are formed, which thus allows performing measurement with low noise even when respective pixels are aligned successively over both substrates.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: March 31, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Masatoshi Ishihara, Nao Inoue, Hirokazu Yamamoto
  • Patent number: 8994051
    Abstract: In a light emission module (40), a light wavelength conversion ceramic (52) is formed in a sheet shape which converts the wavelength of the light emitted from a semiconductor light emission element (48) when emitting the light. The light wavelength conversion ceramic (52) has a tapered plane (52a) which is inclined to approach the semiconductor light emission element (48) toward the brim portion. The light wavelength conversion ceramic (52) is transparent and is arranged so that the light emission wavelength band after the conversion has an all ray permeability of 40% or above.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 31, 2015
    Assignee: Koito Manufacturing Co., Ltd.
    Inventors: Hisayoshi Daicho, Tatsuya Matsuura, Yasuaki Tsutsumi, Masanobu Mizuno, Shogo Sugimori
  • Publication number: 20150083211
    Abstract: The present disclosure provides a photoelectric conversion layer containing a semiconductor and plural metal-containing minute structures dispersed therein. The minute structures are minute structures (A) comprising metal material (?) or otherwise minute structures (B) comprising metal material (?) and material (?) selected from the group consisting of oxide, nitride and oxynitride of substances and the semiconductor. In the minute structures (B), the material (?) is on the surface of the metal material (?). Each of the minute structures has an equivalent circle diameter of 1 nm to 10 nm inclusive on the basis of the projected area when observed from a particular direction. The closest distance between adjacent two of the minute structures is 3 nm to 50 nm inclusive. The present disclosure also provides applications of the photoelectric conversion layer to a solar cell, a photodiode and an image sensor.
    Type: Application
    Filed: September 17, 2014
    Publication date: March 26, 2015
    Inventors: Akira FUJIMOTO, Takeshi IWASAKI, Kaori KIMURA, Kazutaka TAKIZAWA, Kenji NAKAMURA, Shigeru MATAKE
  • Patent number: 8987738
    Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Hirose, Naoto Kusumoto
  • Patent number: 8981509
    Abstract: A light receiving layer is formed with an array of photodiodes for accumulating signal charge produced by photoelectric conversion of incident light. A wiring layer provided with electrodes and wiring for controlling the photodiodes is formed behind the light receiving layer in a traveling direction of the incident light. In the light receiving layer, there is formed a projection and depression structure in which a pair of inclined surfaces have symmetric inclination directions and each inclined surface corresponds to each photodiode. Each inclined surface makes the incident light enter each photodiode by a light amount corresponding to an incident angle.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 17, 2015
    Assignee: FUJIFILM Corporation
    Inventor: Makio Nishimaki
  • Patent number: 8975715
    Abstract: A photodetector includes a substrate and an insulating arrangement formed in the substrate. The insulating arrangement electrically insulates a confined region of the substrate. The confined region is configured to generate free charge carriers in response to an irradiation. The photodetector further includes a read-out electrode arrangement configured to provide a photocurrent formed by at least a portion of the free charge carriers that are generated in response to the irradiation. The photodetector also includes a biasing electrode arrangement that is electrically insulated against the confined region by means of the insulating arrangement. The biasing electrode arrangement is configured to cause an influence on a spatial charge carrier distribution within the confined region so that fewer of the free charge carriers recombine at boundaries of the confined region compared to an unbiased state.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventor: Thoralf Kautzsch
  • Publication number: 20150061060
    Abstract: A method of manufacturing a semiconductor device provided with an interlayer insulating film formed on a semiconductor substrate, and a plurality of wiring layers formed on the interlayer insulating film. The method includes forming of a first wiring layer closest to the semiconductor substrate among the plurality of wiring layers, and forming of an alloy of a titanium layer and a metal layer by heating treatment. The forming of the first wiring layer includes: forming of a titanium layer on an interlayer insulating film; forming of a metal layer containing a metal capable of forming an alloy with titanium in the titanium layer; forming of an orientation layer on the metal layer; and forming of an aluminum layer on the orientation layer.
    Type: Application
    Filed: August 25, 2014
    Publication date: March 5, 2015
    Inventor: Yukinobu Suzuki
  • Patent number: 8963265
    Abstract: A graphene based detector device can include a source, a drain, and a gate. The gate can incorporate a discharging element and a graphene sheet that is proximate to the discharging element. The graphene sheet for the transistor can have a decreasing width, from a maximum width w2 distal to the discharging element to a minimum width w1 proximate to the discharging element. An electric potential can be established across graphene sheet, to facilitate funneling of the electrons from the graphene sheet (which are caused by quanta of electromagnetic radiation) toward the discharging element. The devices can be formed in an array to establish an antenna that operates according to the quantum nature of light, as opposed to resonance (wavelength). Multiple graphene layers that are doped using different materials can be included. The multiple layer funnel electrons at specific frequencies, to create an operating frequency range for the device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 24, 2015
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventors: Marclo C. de Andrade, Anna M. Leese de Escobar, David Garmire, Nackieb Kamin
  • Patent number: 8963266
    Abstract: A device having a detector includes a sensor package. The sensor package includes a light sensor, at least one filter located over the light sensor and at least one bond pad. The light sensor is formed on a semiconductor device that provides sensor information related to light incident upon the light sensor. A perimeter of each bond pad is covered by a protective layer forming a sidewall seal. The sensor package also includes a package that encases the light sensor, filter(s) and bond pad(s). Additionally, at least one package pin is communicatively coupled to the bond pad(s). The device also includes a functional circuit that is coupled to the sensor package and receives the sensor information from the light sensor. The device can be an ambient light sensor, camera, backlit mirror, handheld electronic device, filter device, light-to-digital output sensor, gain selection device, proximity sensor, or light-to-voltage non-linear converter.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: February 24, 2015
    Assignee: Intersil Americas LLC
    Inventors: Helen Hongwei Li, Joy Ellen Jones, Phillip J. Benzel, Jeanne M. McNamara, John T. Gasner
  • Patent number: 8962376
    Abstract: An optoelectronic device, including a semiconductor body having a surface to receive photons and a plurality of doped regions of opposite doping polarities, the doped regions extending substantially from the surface of the semiconductor body and into the semiconductor body, and being arranged in one or more pairs of opposite doping polarities such that each pair of doped regions forms a corresponding space charge region having a corresponding electric field therein, the space charge region extending substantially from the surface of the semiconductor body and into the semiconductor body such that photons entering the semiconductor body through the surface and travelling along paths within the space charge region generate electron-hole pairs in the space charge region that are separated in opposing directions substantially orthogonal to the photon paths by the electric field and collected by the corresponding pair of doped regions, thereby providing an electrical current to be conducted from the device.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: February 24, 2015
    Assignee: The Silanna Group Pty Ltd
    Inventors: Petar Branko Atanackovic, Steven Grant Duvall
  • Publication number: 20150048466
    Abstract: The present invention provides an image sensor and a fabricating method of the image sensor. The image sensor comprises: a first type epitaxial layer, a photodiode region, a first type well region, a gate region of a source follower transistor, and a first type implant isolation region. The first type well region is formed within the first type epitaxial layer with a first horizontal distance to the photodiode region and a vertical distance to a surface of the first type epitaxial layer. The gate region of a source follower transistor is formed on the surface of the first type epitaxial layer and above the first type well region, and has a second horizontal distance to the photodiode region. There is a distance between the first type implant isolation region and the first type well region as an anti-blooming path.
    Type: Application
    Filed: March 12, 2014
    Publication date: February 19, 2015
    Applicant: Himax Imaging, Inc.
    Inventors: Yang Wu, Feixia Yu, Inna Patrick, Yu Hin Desmond Cheung
  • Patent number: 8957488
    Abstract: A system and method for fabricating a self-powering integrated circuit chip having an integrated circuit, which may be a MEMS or CMOS device or the like and a thin film photovoltaic cell stack overlayed thereupon or on the opposite side of the substrate on which the IC is manufactured upon.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 17, 2015
    Assignee: Sol Chip Ltd.
    Inventors: Shani Keysar, Ofer Navon
  • Patent number: 8957489
    Abstract: A component assembly including a carrier element including a first contact face and a semiconductor component disposed on the carrier element, wherein the semiconductor component includes a second contact face. The component assembly further includes a contact-making bonding wire, wherein one end of the contact-making bonding wire is connected to the first contact face and a second end of the contact-making bonding wire is connected to the second contact face. The component assembly includes a flow stop bonding wire positioned on the second contact face, wherein the flow stop bonding wire defines on the second contact face a first zone and a second zone. An encapsulation material is applied from the first zone to the first contact face so as to define an encapsulation for the flow stop bonding wire, wherein the flow stop bonding wire prevents an uncontrolled flow of the encapsulation material into the second zone.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: February 17, 2015
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventor: Roman Angerer
  • Publication number: 20150041945
    Abstract: A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 12, 2015
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 8952473
    Abstract: A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: February 10, 2015
    Assignee: Sol Chip Ltd.
    Inventors: Shani Keysar, Reuven Holzer, Ofer Navon, Rami Friedlander
  • Patent number: 8947566
    Abstract: The first face of the pad is situated between the front-side face of the second semiconductor substrate and a hypothetical plane including and being parallel to the front-side face, and a second face of the pad that is a face on the opposite side of the first face is situated between the first face and the front-side face of the second semiconductor substrate, and wherein the second face is connected to the wiring structure so that the pad is electrically connected to the circuit arranged in the front-side face of the second semiconductor substrate via the wiring structure.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: February 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Kobayashi, Mineo Shimotsusa
  • Patent number: 8946846
    Abstract: Conductive layer(s) in a thin film photovoltaic (TFPV) panel are divided by first scribe curves into photovoltaic cells connected in series. At least one of the layers is scribed to isolate a shunt defect in a cell from parts of that cell away from the defect. The isolation scribes can substantially follow or parallel current-flow lines established by the design of the panel. A TFPV panel can be altered by, using a controller, automatically locating a shunt defect and scribing at least one of the conductive layers along two spaced-apart second scribe curves. Each second scribe curve can intersect the two first scribe curves that bound the cell with the defect. The two second scribe curves can be on opposite sides of the defect.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 3, 2015
    Assignee: Purdue Research Foundation
    Inventors: Muhammad Ashraful Alam, Sourabh Dongaonkar
  • Patent number: 8946616
    Abstract: An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Woo Kim, Seog Heon Ham, Kyung-Min Kim, Yong Lim
  • Patent number: 8946841
    Abstract: Disclosed herein is a solid-state imaging element including: a semiconductor layer; a plurality of photoelectric conversion sections arranged within the semiconductor layer; and a pixel separating section disposed in a shape of a same width from a light receiving surface of the semiconductor layer to an opposite surface of the semiconductor layer from the light receiving surface in a position of separating the photoelectric conversion sections from each other for each pixel, the pixel separating section being formed by a material including an impurity.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventor: Masashi Nakazawa
  • Patent number: 8946839
    Abstract: An absorber is disclosed. The disclosed absorber contains a base layer, and a plurality of pillars disposed above the base layer and composed of material configured to absorb an incident light and generate minority electrical carriers and majority electrical carrier, wherein the height of the pillars is predetermined to provide a common pyramidal outline shared by the pillars in the plurality of pillars.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: February 3, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, James H. Schaffner
  • Publication number: 20150028441
    Abstract: A semiconductor element includes a CdTe-based semiconductor material and a number of connection points of the semiconductor element to connect to electronic components. In at least one embodiment, the connection points are provided with a special solder resist layer including a mixture AB of at least two metals with different coefficients of expansion. In at least one embodiment, a radiation detector includes such a semiconductor element and optionally includes evaluation electronics for reading out a detector signal. In at least one embodiment, a medical technology device includes such a radiation detector. Furthermore, a method is disclosed for creating a semiconductor element which includes applying a solder resist layer to connection points. In at least one embodiment, the solder resist layer includes a mixture of at least two metals with different coefficients of expansion.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 29, 2015
    Inventor: Christian SCHRÖTER
  • Patent number: 8941203
    Abstract: Methods and structures for providing single-color or multi-color photo-detectors leveraging plasmon resonance for performance benefits. In one example, a radiation detector includes a semiconductor absorber layer having a first electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region, a semiconductor collector layer coupled to the absorber layer and having a second electrical conductivity type, and a plasmonic resonator coupled to the collector layer and having a periodic structure including a plurality of features arranged in a regularly repeating pattern.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: January 27, 2015
    Assignee: Raytheon Company
    Inventors: Justin Gordon Adams Wehner, Edward Peter Gordon Smith
  • Patent number: 8937342
    Abstract: A CMOS image sensor includes an active pixel structure suitable for sensing light incident from outside and converting a sensed light into an electrical signal, and an optical block structure suitable for blocking a visible light and passing a UV light to check and evaluate an electrical characteristic of the active pixel area. The UV pass filter includes first and second insulation layers comprising an insulator, and a metal layer formed between the first and second insulation layers.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: January 20, 2015
    Assignees: SK Hynix Inc., Postech Academy-Industry Foundation
    Inventors: Do Hwan Kim, Su Hwan Lim, Hae Wook Han, Young Woong Do, Won Jun Lee
  • Publication number: 20150008552
    Abstract: A wiring is located on a multilayer ceramic substrate. A ceramic block is located on the multilayer ceramic substrate. Electronic parts, including a semiconductor laser, are located on a surface of the ceramic block. A wiring located on the surface of the ceramic block connects some of the electronic parts to the wiring. A metallic cap with a glass window is located on the multilayer ceramic substrate. This metallic cap covers the ceramic block and the electronic parts, including the semiconductor laser.
    Type: Application
    Filed: April 4, 2012
    Publication date: January 8, 2015
    Inventor: Akihiro Matsusue
  • Publication number: 20150008551
    Abstract: A semi-conducting structure, configured to receive an electromagnetic radiation and to transform the electromagnetic radiation into an electric signal, including: a first zone and a second zone of a same conductivity type and of same elements; a barrier zone, provided between the first and second zones, for acting as a barrier to majority carriers of the first and second zones on a barrier thickness, the barrier zone having its lowest bandgap energy defining a barrier proportion; and a first interface zone configured to interface the first zone and the barrier zone on a first interface thickness, the first interface zone including a composition of elements which is varied from a proportion corresponding to that of the first material to the barrier proportion, the first interface thickness being at least equal to half the barrier thickness.
    Type: Application
    Filed: January 2, 2013
    Publication date: January 8, 2015
    Applicant: Commissariat a l'energie atomique et aux ene alt
    Inventors: Olivier Gravrand, Alexandre Ferron
  • Patent number: 8927965
    Abstract: A light-receiving element includes a III-V group compound semiconductor substrate, a light-receiving layer having a type II multi-quantum well structure disposed on the substrate, and a type I wavelength region reduction means for reducing light in a wavelength region of type I absorption in the type II multi-quantum well structure disposed on a light incident surface or between the light incident surface and the light-receiving layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 6, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yasuhiro Iguchi, Hiroshi Inada
  • Patent number: 8928101
    Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; an insulation layer on the first semiconductor layer; a second semiconductor layer in the insulation layer; an active element in the second semiconductor layer; a first semiconductor region on the first semiconductor layer and of a second conductivity type; a second semiconductor region in the first semiconductor region and of the second conductivity type with a higher impurity concentration than the first semiconductor region; a first conductor in a through hole in the insulation layer and connected to the second semiconductor region; a second conductor above or within the insulation layer, the second conductor surrounding the first conductor such that an outside edge thereof is outside the second semiconductor region; a third conductor connecting the first and second conductors; and a fourth conductor connected to the first semiconductor layer.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: January 6, 2015
    Assignees: LAPIS Semiconductor Co., Ltd., RIKEN
    Inventors: Hiroki Kasai, Yasuo Arai, Takaki Hatsui
  • Publication number: 20150001657
    Abstract: The method for producing a photoelectric converter of the present invention comprises a preparation step for preparing a substrate (2) that has a photoelectric conversion layer (2a) and is formed from silicon; a first film-formation step for the formation of a first protective film (3) by deposition of aluminum oxide on a top surface (2B) of the substrate (2) using the atom deposition method or chemical vapor deposition method in an atmosphere containing hydrogen; and a second film-formation step for forming a second protective film (4) by deposition of aluminum oxide on the first protective film (3) using sputtering after the first film-formation step.
    Type: Application
    Filed: January 30, 2013
    Publication date: January 1, 2015
    Applicant: KYOCERA Corporation
    Inventors: Shiro Miyazaki, Tomofumi Honjo, Koji Niwa, Hironori Kii, Shigeo Aono, Yosuke Nishioka
  • Patent number: 8921210
    Abstract: A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: December 30, 2014
    Assignee: Saint-Gobain Cristaux et Detecteurs
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 8921962
    Abstract: A magnetostrictive-piezoelectric multiferroic single- or multi-domain nanomagnet whose magnetization can be rotated through application of an electric field across the piezoelectric layer has a structure that can include either a shape-anisotropic mangnetostrictive nanomagnet with no magnetocrystalline anisotropy or a circular nanomagnet with biaxial magnetocrystalline anisotropy with dimensions of nominal diameter and thickness. This structure can be used to write and store binary bits encoded in the magnetization orientation, thereby functioning as a memory element, or perform both Boolean and non-Boolean computation, or be integrated with existing magnetic tunneling junction (MTJ) technology to perform a read operation by adding a barrier layer for the MTJ having a high coercivity to serve as the hard magnetic layer of the MTJ, and electrical contact layers of a soft material with small Young's modulus.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Virginia Commonwealth University
    Inventors: Jayasimha Atulasimha, Supriyo Bandyopadhyay
  • Patent number: 8921963
    Abstract: A photovoltaic cell such as a solar cell is disclosed. The cell comprises (a) a semiconductor substrate having a front surface, (b) one or more anti-reflection coating layers on the front surface of the semiconductor substrate, (c) a plurality of silver-containing fingers in contact with the one or more anti-reflection coating layers and in electrical contact with the semiconductor substrate; and (d) one or more base metal containing buss bars each in contact with the one or more anti-reflection coating layers and the silver-containing fingers. The base metal may be selected from one or more of copper, nickel, lead, tin, iron, indium, zinc, bismuth and cobalt. Methods for making photovoltaic cells with base metal containing buss bars are also disclosed.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 30, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: William J Borland, Alan Frederick Carroll, Barry Edward Taylor
  • Publication number: 20140374861
    Abstract: A method for manufacturing an epitaxial wafer for manufacture of an image pickup device, wherein, before the growth of the epitaxial layer, a thickness X of a region where oxygen concentration in the epitaxial layer becomes 4×1017 atoms/cm3 or more after the manufacture of the image pickup device is calculated and, in the growth of the epitaxial layer, the epitaxial layer is grown with a thickness such that a thickness of a region where the oxygen concentration in the epitaxial layer is less than 4×1017 atoms/cm3 after the manufacture of the image pickup device is 6 ?m or more in addition to the thickness X. As a result, it is possible to provide the epitaxial wafer in which an adverse effect of an impurity such as oxygen in the silicon wafer is not exerted on an image pickup device forming portion of the epitaxial layer and a manufacturing method thereof.
    Type: Application
    Filed: October 2, 2012
    Publication date: December 25, 2014
    Inventors: Ryoji Hoshi, Masahiro Sakurada, Izumi Fusegawa
  • Patent number: 8916877
    Abstract: A thin film transistor (TFT) comprises: an active layer formed on a substrate; a gate insulating layer formed on the active layer; a gate electrode including a first gate region and a second gate region formed on portions of the gate insulating layer and spaced apart with a separation region interposed therebetween; an interlayer insulating layer formed on the gate insulating layer and the gate electrode, and having an opening formed to expose portions of the gate insulating layer and the gate electrode around the separation region; a gate connection electrode formed on the interlayer insulating layer and connected to the first gate region and the second gate region through the opening; and source and drain electrodes formed on the interlayer insulating layer. The TFT and the OLED display device have excellent driving margin without a spatial loss.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 23, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Ho Yang, Seung-Gyu Tae
  • Patent number: 8916945
    Abstract: Prepared is an n? type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p+ type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p+ type semiconductor region 3 in the second principal surface 1b of the n? type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n? type semiconductor substrate 1 is formed on the second principal surface 1b side of the n type semiconductor substrate 1. After formation of the accumulation layer 11, the n? type semiconductor substrate 1 is subjected to a thermal treatment.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: December 23, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Akira Sakamoto, Takashi Iida, Koei Yamamoto, Kazuhisa Yamamura, Terumasa Nagano
  • Patent number: 8912615
    Abstract: The present invention is a photodiode or photodiode array having improved ruggedness for a shallow junction photodiode which is typically used in the detection of short wavelengths of light. In one embodiment, the photodiode has a relatively deep, lightly-doped P zone underneath a P+ layer. By moving the shallow junction to a deeper junction in a range of 2-5 ?m below the photodiode surface, the improved device has improved ruggedness, is less prone to degradation, and has an improved linear current.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 16, 2014
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 8912618
    Abstract: In particular embodiments, a method is described for depositing thin films, such as those used in forming a photovoltaic cell or device. In a particular embodiment, the method includes providing a substrate suitable for use in a photovoltaic device and plasma spraying one or more layers over the substrate, the grain size of the grains in each of the one or more layers being at least approximately two times greater than the thickness of the respective layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 16, 2014
    Assignee: AQT Solar, Inc.
    Inventors: Brian Josef Bartholomeusz, Michael Bartholomeusz
  • Patent number: 8907438
    Abstract: An organic diode operated in photovoltaic mode is used as a sensor for nitroaromatic electron accepting compounds. While illuminated by a light source with a wavelength within the organic materials absorption the device produces a small photovoltaic response due to inefficient separation of charges. Upon exposure to an electron accepting compound, the device produces an increase in photovoltaic activity due to more efficient charge separation, producing a larger measurable open circuit voltage. Upon removal of the compound the measured voltage decreases and returns to near its baseline value.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: December 9, 2014
    Assignee: The United States of America as Represented by the Secretary of the Army
    Inventor: Eric C. Nallon
  • Patent number: 8907717
    Abstract: The light receiving circuit includes: a photoelectric conversion element for causing a current corresponding to an amount of incident light to flow; a MOS transistor including a source connected to the photoelectric conversion element and a drain connected to a node, for causing the current of the photoelectric conversion element to flow to the node while maintaining a voltage of the source to a first voltage; a reset circuit for causing a current to flow from the node to a GND terminal so that a voltage of the node becomes a second voltage lower than the first voltage; a control circuit for outputting a reset signal to the reset circuit; and a voltage increase detection circuit for detecting a fluctuation in the voltage of the node and outputting a detection result.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 9, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 8907386
    Abstract: In a linear image sensor 1 according to an embodiment of the present invention, a plurality of embedded photodiodes PD(n) of an elongated shape are arrayed. Each of the embedded photodiodes PD(n) comprises a first semiconductor region 10 of a first conductivity type; a second semiconductor region 20 formed on the first semiconductor region 10, having a low concentration of an impurity of a second conductivity type, and having an elongated shape; a third semiconductor region 30 of the first conductivity type formed on the second semiconductor region 20 so as to cover a surface of the second semiconductor region 20; and a fourth semiconductor region 40 of the second conductivity type for extraction of charge from the second semiconductor region 20; the fourth semiconductor region 40 comprises a plurality of fourth semiconductor regions arranged as separated in a longitudinal direction of the second semiconductor region on the second semiconductor region 20.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: December 9, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Keiichi Ota, Sadaharu Takimoto, Hiroshi Watanabe
  • Patent number: 8901628
    Abstract: In an image sensor 1 according to an embodiment of the present invention, a plurality of embedded photodiodes PD(m,n) are arrayed. Each of the embedded photodiodes PD(m,n) comprises a first semiconductor region 10 of a first conductivity type; a second semiconductor region 20 formed on the first semiconductor region 10 and having a low concentration of an impurity of a second conductivity type; a third semiconductor region 30 of the first conductivity type formed on the second semiconductor region 20 so as to cover a surface of the second semiconductor region 20; and a fourth semiconductor region 40 of the second conductivity type for extraction of charge from the second semiconductor region 20; the fourth semiconductor region 40 comprises a plurality of fourth semiconductor regions 40 arranged as separated, on the second semiconductor region 20.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: December 2, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Keiichi Ota, Sadaharu Takimoto, Hiroshi Watanabe
  • Patent number: 8900906
    Abstract: In one embodiment, a method of forming a semiconductor device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a first trench in the sacrificial layer, forming a first sidewall layer with a thickness of less than about 50 nm on a first sidewall of the first trench using atomic layer deposition (ALD), and removing the sacrificial layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 2, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Gary Yama, Fabian Purkl, Matthieu Liger, Matthias Illing
  • Patent number: 8901691
    Abstract: A touch sensing substrate includes a substrate, a first light sensing element, a second light sensing element and a first bias line. The first light sensing element includes a first gate electrode, a first active pattern overlapping with the first gate electrode, a first source electrode partially overlapping with the first active pattern and a first drain electrode partially overlapping with the first active pattern. The second light sensing element includes a second gate electrode, a second active pattern overlapping with the second gate electrode, a second source electrode partially overlapping with the second active pattern and a second drain electrode partially overlapping with the second active pattern. The first bias line is connected to the first and second gate electrodes.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Jong Yeo, Byeong-Hoon Cho, Ki-Hun Jeong, Hong-Kee Chin, Jung-Suk Bang, Woong-Kwon Kim, Sung-Ryul Kim, Hee-Joon Kim, Dae-Cheol Kim, Kun-Wook Han
  • Patent number: 8901541
    Abstract: A photoelectric conversion device includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, an electrode provided on the insulating layer, a photoelectric conversion film provided on the electrode for converting received light to charges, a line connected between the electrode and the semiconductor substrate, a first planar electrode provided in the insulating layer and connected to the electrode, and a second planar electrode provided in the insulating layer between the first planar electrode and the semiconductor substrate.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: December 2, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Hiroshi Nishiyama, Takashi Esumi
  • Patent number: 8901694
    Abstract: An optical input/output (I/O) device is provided. The device includes a substrate including an upper trench; a waveguide disposed within the upper trench of the substrate; a photodetector disposed within the upper trench of the substrate and comprising a first end surface optically connected to an end surface of the waveguide; and a light-transmitting insulating layer interposed between the end surface of the waveguide and the first end surface of the photodetector.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Joong-Han Shin, Byung-Lyul Park, Gil-Heyun Choi