Abstract: In the solar cell module 1, one finger electrode 30 is branched into multiple branched portions 30a in an intersecting region ? where the one finger electrode 30 intersects a conductive body including a wiring member 40 configured to collect photo-generated carriers from the finger electrode 30.

Abstract: A solid-state imaging device includes an imaging element, an external terminal, an insulating film, a through-electrode and a first electrode. The imaging element is formed on a first major surface of a semiconductor substrate. The external terminal is formed on a second major surface opposing the first major surface of the semiconductor substrate. The insulating film is formed in a through-hole formed in the semiconductor substrate. The through-electrode is formed on the insulating film in the through-hole and electrically connected to the external terminal. The first electrode is formed on the through-electrode on the first major surface of the semiconductor substrate. When viewed from a direction perpendicular to the first major surface of the semiconductor substrate, an outer shape with which the insulating film and the semiconductor substrate are in contact is larger than an outer shape of the first electrode.

Abstract: The wiring arrangement length in a photoreceiving device is shortened. The photoreceiving device includes an amplifier for amplifying an output of the photoreceiving element and a photoreceiving element and they are mounted at a base member. A plurality of first bonding pads and a plurality of second bonding pads for connection to power supply are provided at both sides of a transmission path of an input or output signal of a photoreceiving element. Furthermore, at a position other than the parts arrangement surface of the base member, a plurality of first bonding pads are electrically connected to a plurality of second bonding pads.

Abstract: A substrate has a plurality of pads formed over one surface of a base, and an insulating film which is formed thereon and has a plurality of openings formed therein so as to expose each of the pads, wherein the openings of the insulating film are formed so that, in each pad formed at the corner of the base, among the plurality of pads, a first peripheral portion which composes a portion of the pad more closer to the corner and more distant away from the center of the base is covered by the insulating film, and so that a second peripheral portion which composes a portion of the pad more closer to the center as compared with the first peripheral portion is exposed in the opening.

Abstract: A photovoltaic device includes a substrate, the substrate having a base region and an emitter region, the base region having a first width and the emitter region having a second width, a first electrode in contact with and electrically connected to the base region, the first electrode having a third width where it overlies the base region, the third width being greater than the first width such that the first electrode overhangs the base region at at least one side thereof, and a second electrode in contact with and electrically connected to the emitter region, the second electrode having a fourth width where it overlies the emitter region, a ratio of the third width to the fourth width being about 0.3 to about 3.4.

Abstract: According to at least one embodiment of the semiconductor arrangement, the latter comprises a mounting side, at least one optoelectronic semiconductor chip with mutually opposing chip top and bottom, and at least one at least partially radiation-transmissive body with a body bottom, on which the semiconductor chip is mounted such that the chip top faces the body bottom. Moreover, the semiconductor arrangement comprises at least two electrical connection points for electrical contacting of the optoelectronic semiconductor chip, wherein the connection points do not project laterally beyond the body and with their side remote from the semiconductor chip delimit the semiconductor arrangement on the mounting side thereof.

Abstract: Processes for fabricating back contacts for photovoltaic cell devices are disclosed. The processes involve depositing a passivation layer on the back surface of a wafer, depositing an emitter layer on the passivation layer, depositing a metal layer on the emitter layer, laser firing selected areas of the metal layer to form base contacts, laser cutting the metal layer to create at least one isolation region between emitter contacts and base contacts, and applying a stream of reactive gas to form a second passivation layer in the isolation region. The process may further involve inkjetting a resist on the passivation layer in a pattern corresponding to a boundary between the one or more emitter contacts and the one or more base contacts, and laser cutting the metal layer over the resist to create the isolation region.

Abstract: A solar cell includes a semiconductor substrate having a photoelectric converting portion, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode connected to the first electrode on the first main surface. The first electrode includes a plurality of first connecting portions to be connected to an interconnector and a first non-connecting portion not connected to an interconnector. The first non-connecting portion is arranged between first connecting portions to electrically connect the first connecting portions together. The first connecting portion and first non-connecting portion are coupled forming an angle larger than 90° and smaller than 180°. A solar cell string and a solar cell module employ the solar cells.

Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Abstract: An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.

Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer which is disposed on the base substrate and has a front surface and a rear surface opposite to the front surface; first ohmic electrodes disposed on the front surface of the first semiconductor layer; a second ohmic electrode disposed on the rear surface of the first semiconductor layer; a second semiconductor layer interposed between the first semiconductor layer and the first ohmic electrodes; and a Schottky electrode part which covers the first ohmic electrodes on the front surface of the first semiconductor layer.

Abstract: The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer.

Abstract: A chip-to-chip multi-signaling communication system with common conductive layer, which comprises a first chip, a second chip, and a common conductive layer, is disclosed. The first chip has at least a first metal pad and a second metal pad. The second chip has at least a first metal pad and a second metal pad. The common conductive layer is to a conductive material and glued directly to the first chip and the second chip. Wherein, the first metal pad of the second chip is aligned with the first metal pad of the first chip for receiving the signal from the first metal pad of the first chip through the common conductive layer. The interference generated by other pads of the first and the second chips is suppressed by the design of the pads and the common conductive layer.

Abstract: Provided is an organic pixel, which includes a semiconductor substrate including a pixel circuit, an interconnection layer having a first contact and a first electrode formed on a semiconductor substrate, and an organic photo-diode formed on the interconnection layer. For example, the organic photo-diode includes an insulation layer formed on the first electrode, a second electrode and a photo-electric conversion region formed between the first contact, the insulation layer and the second electrode. The photo-electric conversion region includes an electron donating organic material and an electron accepting organic material. The organic photo-diode may further include a second contact electrically connected to the first contact. The horizontal distance between the second contacts and the insulation layer may be less than or equal to a few micrometers, for example, 10 micrometers.

Abstract: A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from each other and enclosing the plurality of the pads. The plurality of dummy patterns also include a plurality of peripheral dummy patterns and a plurality of central dummy patterns, wherein a minimum distance between the plurality of the central dummy patterns and the plurality of the pads is greater a minimum distance between the plurality of the peripheral dumpy patterns and the plurality of the pads.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, forming vias that pass through the anti-reflective layer and the back side dielectric layer and contact back sides of super contacts which are formed on the Si substrate, and forming a pad on the back side dielectric layer such that the pad is electrically connected to the vias.

Abstract: An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a dielectric layer, a pad structure and a protection structure. The dielectric layer is disposed on the substrate. The pad structure is disposed in the dielectric layer. The pad structure includes a plurality of first metal layers and a plurality of plugs which are electrically connected to each other vertically. There is no contact plug disposed between the pad structure and the substrate. The protection structure is disposed in the dielectric layer and encompasses the pad structure.

Abstract: Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.

Abstract: A semiconductor component, especially a solar cell comprises a semiconductor substrate of a planar design having a first side and a second side lying opposite thereto, at least one contact structure arranged on at least one side of the semiconductor substrate, the at least one contact structure exhibiting a diffusion barrier to prevent the diffusion of ions from the contact structure into the semiconductor substrate.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.

Abstract: A thin film transistor array panel can include: a substrate; a gate line formed on the substrate; a gate pad formed at an end of the gate line; a gate identification member corresponding to the gate pad and formed in the same layer as the gate pad; a gate insulating layer covering the gate line and the gate identification member; a data line formed on the gate insulating layer; a passivation layer formed on the gate insulating layer and the data line; a gate contact assistant formed on the passivation layer; and a gate driving chip electrically connected to the gate contact assistant, wherein the gate contact assistant at least partially overlaps the gate identification member. The gate identification member is formed without producing a step in the gate contact assistant, reducing the risk of defects when wires or other objects are pressed onto the gate pad.

Abstract: The invention provides a compact camera module. The compact camera module includes an image sensing device, a set of optical elements, and a zooming device. The set of optical elements connects to the image sensing device, and comprises a lens set. The zooming device connects to the set of optical elements for adjusting a distance between the lens set and the image sensing device. The zooming device directly electrically joins with the image sensing device.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure comprises a device substrate having a front side and a back side; an interconnect structure disposed on the front side of the device substrate; and a bonding pad connected to the interconnect structure. The bonding pad comprises a recessed region in a dielectric material layer; a dielectric mesa of the dielectric material layer interposed between the recessed region; and a metal layer disposed in the recessed region and on the dielectric mesa.

Abstract: A semiconductor device comprises a semiconductor substrate, and a multilayer wiring structure arranged on the semiconductor substrate, the multilayer wiring structure including a plurality of first electrically conductive lines, an insulating film covering the plurality of first electrically conductive lines, and a second electrically conductive line arranged on the insulating film so as to intersect the plurality of first electrically conductive lines, where the insulating film has gaps in at least some of a plurality of regions where the plurality of first electrically conductive lines and the second electrically conductive line intersect each other, and the width of the gap in a direction along the second electrically conductive line is not larger than the width of the first electrically conductive line.

Abstract: A semiconductor light receiving device includes: a first semiconductor light receiving element that is provided on a semiconductor substrate and has a mesa structure having an upper electrode to be coupled to an electrode wiring of a mounting carrier and a lower electrode; a first mesa that is provided on the semiconductor substrate and has an upper electrode coupled electrically to a lower electrode of the first semiconductor light receiving element with a wiring provided on the semiconductor substrate; and a second mesa that is provided on the semiconductor substrate and has an upper electrode that has a same electrical potential as the upper electrode of the first semiconductor light receiving element when coupled to the electrode wiring on the mounting carrier.

Abstract: A solar cell includes a p-type semiconductor substance, and an n-type semiconductor substance. The p-type semiconductor substance and the n-type semiconductor substance form a pn junction or a pin junction, and the p-type semiconductor substance or the n-type semiconductor substance includes a structure film having a plurality of carbon nanotubes electrically connected to each other.

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract: The surrounding length of a junction separation portion can be shortened to improve an insulating resistance in order to provide a solar cell with highly efficiency. In a photoelectric transducer of the type where a light-receiving surface electrode is wired to another electrode on a back surface via a through electrode passing through a semiconductor substrate of a first conductive type, the photoelectric transducer comprises: a junction separation portion made around the through electrode on a back surface of the semiconductor substrate; a dielectric layer formed for covering the junction separation portion, the through electrode penetrating the dielectric layer; and a back electrode provided on the dielectric layer and coupled to the through electrode which is connected to the light-receiving surface electrode.

Abstract: A method of bonding a semiconductor substrate having a substrate 11 formed with a MEMS sensor and a substrate 21 having a bonding portion 30b film-formed by contacting an aluminum containing layer 31 with a germanium layer 32 on either a front surface or a rear surface and formed with an integrated circuit that controls the MEMS sensor, either a front surface or a rear surface of the substrate 11 is put to contact directly on the bonding portion of the substrate 21 to bond by eutectic bonding with pressurization and heating.

Abstract: (Problems) To provide an integrated circuit having the wiring structure including pads with a small wiring area and capable of highly integrating elements, a solid image pickup element having the wiring structure, and an imaging device having the solid image pickup element.

Abstract: A semiconductor light-detecting element includes: a semiconductor substrate of a first conductivity type having a band gap energy, a first principal surface, and a second principal surface opposed to the first principal surface; a first semiconductor layer of the first conductivity type on the first principal surface and having a band gap energy smaller than the band gap energy of the semiconductor substrate; a second semiconductor layer of the first conductivity type on the first semiconductor layer; an area of a second conductivity type on a part of the second semiconductor layer; a first electrode connected to the second semiconductor layer; a second electrode connected to the area; and a low-reflection film on the second principal surface. The second principal surface is a light-detecting surface detecting incident light, and no substance or structure having a higher reflection factor, with respect to the incident light, than the low-reflection film, is located on the second principal surface.

Abstract: A CMOS image sensor array has rows and columns of active pixels, and column lines in communication with the active pixels in the respective columns. Each active pixel has an output connected to a column line and includes a photodetector that produces a signal proportional to incident light intensity that is coupled to an active pixel output based on column select and row select signals. Each active pixel has a reset transistor for resetting the active pixel, wherein each reset transistor has a first gate terminal and a second gate terminal. The reset transistors have a variable threshold capability that allows increased sensor array dynamic range or mitigation of the effects of temperature or radiation induced transistor threshold voltage shifts. Row select, column select, and sense transistors can also be configured to have variable thresholds.

Abstract: A process for forming at least one transistor on a substrate is described. The substrate comprises a polyimide and a nanoscopic filler. The polyimide is derived substantially or wholly from rigid rod monomers and the nanoscopic filler has an aspect ratio of at least 3:1. The substrates of the present disclosure are particularly well suited for thin film transistor applications, due at least in part to high resistance to hygroscopic expansion and relatively high levels of thermal and dimensional stability.

Abstract: Provided are an image sensor and a method for manufacturing the same. The image sensor comprises a semiconductor substrate, an interconnection and an interlayer dielectric, a lower electrode layer, an image sensing device, a first via hole, a barrier pattern, a second via hole, and a metal contact. The semiconductor substrate comprises a readout circuitry. The interconnection and the interlayer dielectric are formed on the semiconductor substrate. The lower electrode layer is disposed over the interlayer dielectric. The image sensing device is disposed on the lower electrode layer. The first via hole is formed through the image sensing device. The barrier pattern is formed on a sidewall of the first via hole. The second via hole is formed through the lower electrode layer and the interlayer dielectric under the first via hole. The metal contact is formed in the first and second via holes.

Abstract: A silicon drift detector (SDD) comprising electrically isolated rings. The rings can be individually biased doped rings. One embodiment includes an SDD with a single doped ring. Some of the doped rings may not require a bias voltage. Some of the rings can be field plate rings. The field plate rings may all use the same biasing voltage as a single outer doped ring. The ring widths can vary such that the outermost ring is widest and the ring widths decrease with each subsequent ring towards the anode.

Abstract: According to one embodiment, a position sensitive detector (PSD) comprises a plurality of layers, including a substrate layer, an absorber layer, a barrier layer, a sheet layer, and a contact layer. The absorber layer absorbs incident photons such that the absorbed photons excite positive charges and negative charges in the absorber layer. The barrier layer collects a photocurrent from the absorber layer, the photocurrent comprising either the positive charges or the negative charges. The sheet layer provides resistance to control the flow of the photocurrent between a point of incidence of the photons and a plurality of interconnect contacts. The contact layer comprises the interconnect contacts, each interconnect contact operable to conduct the photocurrent to one or more electrical components external to the PSD. The position sensitive detector facilitates determining the point of incidence of the photons according to a relative amount of photocurrent associated with each interconnect contact.

Abstract: An electrode includes a substantially planar metallic thin film layer with a patterned structure including a plurality of parallel lines or a plurality of crossed lines, the metallic thin film layer configured to transmit an incident light through the metallic thin film layer.

Abstract: Lateral collection photovoltaic (LCP) structures based on micro- and nano-collecting elements are used to collect photogenerated carriers. In one set of embodiments, the collecting elements are arrayed on a conducting substrate. In certain versions, the collecting elements are substantially perpendicular to the conductor. In another set of embodiments, the micro- or nano-scale collecting elements do not have direct physical and electrical contact to any conducting substrate. In one version, both anode and cathode electrodes are laterally arrayed. In another version, the collecting elements of one electrode are a composite wherein a conductor is separated by an insulator, which is part of each collector element, from the opposing electrode residing on the substrate. In still another version, the collection of one electrode structure is a composite containing both the anode and the cathode collecting elements for collection. An active material is positioned among the collector elements.

Abstract: A photoelectric conversion device includes: a first substrate of which end portions are cut off so as to slope or with a groove shape; a photodiode and an amplifier circuit over the first substrate; a first electrode electrically connected to the photodiode and provided over one end portion of the first substrate; a second electrode electrically connected to the amplifier circuit and provided over an another end portion of the first substrate; and a second substrate having third and fourth electrodes thereon. The first and second electrodes are attached to the third and fourth electrodes, respectively, with a conductive material provided not only at the surfaces of the first, second, third, and fourth electrodes facing each other but also at the side surfaces of the first and second electrodes to increase the adhesiveness between a photoelectric conversion device and a member on which the photoelectric conversion device is mounted.

Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.

Abstract: The present application is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present application is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate wafers. More specifically the photodiode array of the present application is fabricated such that the PN-junctions are located on both the front side and back side surfaces of the array, and wherein the front side PN-junction is in electrical communication with the back side PN-junction. Still more specifically, the present application is a photodiode array aving PN-junctions that are electrically connected from the front to back surfaces and which can be operated in a fully depleted mode at low reverse bias.

Abstract: An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.

Abstract: A photodiode array includes a substrate of a common read-out control circuit; and a plurality of photodiodes arrayed on the substrate and each including an absorption layer, and a pair of a first conductive-side electrode and a second conductive-side electrode. In this photodiode array, each of the photodiodes is isolated from adjacent photodiodes, the first conductive-side electrodes are provided on first conductivity-type regions and electrically connected in common across all the photodiodes, and the second conductive-side electrodes are provided on second conductivity-type regions and individually electrically connected to read-out electrodes of the read-out control circuit.

Abstract: The lattice mismatching between a Ge layer and a Si layer is as large as about 4%. Thus, when the Ge layer is grown on the Si layer, penetration dislocation is introduced to cause leakage current at the p-i-n junction. Thereby, the photo-detection sensitivity is reduced, and the reliability of the element is also lowered. Further, in the connection with a Si waveguide, there are also problems of the reflection loss due to the difference in refractive index between Si and Ge, and of the absorption loss caused by a metal electrode.

Abstract: An image sensor includes a unit cell having a plurality of pixels; the unit cell comprising an amplifier input transistor that is shared by the plurality of pixels; a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor; and an interconnect layer which forms an output signal wire which shields the floating diffusion interconnect layer.

Abstract: Method for formation of at least one electrical conductor on a semiconductor material (1), characterized in that it comprises the following steps: (E1)—deposition by serigraphy of a first high-temperature paste; (E2)—deposition by serigraphy of a second low-temperature paste at least partially superposed onto the first high-temperature paste deposited during the preceding step.

Abstract: A semiconductor apparatus includes: a first sheet-like member having a light receiving surface of an imaging device and a first connection terminal disposed thereon, the imaging device generating an image by receiving incident light from a light collecting section for collecting external light disposed thereon; a second sheet-like member having a second connection terminal to be connected to the first connection terminal provided thereon; a conductive bonding portion made of a conductive material and bonded with the first connection terminal; and a bonding wire connecting the conductive bonding portion and the second connection terminal, wherein the bonding wire is disposed along the plane of the first sheet-like member such that reflected light from the bonding wire does not impinge on the light receiving surface.

Abstract: A device that includes a signal generating unit having a surface that can receive photons, a first metal structure located on the surface of the signal generating unit, and a second metal structure located on the surface of the signal generating unit. The second metal structure being spaced apart from the first metal structure.