Light Responsive Pn Junction Patents (Class 257/461)
  • Patent number: 11863890
    Abstract: A pixel circuit comprising: a light-sensing element; a first transistor having its control node coupled to a sense node and its source coupled to a readout path of the pixel circuit; and a reset voltage correction circuit comprising: a first switch configured to selectively couple an input node of the reset voltage correction circuit to a correction node, the input node being connected to the sense node or to the source of the first transistor, the correction node being coupled by a capacitance to the sense node; and a second switch configured to selectively couple the correction node to a reset voltage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: January 2, 2024
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventor: Gaelle Palmigiani
  • Patent number: 11742449
    Abstract: The present invention provides a single photon avalanche diode device. The device has a logic substrate comprising an upper surface. The device has a sensor substrate bonded to an upper surface of the logic substrate. In an example, the sensor substrate comprises a plurality of pixel elements spatially disposed to form an array structure. In an example, each of the pixel elements has a passivation material, an epitaxially grown silicon material, an implanted p-type material configured in a first portion of the epitaxially grown material, an implanted n-type material configured in a second portion of the epitaxially grown material, and a junction region configured from the implanted p-type material and the implanted n-type material.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: August 29, 2023
    Assignee: Adaps Photonics Inc.
    Inventors: Ching-Ying Lu, Yangsen Kang, Shuang Li, Kai Zang
  • Patent number: 11508867
    Abstract: The present invention provides a single photon avalanche diode device. The device has a logic substrate comprising an upper surface. The device has a sensor substrate bonded to an upper surface of the logic substrate. In an example, the sensor substrate comprises a plurality of pixel elements spatially disposed to form an array structure. In an example, each of the pixel elements has a passivation material, an epitaxially grown silicon material, an implanted p-type material configured in a first portion of the epitaxially grown material, an implanted n-type material configured in a second portion of the epitaxially grown material, and a junction region configured from the implanted p-type material and the implanted n-type material.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 22, 2022
    Assignee: ADAPS PHOTONICS INC.
    Inventors: Ching-Ying Lu, Yangsen Kang, Shuang Li, Kai Zang
  • Patent number: 11430233
    Abstract: The disclosure features methods and systems that include illuminating a candidate structure with radiation linearly polarized along a first polarization direction and obtaining a first image of the dendritic structure, illuminating the candidate structure with radiation linearly polarized along a second polarization direction and obtaining a second image of the dendritic structure, where an angle between the first and second polarization directions is at least 10, for a set of pixels corresponding to a first region of the candidate structure in the first and second images, determining a first change in average pixel intensity between the first and second images, and authenticating the candidate structure as a dendritic structure based on the first change in average pixel intensity.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 30, 2022
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventor: Michael N. Kozicki
  • Patent number: 11277040
    Abstract: An assembly for optical to electrical power conversion including a photodiode assembly having a substrate layer and an internal side, an antireflective layer, a heterojunction buffer layer adjacent the internal side; an active area positioned adjacent the heterojunction buffer layer, a plurality of n+ electrode regions and p+ electrode regions positioned adjacent the active area, and back-contacts configured to align with the n+ and p+ electrode regions. The active area converts photons from incoming light into liberated electron hole pairs. The heterojunction buffer layer prevents electrons and holes of the liberated electron hole pairs from moving toward the substrate layer. The plurality of electrode regions are configured in an alternating pattern with gaps between each n+ and p+ electrode region.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 15, 2022
    Assignee: PHION TECHNOLOGIES CORP.
    Inventors: Alan Wang, Jonathan Nydell, Steve Laver
  • Patent number: 11271133
    Abstract: A multi-junction optoelectronic device and method of manufacture are disclosed. The method comprises providing a first p-n structure on a substrate, wherein the first p-n structure comprises a first base layer of a first semiconductor with a first bandgap such that a lattice constant of the first semiconductor matches a lattice constant of the substrate, and wherein the first semiconductor comprises a Group III-V semiconductor. The method includes providing a second p-n structure, wherein the second p-n structure comprises a second base layer of a second semiconductor with a second bandgap, wherein a lattice constant of the second semiconductor matches a lattice constant of the first semiconductor, and wherein the second semiconductor comprises a Group IV semiconductor. The method also includes lifting off the substrate the multi-junction optoelectronic device having the first p-n structure and the second p-n structure, wherein the multi-junction optoelectronic device is a flexible device.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 8, 2022
    Assignee: UTICA LEASECO, LLC
    Inventors: Brendan M. Kayes, Gang He
  • Patent number: 11114494
    Abstract: Disclosed herein is an apparatus comprising: an array of avalanche photodiodes (APDs), each of the APDs comprising an absorption region and an amplification region; wherein the absorption region is configured to generate charge carriers from a photon absorbed by the absorption region; wherein the absorption region comprises a silicon epitaxial layer; wherein the amplification region comprises a junction with an electric field in the junction; wherein the electric field is at a value sufficient to cause an avalanche of charge carriers entering the amplification region, but not sufficient to make the avalanche self-sustaining; wherein the junctions of the APDs are discrete.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 7, 2021
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 11094734
    Abstract: An imaging device including a semiconductor substrate having a first surface, the semiconductor substrate including: a first layer containing an impurity of a first conductivity type; a second layer containing an impurity of a second conductivity type different from the first conductivity type, the second layer being closer to the first surface than the first layer is; and a pixel. The pixel includes a photoelectric converter configured to convert light into charge; and a first diffusion region containing an impurity of the first conductivity type, the first diffusion region facing the first layer via the second layer, configured to store at least a part of the charge. The first layer having a second surface adjacent to the second layer, the second surface including a convex portion toward the first surface, and the convex portion facing the first diffusion region.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 17, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junji Hirase, Yoshinori Takami, Shota Yamada, Yoshihiro Sato, Yoshiaki Satou
  • Patent number: 11092677
    Abstract: An object of the present invention is to provide a time measurement device that facilitates a circuit layout. A time measurement device (20) of the present invention includes: a plurality of pixels (30) provided side by side in a first direction, and each including a single-photon avalanche diode (SPAD) disposed on a first semiconductor substrate, and each generating a first logic signal (S35) depending on detection timing in the single-photon avalanche diode (SPAD); and a time measurement section (24) that is disposed on a second semiconductor substrate attached to the first semiconductor substrate and measures the detection timing in each of the plurality of pixels (30).
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 17, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Koichi Hasegawa
  • Patent number: 11024754
    Abstract: A photovoltaic device that includes a p-n junction of first type III-V semiconductor material layers, and a window layer of a second type III-V semiconductor material on the light receiving end of the p-n junction, wherein the second type III-V semiconductor material has a greater band gap than the first type III-V semiconductor material, and the window layer of the photovoltaic device has a cross-sectional area of microscale.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10943933
    Abstract: An imaging device having a first surface on which light is incident and a second surface on an opposite side of the first surface, includes a photoelectric conversion section including semiconductors having a same conductivity type, in which an impurity concentration on the second surface side is higher than an impurity concentration on the first surface side.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 9, 2021
    Assignee: NIKON CORPORATION
    Inventor: Hironobu Murata
  • Patent number: 10879290
    Abstract: Some embodiments relate to a device array including a plurality of devices arranged in a semiconductor substrate. A protection ring circumscribes an outer perimeter of the device array. The protection ring includes a first ring neighboring the device array, a second ring circumscribing the first ring and meeting the first ring at a first p-n junction, and a third ring circumscribing the second ring and meeting the second ring at a second p-n junction. The first ring has a first width, the second ring has a second width, and the third ring has a third width. At least two of the first width, the second width, and the third width are different from one another.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng
  • Patent number: 10847509
    Abstract: A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m1, with m1?0.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m12. The first partial junction grading coefficient m11 is different to the second partial junction grading coefficient m12, with m11?m12. At least one of the first and second partial junction grading coefficients m11, m12 is greater than 0.50, with m11 and/or m12>0.50. The first junction grading coefficient m1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m11, m12.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: November 24, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Joost Adriaan Willemen
  • Patent number: 10734432
    Abstract: An imaging device includes a semiconductor substrate having a surface, the semiconductor substrate including: a first layer of a first conductivity type; a second layer of a second conductivity type, the second layer being closer to the surface; and a pixel including: a photoelectric converter configured to convert light into charge; a first diffusion region of the first conductivity type, the first diffusion region facing the first layer via the second layer, configured to store at least a part of the charge; and a second diffusion region being a diffusion region closest to the first diffusion region among diffusion regions of the first conductivity type, the diffusion regions facing the first layer via the second layer. A distance between the second diffusion region and the first layer is equal to or less than 1.5 times a distance between the second diffusion region and the first diffusion region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 4, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junji Hirase, Yoshinori Takami, Shota Yamada, Yoshihiro Sato, Yoshiaki Satou
  • Patent number: 10638581
    Abstract: A light-emitting/receiving device including: a diode-type light-emitting element formed on a semiconductor substrate; a diode-type light-receiving element formed on the semiconductor substrate; a light source driving unit configured to supply a first common voltage to an anode or a cathode of the light-emitting element to drive the light-emitting element; and a light signal processing unit configured to perform current/voltage conversion on an output current outputted from the light-receiving element, by referring to a second common voltage.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 28, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Yuta Takagi, Yuji Goda
  • Patent number: 10636925
    Abstract: A method for making photocapacitor is provided. The method includes: preparing a perovskite solar cell, preparing a first supercapacitor electrode, deposing the first supercapacitor electrode onto the perovskite solar cell, dissolving a portion of a cell packaging structure and a first material, and preparing a second supercapacitor electrode opposite to the first supercapacitor electrode.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 28, 2020
    Assignees: Tinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ru-Hao Liu, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 10580548
    Abstract: A carbon nanotube composite material (1) includes a metal base material (10) and carbon nanotube electrically-conductive path portions (20). The metal base material (10) is made from a polycrystalline substance in which a plurality of rod-shaped metal crystal grains (11) are oriented in a direction. The carbon nanotube electrically-conductive path portions (20) are made from doped carbon nanotubes having a dopant, existing in parts of grain boundaries (15) between the rod-shaped metal crystal grains (11) in a cross section of the metal base material (10), and forming an electrically-conductive path which is electrically conductive in a longitudinal direction of the metal base material (10), by existing along the longitudinal direction (L).
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 3, 2020
    Assignees: YAZAKI CORPORATION, The University of Tokyo
    Inventors: Ken Nishiura, Junichiro Tokutomi, Hideo Gonda, Jun Yanagimoto
  • Patent number: 10559610
    Abstract: A method of manufacturing an imaging device, including a first buried diode including a first semiconductor region and a second semiconductor region and a second buried diode including a third semiconductor region and a fourth semiconductor region, includes implanting first impurity ions of a first conductivity type into a first region and a third region between the first region and a second region, and implanting second impurity ions of the first conductivity type into the second region and the third region, wherein the first semiconductor region is formed by implanting the first impurity ions, the third semiconductor region is formed by implanting the second impurity ions, and a fifth semiconductor region having a higher impurity concentration than the first and the second semiconductor regions is formed in the third region by implanting the first and second impurity ions.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: February 11, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoichiro Handa, Ginjiro Toyoguchi, Junji Iwata, Yoichi Wada, Hideyuki Ito, Hiromasa Tsuboi, Daichi Seto
  • Patent number: 10522717
    Abstract: A light-emitting device is disclosed. The light emitting device includes an electron blocking layer, a hole blocking layer, wherein at least a portion of the hole blocking layer is arranged to have a compressive strain, and an active layer disposed between the hole blocking layer and the electron blocking layer. The active layer may include a first barrier layer arranged to have a tensile strain, a second barrier layer arranged to have a tensile strain, and a first well layer disposed between the first barrier layer and the second barrier layer. The active layer may also include a first unstrained barrier layer, a second unstrained barrier layer, and a second well layer disposed between the first unstrained barrier layer and the second unstrained barrier layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 31, 2019
    Assignee: Lumileds LLC
    Inventors: Lekhnath Bhusal, Theodore Chung, Parijat Deb
  • Patent number: 10403662
    Abstract: The present disclosure relates to a solid-state imaging element and an electronic apparatus capable of suppressing color mixing and sensitivity reduction in each of pixels of a solid-state imaging element having a vertical spectral structure. A solid-state imaging element according to a first aspect of the present disclosure is a solid-state imaging element including a vertical spectral structure pixel containing a plurality of photoelectric conversion units stacked in layers.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: September 3, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Atsushi Toda
  • Patent number: 10359544
    Abstract: A long-wave infrared anti-reflective laminate includes a silicon substrate and an anti-reflective composite layer. The anti-reflective composite layer is disposed on the silicon substrate and has at least one first anti-reflective membrane. The at least one first anti-reflective membrane includes a first silicon nitride layer and a first silicon dioxide layer. The first silicon nitride layer is disposed between the silicon substrate and the first silicon dioxide layer. The thickness ratio of the first silicon nitride layer to the first silicon dioxide layer ranges from 175 to 225. The anti-reflective composite layer can be applied on the optical instrument to raise the transmitting rate of the silicon substrate. The transmitting rate of the long-wave infrared anti-reflective laminate is over 90% within the wave band from 8 ?m to 12 ?m.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: July 23, 2019
    Inventor: Tzu-Chiang Chen
  • Patent number: 10340415
    Abstract: A semiconductor device includes a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer provided between the first conductive semiconductor layer and the second conductive semiconductor layer, and a semiconductor device package including the semiconductor device. The active layer includes a plurality of barrier layers and a plurality of well layers. The second conductive semiconductor layer includes a conductive second semiconductor layer and a conductive first semiconductor layer provided on the conductive second semiconductor layer. The conductive second semiconductor layer has a higher aluminum composition than the well layers, and the conductive first semiconductor layer has a lower aluminum composition than the well layers.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hyun Jee Oh, Rak Jun Choi, Byeoung Jo Kim
  • Patent number: 10323980
    Abstract: A sensor system, device and method for generating a wireless signal in response to a sensed illumination. A sensor is disclosed having: a photosensitive element; a device that converts a sensed illumination detected by the photosensitive element into a corresponding impedance response; and a wireless signal generator that generates a wireless output based on a characteristic of the corresponding impedance response, wherein the wireless output correlates to the sensed illumination.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: June 18, 2019
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Tanuj Saxena, Partha Sarathi Dutta, Serguei Lvovich Roumiantsev, Michael Shur
  • Patent number: 10276617
    Abstract: Some embodiments relate to a pixel sensor array including a plurality of photosensors arranged in a semiconductor substrate. A protection ring circumscribes an outer perimeter of the pixel sensor array. The protection ring includes a first ring neighboring the pixel sensor array, a second ring circumscribing the first ring and meeting the first ring at a first p-n junction, and a third ring circumscribing the second ring and meeting the second ring at a second p-n junction. The first ring has a first width, the second ring has a second width, and the third ring has a third width. At least two of the first width, the second width, and the third width are different from one another.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng
  • Patent number: 10276609
    Abstract: A semiconductor device is provided. The device generates a signal based on both a first carrier generated in a first photodiode and a second carrier generated in a second photodiode. The first photodiode includes a first region of a second conductivity type and a second region of a first conductivity type arranged between a surface of a substrate and the first region. The second photodiode includes a third region of the first conductivity type and a fourth region of the second conductivity type arranged between the surface and the third region. A fifth region of the first conductivity type is provided at a position farther apart from the surface than the first region. A peak of an impurity concentration of the third region is positioned in a range where the first region exists between the second region and the fifth region.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: April 30, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keisuke Ota, Hajime Ikeda, Tatsuhito Goden, Yoichi Wada, Toshinori Hasegawa
  • Patent number: 10263308
    Abstract: A solar flow battery comprising: a positive compartment containing at least one positive electrode in contact with a positive electrolyte containing a first redox active molecule; a negative compartment containing at least one negative electrode in contact with a negative electrolyte containing a second redox active molecule, wherein said first and second redox active molecules remain dissolved in solution when changed in oxidation state; at least one of said negative or positive electrodes comprises a semiconductor light absorber; electrical communication means between said electrodes and an external load for directing electrical energy into or out of said solar flow battery; a separator component that separates the positive and negative electrolytes while permitting the passage of non-redox-active species; and means for establishing flow of the positive and negative electrolyte solutions past respective electrodes.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: April 16, 2019
    Assignee: CORNELL UNIVERSITY
    Inventors: James R. McKone, Hector D. Abruna
  • Patent number: 10204957
    Abstract: An imaging device having a first surface on which light is incident and a second surface on an opposite side of the first surface, includes a photoelectric conversion section including semiconductors having a same conductivity type, in which an impurity concentration on the second surface side is higher than an impurity concentration on the first surface side.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: February 12, 2019
    Assignee: NIKON CORPORATION
    Inventor: Hironobu Murata
  • Patent number: 10203411
    Abstract: Aspects of the disclosure pertain to a system and method for reducing ambient light sensitivity of Infrared (IR) detectors. Optical filter(s) (e.g., absorption filter(s), interference filter(s)) placed over a sensor of the IR detector (e.g., gesture sensor) absorb or reflect visible light, while passing specific IR wavelengths, for promoting the reduced ambient light sensitivity of the IR detector.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: February 12, 2019
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Joy T. Jones, Nicole D. Kerness, Sunny K. Hsu, Anand Chamakura, Christopher F. Edwards, David Skurnik, Phillip J. Benzel, Nevzat A. Kestelli
  • Patent number: 10032810
    Abstract: An image system with a dual layer photodiode structure is provided for processing color images. In particular, the image system can include an image sensor that can include photodiodes with a dual layer photodiode structure. In some embodiments, the dual layer photodiode can include a first layer of photodiodes (e.g., a bottom layer), an insulation layer disposed on the first layer of photodiodes, and a second layer of photodiodes (e.g., a top layer) disposed on the insulation layer. The first layer of photodiodes can include one or more suitable pixels (e.g., green, blue, clear, luminance, and/or infrared pixels). Likewise, the second layer of photodiodes can include one or more suitable pixels (e.g., green, red, clear, luminance, and/or infrared pixels). An image sensor incorporating dual layer photodiodes can gain light sensitivity with additional clear pixels and maintain luminance information with green pixels.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: July 24, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yingjun Bai, Qun Sun
  • Patent number: 9960308
    Abstract: A number of micro-sized rectangular dot-like n-type semiconductor regions 121 are created in a p-type semiconductor region which is a base body 11. Contact parts 14, each of which is in contact with one n-type semiconductor region 121 and almost entirely covers the same region, are mutually connected by a wire part 15 as a common cathode terminal. The n-type semiconductor regions 121 receives no light; their function is to collect carriers generated within and outside the surrounding depletion layers. Appropriate setting of the spacing of the n-type semiconductor regions 121 enables efficient collection of the carriers generated in the p-type semiconductor region while improving the SN ratio of the photo-detection signal by a noise-reduction effect due to a decrease in the p-n junction capacitance. Carriers originating from light of shorter wavelengths are barely reflected in the photo-detection signal. Thus, unfavorable influences of the shorter wavelengths of light are eliminated.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 1, 2018
    Assignee: MICRO SIGNAL CO., LTD.
    Inventors: Kunihiro Watanabe, Masaya Okada, Kazunori Nohara
  • Patent number: 9726839
    Abstract: There is provided a bidirectional optical communication module including a bidirectional optical communication chip configured to include an optical circuit board in which a light receiving element constituting a receiving section, a transmitting element constituting a transmitting section, and a wavelength-division multiplexing (WDM) filter that divides transmission signal light and reception signal light from each other are hybrid-integrated, a reflecting section configured to direct a propagation direction of the transmission signal light output from the transmitting section and the reception signal light received by the receiving section to a direction orthogonal to the optical circuit board, and an optical coupling element configured to spatially optically-couple an input-output port for the transmission signal light and the reception signal light provided at the bidirectional optical communication chip to an input-output port of an optical fiber.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 8, 2017
    Assignees: Oki Electric Industry Co., Ltd., Photonics Electronics Technology Research Association
    Inventor: Daisuke Shimura
  • Patent number: 9721994
    Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, a photoelectric conversion layer, a termination layer, and an electrode layer. In the silicon substrate, first semiconductor regions and second semiconductor regions are alternately arranged along a first surface on a light incident side of the silicon substrate. The first semiconductor regions are doped with impurities of first concentration and have a conductivity of either one of p-type and n-type. The second semiconductor regions are doped with impurities of a second concentration lower than the first concentration and have a conductivity of the other type. The photoelectric conversion layer is disposed on a first surface side of the silicon substrate. The termination layer is disposed between the silicon substrate and the photoelectric conversion layer, in contact with the first surface, and to terminate dangling bonds of the silicon substrate. The electrode layer is provided on the light incident side.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: August 1, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Miyazaki, Hideyuki Funaki, Yoshinori Iida, Isao Takasu, Yuki Nobusa
  • Patent number: 9613916
    Abstract: Some embodiments of the present disclosure provide an image sensor. The image sensor includes a pixel sensor array including a plurality of photosensors arranged in a semiconductor substrate. Peripheral circuitry is arranged in or on the semiconductor substrate and is spaced apart from the pixel sensor array. A protection ring circumscribes an outer perimeter of the pixel sensor array and separates the pixel sensor array from the peripheral circuitry. The protection ring has an annular width of greater than 20 microns. The protection ring includes a first ring in the substrate neighboring the pixel sensor array, a second ring circumscribing the first ring and meeting the first ring at a first p-n junction, and a third ring circumscribing the second ring and meeting the second ring at a second p-n junction.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng
  • Patent number: 9583614
    Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 28, 2017
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 9570491
    Abstract: A dual-mode image sensor with a signal-separating CFA includes a substrate including a plurality of photodiode regions and a plurality of tall spectral filters having a uniform first height and for transmitting a first electromagnetic wavelength range. Each of the tall spectral filters is disposed on the substrate and aligned with a respective photodiode region. The image sensor also includes a plurality of short spectral filters for transmitting one or more spectral bands within a second electromagnetic wavelength range. Each of the short spectral filters is disposed on the substrate and aligned with a respective photodiode region. The image sensor also includes a plurality of single-layer blocking filters for blocking the first electromagnetic wavelength range. Each single-layer blocking filter is disposed on a respective short spectral filter. Each single-layer blocking filter and its respective short spectral filter have a combined height substantially equal to the first height.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: February 14, 2017
    Assignee: OmniVision Technologies, Inc.
    Inventors: Jin Li, Qian Yin, Dyson Hsinchih Tai
  • Patent number: 9530913
    Abstract: Provided is a solar cell having improved photoelectric conversion efficiency. The solar cell (1) contains: a substrate (10) comprising a semiconductor material having one type of conductivity; a first semiconductor layer (12n) having the one type of conductivity; and a second semiconductor layer (17n) having the one type of conductivity. The first semiconductor layer (12n) is arranged on one main surface of the substrate (10). The second semiconductor layer (17n) is arranged on the other main surface of the substrate (10). The solar cell (1) is configured such that the strength of the electric field formed by the second semiconductor layer (17n) is greater than the strength of the electric field formed by the first semiconductor layer (12n).
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: December 27, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Isao Hasegawa, Toshio Asaumi, Hitoshi Sakata
  • Patent number: 9502265
    Abstract: An embodiment method includes forming a nanowire extending upwards from a substrate, wherein the nanowire includes: a bottom semiconductor region; a middle semiconductor region over the bottom semiconductor region; and a top semiconductor region over the middle semiconductor region. The method also includes forming a dielectric layer around and extending over the nanowire and forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process. After forming the CMP-stop layer, the dielectric layer is planarized.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hong Jiang, Li-Ting Wang, Teng-Chun Tsai, Shih-Chiang Chen
  • Patent number: 9412894
    Abstract: A photovoltaic device includes a semiconductor substrate; an amorphous first conductive semiconductor layer on a first region of a first surface of the semiconductor substrate and containing a first impurity; an amorphous second conductive semiconductor layer on a second region of the first surface of the semiconductor substrate and containing a second impurity; and a gap passivation layer located between the first region and the second region on the semiconductor substrate, wherein the first conductive semiconductor layer is also on the gap passivation layer.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: August 9, 2016
    Assignee: INTELLECTUAL KEYSTONE TECHNOLOGY LLC
    Inventors: Nam-Kyu Song, Min-Seok Oh, Yun-Seok Lee, Cho-Young Lee
  • Patent number: 9177994
    Abstract: An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: November 3, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 9178100
    Abstract: A single photon avalanche diode for use in a CMOS integrated circuit includes a deep n-well region formed above a p-type substrate and an n-well region formed above and in contact with the deep n-well region. A cathode contact is connected to the n-well region via a heavily doped n-type implant. A lightly doped region forms a guard ring around the n-well and deep n-well regions. A p-well region is adjacent to the lightly doped region. An anode contact is connected to the p-well region via a heavily doped p-type implant. The junction between the bottom of the deep n-well region and the substrate forms a multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage is controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the multiplication region.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 3, 2015
    Assignees: STMicroelectronics (Research & Development) Limited, The University Court of the University of Edinburgh
    Inventors: Eric Alexander Garner Webster, Robert Kerr Henderson
  • Patent number: 9153755
    Abstract: A silicone resin sheet is formed from a resin composition containing a thermosetting silicone resin and microparticles. The complex viscosity thereof at a frequency of 10 Hz is 80 to 1000 Pa·s and the tan ? thereof at a frequency of 10 Hz is 0.3 to 1.6 obtained by a dynamic viscoelastic measurement at a frequency of 0.1 to 50 Hz at 30° C.; a rate of frequency increase of 10 Hz/min; and a distortion of 1% in a shear mode.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 6, 2015
    Assignee: NITTO DENKO CORPORATION
    Inventors: Ryuichi Kimura, Hiroyuki Katayama
  • Patent number: 9147776
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the first polarity charge layer.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 29, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Patent number: 9147777
    Abstract: The present invention is directed to a position sensing detector made of a photodiode having a semi insulating substrate layer; a buffered layer that is formed directly atop the semi-insulating substrate layer, an absorption layer that is formed directly atop the buffered layer substrate layer, a cap layer that is formed directly atop the absorption layer, a plurality of cathode electrodes electrically coupled to the buffered layer or directly to the cap layer, and at least one anode electrode electrically coupled to a p-type region in the cap layer. The position sensing detector has a photo-response non-uniformity of less than 2% and a position detection error of less than 10 ?m across the active area.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: September 29, 2015
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 9105789
    Abstract: An embodiment of a geiger-mode avalanche photodiode includes: a body of semiconductor material, having a first surface and a second surface; a cathode region of a first type of conductivity, which extends within the body; and an anode region of a second type of conductivity, which extends within the cathode region and faces the first surface, the anode and cathode regions defining a junction. The anode region includes at least two subregions, which extend at a distance apart within the cathode region starting from the first surface, and delimit at least one gap housing a portion of the cathode region, the maximum width of the gap and the levels of doping of the two subregions and of the cathode region being such that, by biasing the junction at a breakdown voltage, a first depleted region occupies completely the portion of the cathode region within the gap.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: August 11, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Delfo Nunziato Sanfilippo
  • Patent number: 9105767
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. The first polarity charge layer is disposed between a first one of a plurality of passivation layers and a second one of the plurality of passivation layers disposed over the photodiode region.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: August 11, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Patent number: 9093624
    Abstract: A silicone resin sheet is formed from a resin composition containing a thermosetting silicone resin and microparticles. The complex viscosity thereof at a frequency of 10 Hz is 80 to 1000 Pa·s and the tan ? thereof at a frequency of 10 Hz is 0.3 to 1.6 obtained by a dynamic viscoelastic measurement at a frequency of 0.1 to 50 Hz at 30° C.; a rate of frequency increase of 10 Hz/min; and a distortion of 1% in a shear mode.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: July 28, 2015
    Assignee: NITTO DENKO CORPORATION
    Inventors: Ryuichi Kimura, Hiroyuki Katayama
  • Patent number: 9064987
    Abstract: An ultraviolet sensor having a p-type semiconductor layer containing, as its main constituent, a solid solution of NiO and ZnO, and an n-type semiconductor layer containing ZnO as its main constituent, which is joined to the p-type semiconductor layer such that a portion of the p-type semiconductor layer is exposed. An internal electrode is buried in the p-type semiconductor layer and opposed to the n-type semiconductor layer. Both ends of the internal electrode are exposed at both end surfaces of the p-type semiconductor layer, and first and second high-resistance layers composed of insulating materials cover one end of the internal electrode. The second high-resistance layer is obtained by diffusion of the insulating material from the first high-resistance layer into the p-type semiconductor layer. A first external electrode is connected to the other end of the internal electrode, and a second external electrode is connected to the n-type semiconductor layer.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: June 23, 2015
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kazutaka Nakamura
  • Patent number: 9029908
    Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9013023
    Abstract: A photoelectric element includes a first electrode; and a second electrode positioned so as to face the first electrode; and a semiconductor disposed on a face of the first electrode, the face being positioned so as to face the second electrode; and a photosensitizer carried on the semiconductor; and a first charge-transport layer interposed between the first electrode and the second electrode; and a second charge-transport layer interposed between the first charge-transport layer and the second electrode. The first charge-transport layer and the second charge-transport layer contain different oxidation-reduction materials. The oxidation-reduction material in the first charge-transport layer has an oxidation-reduction potential higher than an oxidation-reduction potential of the oxidation-reduction material in the second charge-transport layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 21, 2015
    Assignees: Panasonic Corporation, Waseda University
    Inventors: Michio Suzuka, Takashi Sekiguchi, Naoki Hayashi, Hiroyuki Nishide, Kenichi Oyaizu, Fumiaki Kato
  • Patent number: 9000541
    Abstract: A photoelectric conversion device includes circuit portions disposed on a substrate, a first electrode electrically connected to one of the circuit portions, an optically transparent second electrode opposing the first electrode, and a photoelectric conversion portion disposed between the first electrode and the second electrode. The photoelectric conversion portion has a multilayer structure including a light absorption layer made of a p-type compound semiconductor film having a chalcopyrite structure, an amorphous oxide semiconductor layer, and a window layer made of an n-type semiconductor film.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: April 7, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Yasunori Hattori, Tomotaka Matsumoto, Tsukasa Eguchi