External Physical Configuration Of Semiconductor (e.g., Mesas, Grooves) Patents (Class 257/466)
  • Publication number: 20090160033
    Abstract: A light receiving element 1 has a semiconductor substrate 101; a first mesa 11 provided over the semiconductor substrate 101, and having an active region and a first electrode (p-side electrode 111) provided over the active region; a second mesa 12 provided over the semiconductor substrate 101, and having a semiconductor layer and a second electrode (n-side electrode 121) provided over the semiconductor layer; and a third mesa 13 provided over the semiconductor substrate 101, and having a semiconductor layer, wherein the third mesa 13 is arranged so as to surround the first mesa 11.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 25, 2009
    Applicant: NEC Corporation
    Inventors: Sawaki Watanabe, Kazuhiro Shiba, Takeshi Nakata
  • Publication number: 20090152664
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Application
    Filed: April 18, 2008
    Publication date: June 18, 2009
    Inventors: Ethan Jacob Dukenfield Klem, Dean Delehanty MacNeil, Gerasimos Konstantatos, Jiang Tang, Michael Charles Brading, Hui Tian, Edward Hartley Sargent
  • Patent number: 7535019
    Abstract: An optoelectronic fiber and methods for forming such a fiber are disclosed. The fiber generally includes an electrically conductive fiber core, a first semiconducting layer substantially surrounding the fiber core, and a second semiconducting layer substantially surrounding the first semiconducting layer. The first and second semiconducting layers are of complementary types, i.e., one is p-type and the other is n-type. The fiber may be made, e.g., by electrospinning a material to form a fiber core; substantially surrounding the fiber with a first semiconducting material; and substantially surrounding the first semiconducting material with a second semiconducting material. Optoelectronic fibers can be fashioned into a web to provide a solar cell material or substantially transparent conductive material.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: May 19, 2009
    Assignee: Nanosolar, Inc.
    Inventors: Brian M. Sager, Martin R. Roscheisen
  • Patent number: 7528420
    Abstract: Image sensing devices and methods for fabricating the same are provided. An exemplary image sensing device includes a first substrate having a first side and a second side opposing each other. A plurality of image sensing elements is formed in the first substrate at the first side. A conductive via is formed through the first substrate, having a first surface exposed by the first substrate at the first side and a second surface exposed by the first substrate at the second side. A conductive pad overlies the conductive via at the first side and is electrically connecting the image sensing elements. A conductive layer overlies the conductive via at the second side and electrically connects with the conductive pad. A conductive bump is formed over a portion of the conductive layer. A second substrate is bonded with the first substrate at the first side.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: May 5, 2009
    Assignee: Visera Technologies Company Limited
    Inventors: Jui-Peng Weng, Tzu-Han Lin, Pai-Chun Peter Zung
  • Patent number: 7528458
    Abstract: A photodiode having an increased proportion of light-sensitive area to light-insensitive area includes a semiconductor having a backside surface and a light-sensitive frontside surface. The semiconductor includes a first active layer having a first conductivity, a second active layer having a second conductivity opposite the first conductivity, and an intrinsic layer separating the first and second active layers. A plurality of isolation trenches are arranged to divide the photodiode into a plurality of cells. Each cell has a total frontside area including a cell active frontside area sensitive to light and a cell inactive frontside area not sensitive to light. The cell active frontside area forms at least 95 percent of the cell total frontside area. A method of forming the photodiode is also disclosed.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: May 5, 2009
    Assignee: Icemos Technology Ltd.
    Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
  • Patent number: 7521769
    Abstract: The invention provides sensor compositions and method of making sensors.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: April 21, 2009
    Assignee: SRU Biosystems, Inc.
    Inventor: Brian T. Cunningham
  • Patent number: 7521737
    Abstract: A method of fabricating light-sensing devices including photodiodes monolithically integrated with CMOS devices. Several types of photodiode devices (PIN, HIP) are expitaxially grown in one single step on active areas implanted in a common semiconductor substrate, the active areas having defined polarities. The expitaxially grown layers for the photodiode devices may be either undoped or in-situ doped with profiles suitable for their respective operation. With appropriate choice of substrate materials, device layers and heterojunction engineering and process architecture, it is possible to fabricate silicon-based and germanium-based multi-spectral sensors that can deliver pixel density and cost of fabrication comparable to the state of the art CCDs and CMOS image sensors. The method can be implemented with epitaxially deposited films on the following substrates: Silicon Bulk, Thick-Film and Thin-Film Silicon-On-Insulator (SOI), Germanium Bulk, Thick-Film and Thin-Film Geranium-On-Insulator (GeOI).
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: April 21, 2009
    Assignee: Quantum Semiconductor LLC
    Inventor: Carlos J. R. P. Augusto
  • Patent number: 7518143
    Abstract: A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio are provided. The solid-state imaging device comprises an integrated array of a plurality of pixels, each of which comprises a photodiode PD for receiving light and generating photoelectric charges, a transfer transistor Tr1 for transferring the photoelectric charges, and a storage capacitor element C connected to the photodiode PD at least through the transfer transistor Tr1 for accumulating, at least through the transfer transistor Tr1, the photoelectric charge overflowing from the photodiode PD during accumulating operation.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: April 14, 2009
    Assignee: National University Corporation Tohoku University
    Inventor: Shigetoshi Sugawa
  • Publication number: 20090057806
    Abstract: In one embodiment of the present invention, the segmented photodiode includes a p type substrate, a p type epitaxial layer formed on the p type substrate, an n type epitaxial layer formed on the p type epitaxial layer, and p type segmenting region provided in the n type epitaxial layer separately from the p type epitaxial layer and segmenting the photosensitive region, and is configured that a depleted layer (first depleted layer) created in an n type region right under the segmenting section located between the p type segmenting region and the p type epitaxial layer by applying a reverse bias voltage is configured to reach a depleted layer (second depleted layer) formed in a junction surface between the n type epitaxial layer and the p type epitaxial layer so that the photosensitive region is electrically isolated.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 5, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masaki MATSUDA
  • Patent number: 7491925
    Abstract: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evaluation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically integrated transimpedance amplifier and monolithically integrated evaluation electronics. An actual photocell component (20) is assigned to the chip face onto which the light preferably falls. Electronic circuit components (30) are arranged on the opposite chip face. Electrical connections (40) between the photocell and the electronic circuit are provided with an extension in the direction running perpendicular to the chip normal.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 17, 2009
    Assignees: X-FAB Semiconductor Foundries, AG, Melexis GmbH
    Inventors: Konrad Bach, Alexander Hoelke, Uwe Eckoldt, Wolfgang Einbrodt, Karl-Ulrich Stahl
  • Publication number: 20090027038
    Abstract: Systems, methods and sensors detect changes in incident optical radiation. Current is driven through one or more active areas of a detector while the incident optical radiation illuminates the active areas. Voltage is sensed across one or more of the active areas, a change in the voltage being indicative of the changes in incident optical radiation.
    Type: Application
    Filed: June 30, 2008
    Publication date: January 29, 2009
    Inventors: Elsa Garmire, Ashifi Gogo, Jonathan T. Bessette
  • Patent number: 7482667
    Abstract: An edge viewing semiconductor photodetector may be provided. Light may be transmitted through an optical fiber conduit comprising a core region surrounded by a cladding region. The light may be received at the edge viewing semiconductor photodetector having an active area. The active area may be substantially contained within a first plane. The edge viewing semiconductor photodetector may further have conducting contact pads connected to the active area. The contact pads may be substantially contained within plural planes. The first plane may have its normal direction substantially inclined with respect to a normal direction of the plural planes. The first plane may further have its normal direction substantially inclined with respect to a direction of the received light incident to the active area. Next, a signal may be received from the pads. The signal may correspond to the transmitted light.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: January 27, 2009
    Assignee: Georgia Tech Research Corporation
    Inventors: Daniel Guidotti, Gee-Kung Chang, Jae-Hyun Ryou, Russell Dean Dupuis
  • Patent number: 7473970
    Abstract: An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Jeffrey S. Brown, David M. Fried, Robert J. Gauthier, Jr., Edward J. Nowak, Jed H. Rankin, William R. Tonti
  • Patent number: 7468503
    Abstract: A PIN photodetector includes a first semiconductor contact layer, a semiconductor absorption layer having a larger area than the first semiconductor contact layer, a semiconductor passivation layer positioned between the first semiconductor contact layer and absorption layer, and a second semiconductor contact layer. The semiconductor absorption layer and passivation layers are positioned between the first and second semiconductor contact layers.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: December 23, 2008
    Assignee: Picometrix, LLC
    Inventors: Cheng C. Ko, Barry Levine
  • Patent number: 7456452
    Abstract: Light sensors in an imager having sloped features including, but not limited to, hemispherical, v-shaped, or other sloped shapes. Light sensors having such a sloped feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for absorption there.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 25, 2008
    Assignee: Micron Technology, Inc.
    Inventors: David Wells, Shane P. Leiphart
  • Patent number: 7445949
    Abstract: A method of manufacturing a semiconductor laser device is provided. First, a first mask layer is formed on an epitaxial structure to define a protrudent area in a ridge structure. Thereafter, a conformal second mask layer is formed over the epitaxial structure to cover the first mask layer. A third mask layer is formed over the second mask layer. The exposed second mask layer is removed. Using the first and the third mask layers as etching masks, a portion of the epitaxial structure is removed. The third mask layer and the remaining second mask layer are removed to form the ridge structure. An insulation layer is formed on the epitaxial structure and then the first mask layer is removed to expose the top surface of the protrudent area. A conductive layer is formed on the epitaxial structure such that it contacts with the top surface of the protrudent area.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: November 4, 2008
    Assignee: National Central University
    Inventors: Hung-Cheng Lin, Jen-Inn Chyi, Guan-Ting Chen
  • Patent number: 7439599
    Abstract: A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: October 21, 2008
    Assignee: Emcore Corporation
    Inventors: Xiang Gao, Alex Ceruzzi, Steve Schwed, Linlin Liu, Mark Gottfried
  • Patent number: 7436030
    Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventors: Haining Yang, Thomas W. Dyer, Wai-Kin Li
  • Patent number: 7427530
    Abstract: Methods of manufacturing a photo diode include sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a substrate. The second and first epitaxial layers are etched to form a trench that exposes a portion of the buried layer. A conductive plug of the first conductivity type is formed in the trench. A first electrode is formed on an upper surface of the second epitaxial layer. A second electrode may be formed to contact an upper surface of the conductive plug. Photodiodes having a conductive plug contact to a buried layer are also provided.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: September 23, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ryoul Bae, Dong-kyun Nam
  • Patent number: 7425751
    Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: September 16, 2008
    Assignee: Agency for Science, Technology and Research
    Inventors: Narayanan Balasubramanian, Richard Hammond
  • Patent number: 7425745
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation film that is provided in one principal surface of the semiconductor substrate, wiring that is arranged on the isolation film, a diffusion layer that is formed inside the semiconductor substrate and located in the vicinity of the isolation film, and an insulating film that covers the diffusion layer over the one principal surface of the semiconductor substrate. The insulating film further covers a portion of the isolation film near to the diffusion layer and comes into contact with the side of the wiring near to the diffusion layer.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: September 16, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Sougo Ohta
  • Patent number: 7408210
    Abstract: An object of the present invention is to simultaneously realize the enlargement of a dynamic range and the downsizing of a pixel. An additional capacitor CS is composed by using: a first capacitor formed of a first diffusion layer, a second diffusion layer and a P well by layering the P well, the first diffusion layer, a first dielectric film, a first polysilicon layer, a second dielectric film and a second polysilicon layer; a second capacitor formed of the second diffusion layer, the first polysilicon layer and the first dielectric film; and a third capacitor formed of the first polysilicon layers, a second polysilicon layer, and a second dielectric film. Thereby, the additional capacitor CS for accumulating carriers overflown from a photodiode PD can secure a required capacitance value while making its size as small as possible.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: August 5, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masanori Ogura, Toru Koizumi, Akira Okita, Tetsuya Itano, Shin Kikuchi
  • Patent number: 7397066
    Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: July 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Steven D. Oliver
  • Patent number: 7388270
    Abstract: A method of fabricating a CMOS image sensor is provided, in which a trapezoidal microlens pattern profile is formed to facilitate reflowing the microlens pattern and by which a curvature of the microlens may be enhanced to raise its light-condensing efficiency. The method includes forming a plurality of photodiodes on a semiconductor substrate; forming an insulating interlayer on the semiconductor substrate including the photodiodes; forming a protective layer on the insulating interlayer; forming a plurality of color filters corresponding to the photodiodes; forming a top coating layer on the color filters; forming a microlens pattern on the top coating layer; and forming a plurality of microlenses by reflowing the microlens pattern.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: June 17, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Yong Suk Lee
  • Patent number: 7372123
    Abstract: A semiconductor light-receiving module includes a semiconductor light-receiving element and an incident light direction device. The semiconductor light-receiving element includes a substrate, at least a light absorbing layer and an upper cladding layer formed sequentially on the substrate, a light incident facet formed at least at one facet of the substrate and the light absorbing layer, and electrodes which output an electric signal generated by absorption of the light entering from the light incident facet in the light absorbing layer. The incident light direction device directs to irradiate the light obliquely to the light incident facet of the semiconductor light-receiving element, and to cause at least part of the light to irradiate the light absorbing layer at the light incident facet.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: May 13, 2008
    Assignee: Anritsu Corporation
    Inventors: Kenji Kawano, Hiroaki Yoshidaya, Jun Hiraoka, Eiji Kawazura, Satoshi Matsumoto
  • Patent number: 7317236
    Abstract: A semiconductor light-receiving module includes a semiconductor light-receiving element and an incident light direction device. The semiconductor light-receiving element includes a substrate, at least a light absorbing layer and an upper cladding layer formed sequentially on the substrate, a light incident facet formed at least at one facet of the substrate and the light absorbing layer, and electrodes which output an electric signal generated by absorption of the light entering from the light incident facet in the light absorbing layer. The incident light direction device directs to irradiate the light obliquely to the light incident facet of the semiconductor light-receiving element, and to cause at least part of the light to irradiate the light absorbing layer at the light incident facet.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: January 8, 2008
    Assignee: Anritsu Corporation
    Inventors: Kenji Kawano, Hiroaki Yoshidaya, Jun Hiraoka, Yuichi Sasaki
  • Patent number: 7314832
    Abstract: A method of forming a film on a substrate. In accordance with the invention, an adhesion layer is formed on the substrate. The adhesion layer is chemically bonded to the substrate and has a textured surface. The film is then formed on the textured surface of the adhesion layer.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: January 1, 2008
    Assignee: Pan Jit Americas, Inc.
    Inventors: Michael Kountz, Randy Olsen, Michael Adamson
  • Patent number: 7307210
    Abstract: In a solar cell, at least one of reinforcing material and buffering material is provided at least partially on at least one of a back surface, a front surface and a side surface of the solar cell. With these reinforcing material and/or buffering material, occurrence of cell fracture due to load imposed by external force can be decreased.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: December 11, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Junzou Wakuda, Masaomi Hioki, Satoshi Tanaka, Tomohiro Machida, Kunio Kamimura, Tatsuo Saga, Takashi Tomita
  • Patent number: 7291782
    Abstract: Charge-splitting networks, optoelectronic devices, methods for making optoelectronic devices, power generation systems utilizing such devices and method for making charge-splitting networks are disclosed. An optoelectronic device may include a porous nano-architected (e.g., surfactant-templated) film having interconnected pores that are accessible from both the underlying and overlying layers. A pore-filling material substantially fills the pores. The interconnected pores have diameters of about 1-100 nm and are distributed in a substantially uniform fashion with neighboring pores separated by a distance of about 1-100 nm. The nano-architected porous film and the pore-filling, material have complementary charge-transfer properties with respect to each other, i.e., one is an electron-acceptor and the other is a hole-acceptor. The nano-architected porous, film may be formed on a substrate by a surfactant temptation technique such as evaporation-induced self-assembly.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: November 6, 2007
    Assignee: Nanosolar, Inc.
    Inventors: Brian M. Sager, Martin R. Roscheisen, Klaus Petritsch, Greg Smestad, Jacqueline Fidanza, Gregory A. Miller, Dong Yu
  • Patent number: 7259439
    Abstract: In a semiconductor photodetector 1 according to the present invention, flat surfaces of three steps with different heights are formed in a top surface portion of a semi-insulating GaAs substrate 2. An n-type GaAs layer 3, an i-type GaAs layer 4, and a p-type GaAs layer 5 are successively deposited on the lower step surface formed in a central region of the semi-insulating GaAs substrate 2. Furthermore, a p-side ohmic electrode 6 is provided astride and above a flat surface formed by the p-type GaAs layer 5 and the upper step surface of the semi-insulating GaAs substrate 2, and an n-side ohmic electrode 7 is provided astride and above a flat surface formed by the n-type GaAs layer 3 and the middle step surface of the semi-insulating GaAs substrate 2.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: August 21, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Kazutoshi Nakajima
  • Patent number: 7253493
    Abstract: A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to from word lines that intersect the active area lines at the angled segments.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Chandra Mouli, Luan Tran
  • Patent number: 7253491
    Abstract: A silicon light-receiving device is provided. In the device, a substrate is based on n-type or p-type silicon. A doped region is ultra-shallowly doped with the opposite type dopant to the dopant type of the substrate on one side of the substrate so that a photoelectric conversion effect for light in a wavelength range of 100-1100 nm is generated by a quantum confinement effect in the p-n junction with the substrate. First and second electrodes are formed on the substrate so as to be electrically connected to the doped region. Due to the ultra-shallow doped region on the silicon substrate, a quantum confinement effect is generated in the p-n junction. Even though silicon is used as a semiconductor material, the quantum efficiency of the silicon light-receiving device is far higher than that of a conventional solar cell, owing to the quantum confinement effect. The silicon light-receiving device can also be formed to absorb light in a particular or large wavelength band, and used as a solar cell.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Kyung Lee, Byoung-Lyong Choi, Jun-Young Kim
  • Patent number: 7244998
    Abstract: The present invention is a semiconductor module (20) in which, for example, twenty-five semiconductor devices (10) with a pnotoelectric conversion function are arranged in the form of a five row by five column matrix via an electrically conductive mechanism including of six connecting leads (21 to 26). The semiconductor devices (10) in each column are connected in series, and the semiconductor devices (10) in each row are connected in parallel. Positive and negative terminals, which are embedded in a light transmitting member (28) made of a transparent synthetic resin and which protrude to the outside, are also provided. The semiconductor device (10) comprises a diffusion layer, a pn junction, and one flat surface on the surface of a spherical p-type semiconductor crystal, for example.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: July 17, 2007
    Inventor: Josuke Nakata
  • Patent number: 7230315
    Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 12, 2007
    Assignee: STMicroelectronics S.r.L.
    Inventors: Gabriele Barlocchi, Ubaldo Mastromatteo, Flavio Francesco Villa
  • Patent number: 7227066
    Abstract: Methods for passivating crystalline grains in an active layer for an optoelectronic device and optoelectronic devices having active layers with passivated crystalline grains are disclosed. Crystalline grains of an active layer material and/or window layer material are formed within the nanotubes of an insulating nanotube template. The dimensions of the nanotubes correspond to the dimensions of a crystalline grain formed by the deposition technique used to form the grains. A majority of the surface area of these grains is in contact with the wall of the nanotube template rather than with other grains.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: June 5, 2007
    Assignee: Nanosolar, Inc.
    Inventors: Martin R. Roscheisen, Brian M. Sager
  • Patent number: 7221030
    Abstract: A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in a second region. After that, by performing side etching of the pad oxide film of the first region while protecting the second region with a resist, a gap is formed between the substrate and the silicon nitride film. Subsequently, the inner surfaces of the first and second trenches are oxidized. At this time, a relatively large volume of oxidizing agent (oxygen) is supplied to a top edge portion of the first trench, and the curvature of the corner of the substrate increases.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: May 22, 2007
    Assignee: Fujitsu Limited
    Inventor: Hitoshi Saito
  • Patent number: 7217883
    Abstract: A solar cell involving a silicon wafer having a basic doping, a light-receiving front side and a backside, which is provided with an interdigital semiconductor pattern, which interdigital semiconductor pattern has a first pattern of at least one first diffusion zone having a first doping and a second pattern of at least one second diffusion zone, separated from the first diffusion zone(s) and having a second doping that differs from the first doping, wherein each second diffusion zone is arranged along the sides of at least one groove extending from the backside into the silicon wafer.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 15, 2007
    Assignee: Shell Solar GmbH
    Inventor: Adolf Münzer
  • Patent number: 7214971
    Abstract: A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the boundary between the portion of the p-type layer and the middle region. An n-type layer on the p-type layer has a top surface including a portion on a level with the upper region. Another electrode covers at least part of the boundary between the portion of the n-type layer and the upper region.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: May 8, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Minoru Niigaki, Kazutoshi Nakajima
  • Patent number: 7211820
    Abstract: Quantum-well sensors having an array of spatially separated quantum-well columns formed on a substrate. A grating can be formed increase the coupling efficiency.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: May 1, 2007
    Assignee: California Institute of Technology
    Inventors: Sarath D. Gunapala, Sumith V. Bandara, John K. Liu, Daniel W. Wilson
  • Patent number: 7202899
    Abstract: A method and system for preventing white pixel difficulties resulting from undesired current induced in an image sensor having a photodiode and a depletion region therein. The photodiode is isolated in a pixel layout for an image sensor. A depletion region is configured, such that the depletion region is maintained in a defect-free region associated with the pixel layout for the image sensor, thereby reducing white pixel difficulties caused by induced and undesired current. The image sensor is preferably a CMOS image sensor. A depletion region of the photodiode is constantly maintained in a defect-free region during operation of the CMOS image sensor.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: April 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuen-Hsien Lin, Shang-Hsuan Liu, Chih-Hsing Chen, Hung Jen Tsai, Hsien-Tsong Liu
  • Patent number: 7183597
    Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventor: Brian Doyle
  • Patent number: 7173295
    Abstract: An improved photoconductive semiconductor switch comprises multiple-line optical triggering of multiple, high-current parallel filaments between the switch electrodes. The switch can also have a multi-gap, interdigitated electrode for the generation of additional parallel filaments. Multi-line triggering can increase the switch lifetime at high currents by increasing the number of current filaments and reducing the current density at the contact electrodes in a controlled manner. Furthermore, the improved switch can mitigate the degradation of switching conditions with increased number of firings of the switch.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: February 6, 2007
    Assignee: Sandia Corporation
    Inventors: Alan Mar, Fred J. Zutavern, Guillermo Loubriel
  • Patent number: 7170133
    Abstract: A transistor and a method of fabricating the same: The transistor includes an isolation layer disposed in a semiconductor substrate to define an active region. A pair of source/drain regions is disposed in the active region, spaced apart from each other. A channel region is interposed between the pair of the source/drain regions. The active region has a mesa disposed across the channel region. The mesa extends to the source/drain regions. A gate electrode is disposed to cross the active region along the direction across the mesa.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: January 30, 2007
    Assignee: Samsung Electronics Co.
    Inventors: Young-Chul Jang, Won-Seok Cho, Soon-Moon Jung
  • Patent number: 7136543
    Abstract: A mount assembly which amplifies a light signal from an optical transmission line and transmits the light signal to another optical transmission line and does not require a highly precise perpendicularity at a connection portion between the optical transmission line and the mount assembly. The mount assembly (100) is obtained by connecting a photo-electro conversion device (10a), spherical semiconductor devices (12a) and (12b) and an electro-photo conversion device (10b) through electrical-connection portions (14) so that a light received by the photo-electro conversion device (10a) is amplified by the spherical semiconductor devices (12a) and (12b) and then emitted from the electro-photo conversion device (10b).
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tousaku Nishiyama, Yukihiro Ishimaru, Yasuhiro Sugaya, Toshiyuki Asahi, Seiji Karashima
  • Patent number: 7122840
    Abstract: An image sensor device and fabrication method thereof wherein a substrate having at least one shallow trench isolation structure therein is provided. At least one photosensor and at least one light emitting element, e.g., such as MOS or LED, are formed in the substrate. The photosensor and the light emitting element are isolated by the shallow trench isolation structure. An opening is formed in the shallow trench isolation structure to expose part of the substrate. An opaque shield is formed in the opening to prevent photons from the light emitting element from striking the photosensor.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: October 17, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Hsuan Hsu, Dun-Nian Yaung, Yean-Kuen Fang
  • Patent number: 7115811
    Abstract: The present invention is directed to systems and methods for protecting a solar cell. The solar cell includes first solar cell portion. The first solar cell portion includes at least one junction and at least one solar cell contact on a backside of the first solar cell portion. At least one bypass diode portion is epitaxially grown on the first solar cell portion. The bypass diode has at least one contact. An interconnect couples the solar cell contact to the diode contact.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: October 3, 2006
    Assignee: EMCORE Corporation
    Inventors: Frank Ho, Milton Y. Yeh, Chaw-Long Chu, Peter A. IIes
  • Patent number: 7098589
    Abstract: Light-emitting devices, and related components, systems and methods are disclosed. The light-emitting device can include a multi-layer stack of materials and a support. The multi-layer stack of materials can include a light-generating region and a first layer supported by the light-generating. Thee light-generating region can be between the first layer and the support. The surface of the first layer can be configured so that light generated by the light-generating region can emerge from the light-emitting device via the surface of the first layer. The surface of the first layer can have a dielectric function that varies spatially according to a pattern. The pattern can be formed of holes in the surface of the first layer. The pattern is configured so that light generated by the light-generating region that emerges from the light-emitting device via the surface of the first layer is more collimated than a Lambertian distribution of light.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: August 29, 2006
    Assignee: Luminus Devices, Inc.
    Inventors: Alexei A. Erchak, Eleftrios Lidorikis, Chiyan Luo
  • Patent number: 7087833
    Abstract: Nanocomposite photovoltaic devices are provided that generally include semiconductor nanocrystals as at least a portion of a photoactive layer. Photovoltaic devices and other layered devices that comprise core-shell nanostructures and/or two populations of nanostructures, where the nanostructures are not necessarily part of a nanocomposite, are also features of the invention. Varied architectures for such devices are also provided including flexible and rigid architectures, planar and non-planar architectures and the like, as are systems incorporating such devices, and methods and systems for fabricating such devices. Compositions comprising two populations of nanostructures of different materials are also a feature of the invention.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: August 8, 2006
    Assignee: Nanosys, Inc.
    Inventors: Erik C. Scher, Mihai Buretea, Stephen A. Empedocles
  • Patent number: 7087832
    Abstract: Nanocomposite photovoltaic devices are provided that generally include semiconductor nanocrystals as at least a portion of a photoactive layer. Photovoltaic devices and other layered devices that comprise core-shell nanostructures and/or two populations of nanostructures, where the nanostructures are not necessarily part of a nanocomposite, are also features of the invention. Varied architectures for such devices are also provided including flexible and rigid architectures, planar and non-planar architectures and the like, as are systems incorporating such devices, and methods and systems for fabricating such devices. Compositions comprising two populations of nanostructures of different materials are also a feature of the invention.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: August 8, 2006
    Assignee: Nanosys, Inc.
    Inventors: Erik C. Scher, Mihai Buretea, Calvin Y. H. Chow, Stephen A. Empedocles, Andreas P. Meisel, J. Wallace Parce
  • Patent number: RE40409
    Abstract: A photoelectric converter with improved charge transfer efficiency from a light receiving portion. The photoelectric converter includes a light receiving portion having an output end and a gate portion having a first side and a second side that both define a readout gate width for the light receiving portion, where the first side of the gate portion confronts the output end of the light receiving portion. The photoelectric converter also includes a charge transfer portion formed to confront the second side of the gate portion, where the readout gate width of said gate portion is wider at the first side confronting said light receiving portion than at the second side confronting said charge transfer portion.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: July 1, 2008
    Assignee: Sony Corporation
    Inventors: Satoshi Kitayama, Kazushige Nigawara, Tsuyoshi Sasaki