Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.

Abstract: An UV detector, comprising: a sapphire substrate; a high temperature AlN buffer layer grown on the sapphire substrate; an intermediate temperature GaN buffer layer grown on the high temperature AlN buffer layer; a GaN epitaxial layer deposited on the intermediate temperature GaN buffer layer; a Schottky junction formed on top of the GaN epitaxial layer; and a plurality of ohmic contacts also formed on top of the GaN epitaxial layer, wherein, the high temperature AlN buffer layer and the intermediate temperature GaN buffer layer together form a double buffer layer structure so as to improve the reliability and radiation hardness of the UV detector; and wherein the high temperature AlN buffer layer and the intermediate temperature GaN buffer layer are formed by RF-plasma enhanced MBE growth technology.

Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 ?-?m2 or even less than or equal to 1 ?-?m2 for the electrical device.

Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.

Abstract: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element.

Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

Abstract: To provide a nonvolatile memory which realizes nonvolatile characteristic similar to a flash memory and a high-speed access equivalent to SRAM, has an integration degree exceeding that of DRAM, requires low voltage and low power consumption, and can be driven by a small-size battery, there are provided: (1) a non-volatile memory, including: a pair of metal electrodes; and a nano-hole-containing metal oxide film having a film thickness of 0.

Abstract: A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region.

Abstract: A chip package including a carrier, a chip, a stiffener and a molding compound is provided. A producing method of the chip package includes the steps of disposing a bottom surface of the chip on the carrier; covering an edge of a top surface of the chip with the stiffener for protecting the edge; then wire bonding the top surface of the chip with the carrier; and forming the molding compound for encapsulating the chip, the stiffener and parts of the carrier.

Abstract: The present invention provides a heterojunction photodiode which includes a pn or Schottky-barrier junction formed in a first material region having a bandgap energy Eg1. When reverse-biased, the junction creates a depletion region which expands towards a second material region having a bandgap energy Eg2 which is less than Eg1. This facilitates signal photocurrent generated in the second region to flow efficiently through the junction in the first region while minimizing the process-related dark currents and associated noise due to near junction defects and imperfect surfaces which typically reduce photodiode device performance. The heterojunction photodiode can be included in an imaging system which includes an array of junctions to form an imager.

Abstract: A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and the opposing, second surface. A seed layer is formed on a sidewall defining the at least one hole of the substrate and coated with a conductive layer, and a conductive or nonconductive filler material is introduced into the remaining space within the at least one hole. A method of forming a conductive via through a substrate using a blind hole is also disclosed. Semiconductor components and electronic systems having substrates including the conductive via of the present invention are also disclosed.

Abstract: A semiconductor device, includes: 1) an electric field relaxing area, including: i) a hetero junction formed by the followings: a) a first semiconductor material, and b) a second semiconductor material different from the first semiconductor material in band gap, and ii) an impurity introducing area so formed on the first semiconductor material as to contact the hetero junction.

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solid state chemical sensors. Detention of the following chemical species was established: hydrogen, deuterium, carbon monoxide, and molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Abstract: The present invention relates to organic semiconductor diodes, in particular, to the diodes with nonlinear current-voltage characteristics, which are used for power switching, rectifying variable signals, and frequency mixing. The organic semiconductor diode with the p-n junction comprises an anode, cathode, a hole transport layer in contact with the anode, and an electron transport layer in contact with the cathode, and two transport layers being in contact with each other. Another aspect of the present invention is a Schottky barrier diode comprising anode, cathode, and an organic semiconductor layer, wherein the semiconductor layer is either hole or electron transport layer. At least one of the transport layers is characterized by a globally ordered crystalline structure with intermolecular spacing of 3.4±0.3 ? in the direction of one crystal axis. One more aspect of the present invention is a method for obtaining an organic semiconductor layer with the electron-hole type of conductivity.

Abstract: An organic Schottky diode includes a polycrystalline organic semiconductor layer with a rectifying contact on one side of the layer. An amorphous doped semiconductor layer is placed on the other side of the polycrystalline organic semiconductor layer, and it acts as a buffer between the semiconductor layer and an ohmic contact layer.

Abstract: A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode having a work function of less than about 4.3 eV or greater than about 4.9 eV overlying the gate dielectric, a spacer having a thickness of less than about 100 ? on a side of the gate electrode, and a Schottky source/drain having a work function of less than about 4.3 eV or greater than about 4.9 eV wherein the Schottky source/drain region overlaps the gate electrode. The Schottky source/drain region preferably has a thickness of less than about 300 ?.

Abstract: A problem in related art according to which an increase in leak current cannot be avoided in order to obtain a low forward voltage VF as forward voltage VF and reverse leak current IR characteristics of a Schottky barrier diode are in a trade-off relationship is hereby solved by forming a Schottky barrier diode using a metal layer comprising a Schottky metal layer of Ti including a small amount of Al. Consequently, a low reverse leak current IR can be obtained without causing a large increase in the forward voltage VF of pure Ti such that power consumption can be reduced by suppressing forward power loss and decreasing reverse power loss.

Abstract: A buffer layer, an undoped gallium nitride layer, and an n-type gallium nitride active layer are formed on a sapphire substrate. Ohmic contacts and a Schottky contact are then formed on the n-type gallium nitride active layer as a source contact, a drain contact and a gate contact, respectively. The Schottky contact is a copper alloy, such as palladium copper, in which the content by weight of copper is 5%.

Abstract: A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.

Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 ?-?m2 or even less than or equal to 1 ?-?m2 for the electrical device.

Abstract: A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed.

Abstract: A Merged P-i-N Schottky device in which the oppositely doped diffusions extend to a depth and have been spaced apart such that the device is capable of absorbing a reverse avalanche energy comparable to a Fast Recovery Epitaxial Diode having a comparatively deeper oppositely doped diffusion region.

Abstract: To reduce a reverse leakage current in a Schottky barrier diode with achieving a lower forward voltage Vf and a smaller capacitance than in the related art, a Schottky barrier diode includes a semiconductor layer of a first conductivity type, a first electrode which is a metal layer forming a Schottky contact with a main surface of the semiconductor layer, a second electrode forming an ohmic contact with an opposite main surface of the semiconductor layer, a buried layer of a second conductivity type formed within the semiconductor layer so as not to be in contact with the first electrode, where the second conductivity type has a different charge carrier from the first conductivity type, and a guard ring of the second conductivity type formed within the semiconductor layer so as to be in contact with the first electrode and also to surround the buried layer without contacting with the buried layer.

Abstract: A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drain layer has a drain Fermi-Level (EF4). A channel layer is provided between the source layer and the drain layer, the channel layer being made with a material having a channel band-gap (EG3) and a channel mid-gap value (EGM3), the channel layer having a channel Fermi-Level (EF3). A source contact layer is connected to the source layer opposite the channel layer, the source contact layer having a source contact Fermi-Level (EF1). A gate electrode has a gate electrode Fermi-Level (EF6). The source band-gap is substantially narrower (EG2) than the channel band-gap (EG3).

Abstract: A semiconductor diode with hydrogen detection capability includes a semiconductor substrate, a doped semiconductor active layer formed on the substrate and made from a compound having the formula XYZ, in which X is a Group III element, Y is another Group III element different from X, and Z is a Group V element, a semiconductor contact-enhancing layer formed on the active layer and made from a compound having the formula MN, in which M is a Group III element, and N is a Group V element, an ohmic contact layer formed on the semiconductor contact-enhancing layer, and a Schottky barrier contact layer formed on the active layer. The Schottky barrier contact layer is made from a metal that is capable of dissociating a hydrogen molecule into hydrogen atoms.

Abstract: Described is an electronic device comprising a junction formed between a first fullerene layer having a first doping concentration and a second fullerene layer having a second doping concentration different from the first doping concentration. The first doping concentration may be zero. The first and/or the second fullerene layer may be a monolayer. The second fullerene layer may comprise an electron donor. One example of such a device is a diode wherein the first fullerene layer is connected to an anode and the second fullerene layer is connected to a cathode. Another example is a field effect transistor wherein the first fullerene layer serves as a gate region and the second fullerene layer serves as a channel region. The second fullerene layer may alternatively comprise an electron acceptor. At least one of the first and second fullerene layers may be formed from C60, or may consist of a single bucky ball.

Abstract: The present disclosure provides a deep submicron electrostatic discharge (ESD) protection structure for a deep submicron integrated circuit (IC) and a method for forming such a structure. The structure includes at least two electrodes separated by a dielectric material, such as a thin gate oxide layer. In some examples, the thin gate oxide may be less than 25 ? thick. A source and drain are positioned proximate to and on opposite sides of one of the electrodes to form a channel. The drain is covered with a silicide layer that enhances the ESD protection provided by the structure. The source may also be covered with a silicide layer. In some examples, the drain may be floating.

Abstract: A method for producing a semiconductor component with adjacent Schottky (5) and pn (9) junctions positions in a drift area (2, 10) of a semiconductor material. According to the method, a silicon carbide substrate doped with a first doping material of at least 1018 cm?3 is provided, and a silicon carbide layer with a second doping material of the same charge carrier type in the range of 1014 and 1017 cm?3 is homo-epitaxially deposited on the substrate. A third doping material with a complimentary charge carrier is inserted, and structured with the aid of a diffusion and/or ion implantation, on the silicon carbide layer surface that is arranged far from the substrate to form pn junctions. Subsequently the component is subjected to a first temperature treatment between 1400° C. and 1700° C. Following this temperature treatment, a first metal coating is deposited on the implanted surface in order to form a Schottky contact and then a second metal coating is deposited in order to form an ohmic contact.

Abstract: A memory cell and method of fabricating the memory cell includes an insulating layer formed on a first electrode layer, the insulating layer having a first opening, a stencil layer formed on the insulating layer, and having a second opening formed in an area of the first opening, a phase-change material layer formed on a surface of the first electrode layer in the first opening, and an electrically conductive layer including a first portion formed on the stencil layer and defining a second electrode layer and a second portion formed on the phase-change material layer.

Abstract: The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer. For example, the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. In another embodiment, the seed layer comprises a copper allloy seed layer deposited over the barrier layer and a second seed layer deposited over the copper alloy seed layer. The copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof The second seed layer may comprise a metal, such as undoped copper. In still another embodiment, the seed layer comprises a first seed layer and a second seed layer.

Abstract: A Schottky diode has a Schottky junction formed by a thin metal layer and/or metal silicide layer at the top side of a doped well in a semiconductor body or substrate. In contrast to the fabrication of low-impedance contacts on CMOS wells, a metal, to be precise titanium in the preferred embodiment, is applied not to a highly doped contact region but to the lightly doped semiconductor material of the doped well, for example an HV well for the fabrication of high-voltage transistors.

Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.

Abstract: An integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.

Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.

Abstract: A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drain layer has a drain Fermi-Level (EF4). A channel layer is provided between the source layer and the drain layer, the channel layer being made with a material having a channel band-gap (EG3) and a channel mid-gap value (EGM3), the channel layer having a channel Fermi-Level (EF3). A source contact layer is connected to the source layer opposite the channel layer, the source contact layer having a source contact Fermi-Level (EF1). A gate electrode has a gate electrode Fermi-Level (EF6). The source band-gap is substantially narrower (EG2) than the channel band-gap (EG3).

Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.

Abstract: The invention describes herein relates to new titanium-comprising materials which can be utilized for forming titanium alloy sputtering targets. The titanium alloy sputtering targets can be reactively sputtered in a nitrogen-comprising sputtering atmosphere to form an alloy TiN film, or alternatively in a nitrogen-comprising and oxygen-comprising sputtering atmosphere to form an alloy TiON thin film. The thin films formed in accordance with the present invention can have a non-columnar grain structure, low electrical resistivity, high chemical stability, and barrier layer properties comparable to those of TaN for thin film Cu barrier applications. Further, the titanium alloy sputtering target materials produced in accordance with the present invention are more cost-effective for semiconductor applications than are high-purity tantalum materials and have superior mechanical strength suitable for high-power sputtering applications.

Abstract: A preferred embodiment of the present invention provides a Schottky diode (100) formed from a conductive anode contact (102), a semiconductor junction layer (104) supporting the conductive contact (102) and a base layer ring (108) formed around at least a portion of the conductive anode contact (102). In particular, the base layer ring (108) has material removed to form a base layer material gap (118) (e.g., a vacuum gap) adjacent to the conductive anode contact (102). A dielectric layer (110) is also provided to form one boundary of the base layer material gap (118).

Abstract: The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a platinum silicide, or of a metal silicide having with the P-type silicon a barrier height lower than or equal to that of the platinum silicide.

Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.

Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

Abstract: A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide layer. A trench crosses the P-type epitaxial layer and penetrates into at least a portion of the height of the N-type epitaxial layer beyond the periphery of the active area. The doping level of the P-type epitaxial layer is chosen so that, for the maximum voltage that the diode is likely to be subjected to, the equipotential surfaces corresponding to approximately ¼ to ¾ of the maximum voltage extend up to the trench.

Abstract: A method for producing Schottky diodes having a protective ring in an edge region of a Schottky contact. The protective ring is produced by a protective ring material that is deposited onto a surface of a semiconductor layer, which surface is provided with a patterned masking layer beforehand, and the protective ring material subsequently being siliconized. In this case, the protective ring material constitutes a metal, in particular a high barrier metal, which has, in particular, platinum.

Abstract: A rectifier structure that exhibits a low turn-on voltage and allows rapid switching without ringing is provided. The structure utilizes a thin epitaxial layer interposed between the two layers comprising the rectifier junction. Preferably the epitaxial layer is of the same conductivity as the underlying layer while being comprised of the same material as the outermost layer.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings in an implant and drive system. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or palladium contact layer. A thin high resistivity layer of amorphous silicon is deposited over the full upper surface of the wafer and is disposed between the wafer upper surface and all of the metal rings.

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A substrate-fluorescent LED having a fluorescent-impurity doped substrate and an epitaxial emission structure including an active layer and being made on the substrate. The epitaxial emission structure emits blue or green light corresponding to the band gap of the active layer. The substrate absorbs a part of the blue or green light and makes fluorescence of a longer wavelength. Neutral color light or white light is emitted from the LED. The fluorescent substrate is n-AlGaAs(Si dope), GaP(Zn+O dope), ZnSe(Cu+I, Ag+I, Al+I dope), GaN(O.C.Va(N) dope) or so.