With Electric Field Controlling Semiconductor Layer Having A Low Enough Doping Level In Relationship To Its Thickness To Be Fully Depleted Prior To Avalanche Breakdown (e.g., Resurf Devices) Patents (Class 257/493)
  • Patent number: 7704864
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a heavily doped region of a first conductivity and has a lightly doped region of the first conductivity. The semiconductor substrate a plurality of trenches etched into an active region of the substrate forming a plurality of mesas. A preselected area in the active region is oxidized and then etched using a dry process oxide etch to remove the oxide in the bottoms of the trenches. A protective shield is formed over a region at a border between the active region and the termination region. The protective shield is partially removed from over the preselected area. Dopants are implanted at an angle into mesas in the preselected area. The plurality of trenches are with an insulating material, the top surface of the structure is planarized and a superjunction device is formed on the structure.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: April 27, 2010
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7692242
    Abstract: A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: April 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Norio Yasuhara, Yusuke Kawaguchi, Kenichi Matsushita
  • Patent number: 7679160
    Abstract: A high voltage/power semiconductor device has at least one active region having a plurality of high voltage junctions electrically connected in parallel. At least part of each of the high voltage junctions is located in or on a respective membrane such that the active region is provided at least in part over plural membranes. There are non-membrane regions between the membranes. The device has a low voltage terminal and a high voltage terminal. At least a portion of the low voltage terminal and at least a portion of the high voltage terminal are connected directly or indirectly to a respective one of the high voltage junctions. At least those portions of the high voltage terminal that are in direct or indirect contact with one of the high voltage junctions are located on or in a respective one of the plural membranes.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: March 16, 2010
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Gehan Anil Joseph Amaratunga
  • Patent number: 7679146
    Abstract: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: March 16, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shanghui Larry Tu, Gordon M. Grivna
  • Patent number: 7671440
    Abstract: A field-effect transistor having cells (18) each having a source region (22), source body region (26), drift region (20), drain body region (28) and drain region (24) arranged longitudinally, laterally alternating with structures to achieve a reduced surface field. In embodiments, the structures can include longitudinally spaced insulated gate trenches (35) defining a gate region (31) adjacent the source or drain region (22, 24) and a longitudinally extending potential plate region (33) adjacent the drift region (20). Alternatively, a separate potential plate region (33) or a longitudinally extending semi-insulating field plate (50) may be provided adjacent the drift region (20). The transistor is suitable for bi-directional switching.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: March 2, 2010
    Assignee: NXP B.V.
    Inventors: Raymond J. E. Hueting, Erwin A. Hijzen
  • Publication number: 20100044825
    Abstract: In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body.
    Type: Application
    Filed: August 19, 2008
    Publication date: February 25, 2010
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Gerhard Schmidt
  • Patent number: 7663203
    Abstract: In a high-voltage PMOS transistor having an insulated gate electrode (18), a p-conductive source (15) in an n-conductive well (11), a p-conductive drain (14) in a p-conductive well (12) which is arranged in the n-conductive well, and having a field oxide area (13) between the gate electrode and drain, the depth (A?-B?) of the n-conductive well underneath the drain (14) is less than underneath the source (15), and the depth (A?-B?) of the p-conductive well is greatest underneath the drain (14).
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: February 16, 2010
    Assignee: Austriamicrosystems AG
    Inventor: Martin Knaipp
  • Publication number: 20100032685
    Abstract: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P—N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P—N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.
    Type: Application
    Filed: August 11, 2008
    Publication date: February 11, 2010
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Publication number: 20100032791
    Abstract: A semiconductor device includes: a first semiconductor region of a first conductivity type disposed on the side of a first electrode; and a second semiconductor region having first pillar regions of the first conductivity type and second pillar regions of a second conductivity type, the first pillar regions and the second pillar regions being provided in paired state and alternately, in a device portion and a terminal portion surrounding the device portion, along a surface on the side of a second electrode disposed on the opposite side of the first semiconductor region from the first electrode. The semiconductor device further includes a lateral RESURF (reduced surface field) region of the second conductivity type disposed at a surface portion, on the opposite side from the first semiconductor region, of the second semiconductor region in the terminal portion.
    Type: Application
    Filed: July 7, 2009
    Publication date: February 11, 2010
    Applicant: Sony Corporation
    Inventors: HIROKI HOZUMI, YUJI SASAKI, YANAGAWA SHUSAKU
  • Patent number: 7652307
    Abstract: In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: January 26, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Kiyofumi Nakaya, Shigeaki Okawa
  • Patent number: 7649225
    Abstract: An asymmetric heterodoped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a second polarity. A source region is disposed inside each tub region and has dopants of a first polarity opposite to the second polarity. On the other side of the gate, heterodoped buffer and drift regions are formed. The buffer regions comprise dopants of the second polarity. The drift regions are disposed inside the buffer regions and are doped with dopants of the first polarity. A drain n+ tap region is disposed in the drift region.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: January 19, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Michael Harley-Stead, Jim G. Holt
  • Patent number: 7642139
    Abstract: A production method for a semiconductor device, including the steps of: forming a semiconductor layer of the first conductivity on the semiconductor substrate; forming a trench in the semiconductor layer, the trench penetrating through the semiconductor layer to reach the semiconductor substrate; filling a filling material in a predetermined bottom portion of the trench, so that a filling material portion is provided in the bottom portion of the trench up to a predetermined upper surface position which is shallower than an interface between the semiconductor substrate and the semiconductor layer; and, after the filling step, introducing an impurity of the second conductivity into a portion of the semiconductor layer exposed to an interior side wall of the trench.
    Type: Grant
    Filed: December 24, 2004
    Date of Patent: January 5, 2010
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Publication number: 20090309182
    Abstract: A first embodiment of an Electrostatic Discharge (ESD) structure for an integrated circuit for protecting the integrated circuit from an ESD signal, has a substrate of a first conductivity type. The substrate has a top surface. A first region of a second conductivity type is near the top surface and receives the ESD signal. A second region of the second conductivity type is in the substrate, separated and spaced apart from the first region in a substantially vertical direction. A third region of the first conductivity type, heavier in concentration than the substrate, is immediately adjacent to and in contact with the second region, substantially beneath the second region. In a second embodiment, a well of a second conductivity type is provided in the substrate of the first conductivity type. The well has a top surface. A first region of the second conductivity type is near the top surface. A second region of the second conductivity type is in the well, substantially along the bottom of the well.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 17, 2009
    Inventors: Kung-Yen Su, Yaw Wen Hu, Bomy Chen, Kevin Gene-Wah Jew
  • Patent number: 7629631
    Abstract: A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of JFET regions separated by portions of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and at least two sides of each JFET region is lined with an oxide layer. In one group of embodiments the JFET regions extend from the surface of an epitaxial layer to an interface between the epitaxial layer and an underlying substrate, and the walls of each JFET region are lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region and allowing the JFET regions to be accurately located in the drift region.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: December 8, 2009
    Inventor: Hamza Yilmaz
  • Patent number: 7622787
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: November 24, 2009
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Brain D. Pratt
  • Publication number: 20090267174
    Abstract: A semiconductor device with a charge carrier compensation structure in a semiconductor body and to a method for its production. The semiconductor body includes drift zones of a first conduction type and charge compensation zones of a second conduction type complementing the first conduction type. The drift zones include a semiconductor material applied in epitaxial growth zones, wherein the epitaxial growth zones include an epitaxially grown semiconductor material which is non-doped to lightly doped. Towards the substrate, the epitaxial growth zones are provided with a first conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of a second, complementary conduction type. Towards the front side, the epitaxial growth zones are provided with a second, complementary conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of the first conduction type.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 29, 2009
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Armin Willmeroth, Michael Rueb
  • Patent number: 7598586
    Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity; and a semiconductor layer provided on the semiconductor substrate and having a super junction structure including drift layers of the first conductivity and RESURF layers of a second conductivity different from the first conductivity, the drift layers and the RESURF layers being laterally arranged in alternate relation parallel to the semiconductor substrate, the RESURF layers being each provided alongside an interior side wall of a trench penetrating through the semiconductor layer, the drift layers each having an isolation region present between the RESURF layer and the semiconductor substrate to prevent the RESURF layer from contacting the semiconductor substrate.
    Type: Grant
    Filed: December 24, 2004
    Date of Patent: October 6, 2009
    Assignee: ROHM Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 7589389
    Abstract: A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: September 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Norio Yasuhara
  • Patent number: 7576393
    Abstract: A semiconductor device comprises a pillar layer including first semiconductor pillars of a first conduction type and second semiconductor pillars of a second conduction type formed laterally, periodically and alternately. The first and second semiconductor pillars include a plurality of diffusion layers formed in a third semiconductor layer as coupled along the depth. The diffusion layers have lateral widths varied at certain periods along the depth. An average of the lateral widths of the diffusion layers in one certain period is made almost equal to another between different periods.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: August 18, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Wataru Saito
  • Patent number: 7550804
    Abstract: A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: June 23, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer, Ronghua Zhu
  • Patent number: 7546557
    Abstract: The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transistor(s) can be adjusted to change the capacitive and/or resistive capability of the transistor(s). These altered diffusion structures can reduce the peak IR drop value, such as by an amount in the range of 8%-30% of the original peak noise, to prevent the chip from malfunctioning due to the resultant noise. The reduction in IR drop can be balanced with the timing delays introduced by the increased capacitance of the source area. An optimal combination of source area and drain width can be obtained and instituted during the simulation and testing processes.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: June 9, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Myung Jin Kong
  • Patent number: 7541248
    Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: June 2, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuya Nitta, Tomohide Terashima
  • Patent number: 7541660
    Abstract: A The semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: June 2, 2009
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Frank Hille, Thomas Raker
  • Patent number: 7538407
    Abstract: A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: May 26, 2009
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masato Taki, Hideki Tojima
  • Patent number: 7535057
    Abstract: Floating trenches are arranged in the layout of a single DMOS transistor or an array of DMOS transistors, the array forming a single power transistor. The trenches run perpendicular to the gate width direction either outside the transistor(s) or between rows of the transistors. The floating trenches are at a potential between the drain voltage and the substrate voltage (usually ground). The potentials of the opposing trenches cause merging depletion regions in the drift region. This merging shapes the field lines so as to increase the breakdown voltage of the transistor and provide other advantages. The technique is applicable to both lateral and vertical DMOS transistors.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: May 19, 2009
    Inventor: Robert Kuo-Chang Yang
  • Patent number: 7531888
    Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: May 12, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Cai
  • Patent number: 7511319
    Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET)(100) incorporates a stepped drift region including a shallow trench insulator (STI)(112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: March 31, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Todd C. Roggenbauer
  • Patent number: 7511353
    Abstract: A semiconductor diode (30) has an anode (32), a cathode (33) and a semiconductor volume (31) provided between the anode (32) and the cathode (33). An electron mobility and/or hole mobility within a zone (34) of the semiconductor volume (31) that is situated in front of the cathode (33) is reduced relative to the rest of the semiconductor volume (31).
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: March 31, 2009
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Frank Hille, Vytla Rajeev Krishna, Elmar Falck, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Helmut Strack
  • Publication number: 20090051000
    Abstract: A semiconductor device structure is provided. By placing an insulating dielectric material in the drift region of a device to modulate the electric field distribution and current flow in the drift region, the breakdown voltage of the device is increased while the turn-on impedance of the device is reduced.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 26, 2009
    Inventors: JENG GONG, Wen-Chun Chung, Ru-Yi Su, Fu-Hsiung Yang
  • Patent number: 7482205
    Abstract: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: January 27, 2009
    Assignee: International Rectifier Corporation
    Inventor: Thomas Herman
  • Patent number: 7476931
    Abstract: A vertical semiconductor device includes a vertical, active region including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type, a trench extending through the third semiconductor layer at least into the second semiconductor layer, the trench comprising a first portion bordering on the third semiconductor layer, and the trench comprising a second portion extending at least into the second semiconductor layer starting from the first portion, an insulating layer associated with a control terminal and at least partially arranged on a side wall of the first portion of the trench and at least partially extending into the second portion of the trench, and a resistive layer with a field-strength-dependent resistance and arranged in the second portion of the trench at least partially on the sidewall and the bottom of the trench.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: January 13, 2009
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 7473965
    Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: January 6, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tomohide Terashima
  • Patent number: 7466006
    Abstract: Methods and apparatus are provided for reducing substrate leakage current of lateral RESURF diode devices. The diode device (60, 60?, 100) comprises first (39) and second (63) surface terminals overlying a semiconductor substrate (22) coupled to P (38, 32, 26) and N (24, 30, 46) type regions providing the diode action. An unavoidable parasitic vertical device (54, 92) permits leakage current to flow from the first terminal (39) to the substrate (22). This leakage current is reduced by having the diode device second terminal (63) comprise both N (46) and P (62) type regions coupled together by the second terminal (63). This forms a shorted base-collector lateral transistor (72) between the first (39) and second (63) terminals to provide the diode function. The gain of this lateral transistor (72) increases the proportion of first terminal (39) current that flows to the second terminal (63) rather than the substrate (22).
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: December 16, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishnu K. Khemka, Ronghua Zhu, Amitava Bose
  • Publication number: 20080283956
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Application
    Filed: April 16, 2008
    Publication date: November 20, 2008
    Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Patent number: 7449762
    Abstract: A Lateral Epitaxial Gallium Nitride metal insulator semiconductor field effect transistor (LEGaN-MISFET) is described that includes a body region including at least one layer formed of Gallium Nitride having a first conductivity type formed on the substrate; a resurf layer of Gallium Nitride having a second conductivity type formed the body region; a source region in contact with the resurf layer; a drain region, in contact with the resurf layer and spaced apart from the source region; a gate metal insulator semiconductor (MIS) structure in contact with the body region including a gate contact; and a MIS conductive inversion channel along the surface of the body region in contact with the gate MIS structure. A lateral current conduction path may be formed in the resurf layer between the source region and the drain region connected by the MIS channel, where the lateral current conduction path is controlled by an applied gate source bias.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: November 11, 2008
    Assignee: Wide Bandgap LLC
    Inventor: Ranbir Singh
  • Patent number: 7446387
    Abstract: In a HV transistor having a high breakdown voltage and a method of manufacturing the same, a first insulation pattern is formed on a semiconductor substrate by oxidizing a portion of the substrate, and a second insulation pattern is formed such that at least a portion of the first insulation pattern is covered with the second insulation pattern. A gate electrode including a first end portion and a second end portion opposite to the first end portion is formed on the substrate by depositing conductive materials onto the substrate. The first end portion is formed on the first insulation pattern and the second end portion is formed on the second insulation pattern. Source/drain regions are formed at surface portions of the substrate by implanting impurities onto the substrate. Electric field intensity at an edge portion of the gate electrode is reduced, and the HV transistor has a high breakdown voltage.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: November 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-Hyun Kang, Hwa-Sook Shin, Mueng-Ryul Lee
  • Publication number: 20080258208
    Abstract: A semiconductor component including compensation zones and discharge structures for the compensation zones. One embodiment provides a drift zone of a first conduction type, at least one compensation zone of a second conduction type, complementary to the first conduction type, the at least one compensation zone being arranged in the drift zone, at least one discharge structure which is arranged between the at least one compensation zone and a section of the drift zone that surrounds the compensation zone or in the compensation zone and designed to enable a charge carrier exchange between the compensation zone and the drift zone if a potential difference between an electrical potential of the compensation zone and an electrical potential of the section of the drift zone that surrounds the compensation zone is greater than a threshold value predetermined by the construction and/or the positioning of the discharge structure.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 23, 2008
    Applicant: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Ralf Siemieniec, Ilja Pawel
  • Patent number: 7436025
    Abstract: A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24? of the second dopant type.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: October 14, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Todd C. Roggenbauer
  • Patent number: 7436041
    Abstract: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: October 14, 2008
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu
  • Publication number: 20080237774
    Abstract: A semiconductor device includes: a semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a major surface of the semiconductor substrate and having lower doping concentration than the semiconductor substrate; a plurality of first semiconductor column regions of the first conductivity type provided on the first semiconductor layer; a plurality of second semiconductor column regions of a second conductivity type provided on the first semiconductor layer, the second semiconductor column regions being adjacent to the first semiconductor column regions; a first semiconductor region; a second semiconductor region; a gate insulating film; a first main electrode; a second main electrode; and a control electrode. Doping concentrations in both the first and second semiconductor column region are low on the near side of the first semiconductor layer and high on the second main electrode side.
    Type: Application
    Filed: September 28, 2007
    Publication date: October 2, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Syotaro ONO, Wataru Saito
  • Publication number: 20080237775
    Abstract: An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and a cathode diffusion contact region doped to the second conductivity type disposed in the first region. The diode can also comprise a cathode contact electrically contacting the cathode diffusion contact region, an anode disposed in the island, an anode contact electrically contacting the anode, and a first extension region doped to the first conductivity type disposed at a surface junction between the first region and the island.
    Type: Application
    Filed: May 6, 2008
    Publication date: October 2, 2008
    Inventor: James Douglas BEASOM
  • Patent number: 7427795
    Abstract: Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 23, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Sameer Pendharkar
  • Publication number: 20080191307
    Abstract: A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the structure. The electrical characteristic of the structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The structure optionally includes a fourth region that extends into the third region, and surrounds a portion of the pair of dielectric regions. The interface region between the dielectric regions and the fourth region includes intentionally introduced charges.
    Type: Application
    Filed: January 8, 2008
    Publication date: August 14, 2008
    Applicant: MaxPower Semiconductor, Inc.
    Inventor: Mohamed N. Darwish
  • Patent number: 7411266
    Abstract: In one embodiment, a semiconductor device is formed having charge compensation trenches in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: August 12, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Shanghui Larry Tu, Gordon M. Grivna
  • Patent number: 7408234
    Abstract: An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate; a semiconductor layer having a P? type active region that is formed on the supporting substrate, interposing a buried oxide film between the semiconductor layer and the supporting substrate; and a gate electrode that is formed on the semiconductor layer, interposing a gate oxide film and a part of a LOCOS film between the gate electrode and the semiconductor layer, wherein the P? type active region has: an N+ type source region; a P type body region; a P+ type back gate contact region; an N type drain offset region; an N+ type drain contact region; and an N type drain buffer region that is formed in a limited region between the N type drain offset region and the P type body region, and the N type drain buffer region is in contact with a source sid
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: August 5, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisao Ichijo, Hiroyoshi Ogura, Yoshinobu Sato, Teruhisa Ikuta
  • Publication number: 20080128798
    Abstract: One aspect is a semiconductor component including a terminal zone; a drift zone of a first conduction type, which is doped more weakly than the terminal zone; a component junction between the drift zone and a further component zone; and a charge carrier compensation zone of the first conduction type, which is arranged between the drift zone and the terminal zone and whose doping concentration is lower than that of the terminal zone, and whose doping concentration increases at least in sections in the direction of the terminal zone from a minimum doping concentration to a maximum doping concentration, the minimum doping concentration being more than 1016 cm?3.
    Type: Application
    Filed: October 1, 2007
    Publication date: June 5, 2008
    Applicant: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Josef Lutz
  • Patent number: 7372111
    Abstract: The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of second n-type regions and second p-type regions arranged alternately. The peripheral section further includes a third alternating conductivity type layer in its surface portion. The third alternating conductivity type layer is formed of third n-type regions and third p-type regions arranged alternately. At least the peripheral section is configured to improve the avalanche withstanding capability over the entire device.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: May 13, 2008
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Yasuhiko Onishi, Takeyoshi Nishimura, Yasushi Niimura, Masanori Inoue
  • Patent number: 7372104
    Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: May 13, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
  • Patent number: 7364994
    Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: April 29, 2008
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Brian D. Pratt
  • Patent number: 7365402
    Abstract: An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial layer of a second conductivity type, a channel located between the drain and source regions, and a gate arranged above the channel within an insulating layer, wherein the lightly doped drain region comprises an implant region of the first conductivity type extending from the surface of the epitaxial layer into the epitaxial layer covering an end portion of the lightly doped drain region next to the gate.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: April 29, 2008
    Assignee: Infineon Technologies AG
    Inventor: Gordon Ma