Abstract: Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.

Abstract: A method of mass-producing a solid state device comprises providing an atomically smooth, solid state material layer no more than 40 Angstroms thick. This layer is uniformly and defect-freely bonded onto a substrate to provide an acceptable device yield.

Abstract: Disclosed herein is a dummy pattern structure of a semiconductor device. The dummy pattern structure may include daughter dummy patterns respectively formed at places corresponding to vertexes of polygons in regions where metal wirings are not formed in an interlayer insulating film where metal wirings are formed, thus being arranged in the whole region while constituting a polygon shape, and mother dummy patterns respectively formed at places corresponding to the middles of the polygon, which is formed by the daughter dummy patterns. Generation of metal residues in a region where metal wirings are not formed when the metal wirings are formed by means of a damascene process are prevented. Also, a delamination phenomenon that interlayer insulating films are fallen apart can be prevented.

Abstract: Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).

Abstract: The present invention provides an optoelectronic device and a method of manufacture thereof. In one embodiment, the method of manufacturing the optoelectronic device may include creating a multilayered optical substrate and then forming a self aligned dual mask over the multilayered optical substrate. The method may further include etching the multilayered optical substrate through the self aligned dual mask to form a mesa structure.

Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.

Abstract: To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and second conductive patterns 11B, onto which comparatively thick second circuit elements 12B are mounted, are formed thinly. Also, fine wiring parts may be formed using the thinly formed second conductive patterns 12B. Thus even in the case where thick circuit elements are incorporated, by affixing such circuit elements onto the thinly formed second conductive patterns 11B, the total thickness can be made thin. Thinning of circuit device 10 as a whole can thus be accomplished.

Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Abstract: The termination of a MOSgated device is formed by a trench bevel which surrounds the active device area. The trench bevel has flat walls which extend into and through the epitaxial layer containing the active area which has a lateral extend equal to or less than the thickness of the epitaxial layer. The surface of the bevel is coated with a resistive film, preferably, an amorphous silicon which connects the device source to the device drain to cause the electric field in the epitaxial silicon to the linearly distributed over the length of the bevel.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.

Abstract: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate of a first conductive type; a semiconductor layer of the first conductive type formed on the semiconductor substrate; a base layer of a second conductive type formed on the semiconductor layer; a plurality of columns of stripe trenches formed at predetermined intervals from a surface of the base layer by a predetermined depth; insulating films formed on side surfaces and bottoms of the trenches, respectively; source layers of the first conductive type formed on surface layer portions of the base layer between the trenches, respectively; stripe contact layers of the second conductive type formed each at centers of the surface layer portions of the base layer between the trenches, respectively; a gate electrode formed in every other trench among the plurality of columns of trenches; source electrodes formed in the trenches other than the trenches in which the gate electrodes are formed and on the sour

Abstract: An integrated circuit having structure for isolating circuit sections having at least one differing characteristic. The structure includes a chip guard ring for each circuit section having the at least one differing characteristic. Providing multiple chip guard rings allows for isolation of circuit sections and prevention of ionic contamination, but without increased expense and size. In addition, it is practicable with any IC. The invention also may include an interconnect for electrical connectivity about a chip guard ring.

Abstract: A semiconductor device includes a stable high withstand voltage lateral MISFET device which suppresses a gradual withstand voltage drop under high voltage and humidity conditions. In a MISFET device with a 700V breakdown drain voltage, the length of extension Mc (&mgr;m) of a field plate FP1 from the source side end of a thermal oxidization film, and the total insulating film thickness Tox (&mgr;m) directly below the extending tip of the field plate FP1, are greater than or equal to lower limit values Mcmin, Tcmin. As a result, even if there is growth in charge accumulation at the interface of the mold resin, the field strength at a point B and point C is always lower than at a point A, which suppresses a gradual withstand voltage drop and a gradual ON current drop, whereby it becomes possible to realize a withstand voltage of 700V.

Abstract: A switching power supply including a power factor correction circuit comprises a rectifier, an inductor coupled in series with the rectifier, a semiconductor switch formed by a compensation device coupled in parallel with the rectifier and the inductor. The output circuit comprises a diode coupled in series with a capacitor both coupled in parallel with the semiconductor switch. An input current sensor, and a control unit for controlling the compensation device are provided.

Abstract: A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone. An edge area outside of the first zone has areas etched out. A second zone of a second conductivity type is disposed in the semiconductor body and is connected to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and is embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.

Abstract: A lateral semiconductor device has a semiconductor layer on an insulating layer on a semiconductor substrate. The semiconductor layer has a region of a first conduction type and a region of a second conduction type with a drift region therebetween. The drift region is provided by a region of the first conduction type and a region of the second conduction type. The first and second conduction type drift regions are so arranged that when a reverse voltage bias is applied across the first and second conduction type regions of the semiconductor layer, the second conduction type drift region has an excess of charge relative to the first conduction type drift region which varies substantially linearly from the end of the drift region towards the first conduction type region of the semiconductor layer to the end of the drift region towards the second conduction type region of the semiconductor layer.

Abstract: A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, comprises a semiconductor substrate, a plurality of parallel trenches formed in the semiconductor substrate, a peripheral trench formed in the semiconductor substrate and spaced from and at least partially surrounding the parallel trenches, a dielectric material lining the trenches, and a conductive material substantially filling the dielectric-lined trenches.

Abstract: A surface orientation other than a (100) surface orientation is exposed to the surface portion of a silicon substrate having the (100) surface orientation, for example. A silicon epitaxial growth layer is formed only on a region containing a channel forming region on the (100) surface orientation.

Abstract: A universal semiconductor wafer for high-voltage semiconductor components includes at least one layer of a first conductivity type which is provided on a semiconductor substrate of the first conductivity type. A plurality of floating semiconductor zones of a second, opposite conductivity type are embedded in the interface region between the semiconductor substrate and the at least one layer. The floating semiconductor zones are dimensioned such that the dimension of a semiconductor zone is do small compared to the layer thickness of the at least one semiconductor layer and is essentially equal to or less than a distance between the floating semiconductor zones in the interface region.

Abstract: A high breakdown voltage semiconductor device includes a semiconductor layer, a drain offset diffusion region, a source diffusion region, a drain diffusion region, a buried diffusion region of a first conductivity type that is buried in the drain offset diffusion region, at least one plate electrode in a floating state formed on a field insulating film, and a metal electrode that is formed on an interlayer insulating film positioned on the plate electrode and a part of which is electrically connected to the drain diffusion region and that is capacitively coupled to the plate electrode.

Abstract: A semiconductor structure with greatly reduced backside chipping and cracking, as well as increased die strength, accommodation of compact assembly with a carrier such as another semiconductor chip, and resistance to package damage is provided by dicing chips from a wafer in a manner that chamfers edges of the chips. Similar advantages are obtained in multi-chip structure.

Abstract: A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive track extending above the substrate between the second region and the wall. The component includes a succession of trenches extending in the substrate under the track and perpendicularly to this track, each trench being filled with an insulator.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings in an implant and drive system. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or palladium contact layer. A thin high resistivity layer of amorphous silicon is deposited over the full upper surface of the wafer and is disposed between the wafer upper surface and all of the metal rings.

Abstract: High density MOS technology power device structure, including body regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, wherein the body regions include at least one plurality of substantially rectilinear and substantially parallel body stripes each joined at its ends to adjacent body stripes by junction regions, so that the at least one plurality of body stripes and the junction regions form a continuous, serpentine-shaped body region.

Abstract: A semiconductor device (102) comprises an N type semiconductor substrate (1). A P layer (22) is formed in a first surface (S1) of the semiconductor substrate (1), and a P layer (23) is formed in the semiconductor substrate (1) and in contact with the first surface (S1) and a second surface (S2) of the semiconductor substrate (1) corresponding to a beveled surface. The P layer (23) surrounds the P layer (22) in non-contacting relationship with the P layer (22). A separation distance (D) between the P layers (22, 23) is set at not greater than 50 &mgr;m. A distance (D23) between a third surface (S3) of the semiconductor substrate (1) and a portion of the P layer (23) which is closer to the third surface (S3) is less than a distance (D22) between the third surface (S3) and a portion of the P layer (22) which is closer to the third surface (S3).

Abstract: A FRED device having an ultralow Irr employs a contact layer which contacts spaced P diffusions in an N type silicon substrate and also contacts the silicon surface spanning between the P diffusions. The contact layer is formed of a contact having a lower barrier height than the conventional aluminum, and is palladium silicide with a top contact layer of aluminum.

Abstract: A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source electrode and the drain electrode and making a Schottky junction with the channel layer. The gate electrode is provided with an overhanging field plate section and between the field plate section and the channel layer, there is laid a dielectric film. When the relative permittivity and the film thickness of the dielectric film are denoted by ∈ and t (nm), respectively, the following condition is satisfied 5≦∈<8, and 100<t<350.

Abstract: A semiconductor device has an element region including MOS structure. A p-well region, a connecting impurity diffused region, and an impurity diffused region for guard ring are formed in an n-type semiconductor layer so as to form a well region, The well region has a step defining a higher portion and a lower portion lower than the higher portion so that the impurity diffused region for guard ring is located at the lower portion. The lower portion is located at a periphery of the element region. In this structure, the impurity diffused region for guard ring is completely depleted while the connecting impurity diffused region is partially depleted so that a portion having carriers remains therein while a depletion layer expands in the connecting impurity diffused region before a breakdown due to a reverse bias occurs in the element region.

Abstract: An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. A field-shield (FS) isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes the edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of prescribed region is smaller than a channel length at the central portion.

Abstract: A high voltage vertical conduction semiconductor device has a plurality of deep trenches or holes in a lightly doped body of one conductivity type. A diffusion of the other conductivity type is formed in the trench walls to a depth and a concentration which matches that of the body so that, under reverse blocking, both regions fully deplete. The elongated trench or hole is filled with a dielectric which may be a composite of nitride and oxide layers having a lateral dimension change matched to that of the silicon. The filler may also be a highly resistive SIPOS which permits leakage current flow from source to drain to ensure a uniform electric field distribution along the length of the trench during blocking.

Abstract: A power field effect transistor includes a bulge portion and/or a constricted portion in at least one of the heavily doped drain contact region and the lightly doped channel forming region, and heavily doped source regions are formed in the lightly doped channel forming region at intervals, wherein the avalanche breakdown takes place at the bulge portion and/or the constricted portion due to the concentration of electric field in the presence of excess voltage applied to the heavily doped drain contact region, and the breakdown current flows through the gaps between the heavily doped source regions so that a emitter-base junction of a parasitic bipolar transistor is not strongly biased.

Abstract: Walkout in high voltage trench isolated semiconductor devices is inhibited by applying a voltage bias signal directly to epitaxial silicon surrounding the device. Voltage applied to the surrounding epitaxial silicon elevates the initial breakdown voltage of the device and eliminates walkout. This is because voltage applied to the surrounding epitaxial silicon reduces the strength of the electric field between the silicon of the device and the surrounding silicon. Specifically, application of a positive voltage bias signal to surrounding epitaxial silicon equal to or more positive than the most positive potential occurring at the collector during normal operation of the device ensures that no walkout will occur.

Abstract: A cellular trench-gate field-effect transistor comprises a field plate (38) on dielectric material (28) in a perimeter trench (18). The dielectric material (28) forms a thicker dielectric layer than the gate dielectric layer (21) in the array trenches (11). The field plate (38) is connected to the source (3) or trench-gate (31) of the transistor and acts inwardly towards the cellular array rather than outwardly towards the body perimeter (15) because of its presence on the inside wall 18a of the trench (18) without acting on any outside wall (18b). The array and perimeter trenches (11,18) are sufficiently closely spaced, and the intermediate areas (4a, 4b) of the drain drift region (4) are sufficiently lowly doped, that the depletion layer (40) formed in the drain drift region (4) in the blocking state of the transistor depletes the whole of these intermediate areas between neighbouring trenches at a voltage less than the breakdown voltage.

Abstract: An open drain FET driver circuit at an input-output pad of a semiconductor chip and a frame of the same conductivity type as the drain and source diffusions of the driver is formed around the driver (or partly around the driver). The frame is connected to Vdd and forms the diffusion for the Vdd end of a field FET. The drain of the driver forms the diffusion for the pad end of this field FET and the pad to Vdd FET breaks down in response to an ESD voltage between the pad and Vdd and provides a path for ESD current that the open drain driver itself does not provide. Optionally, a second field FET is formed between the source of the driver FET and the frame and this FET conducts an ESD current between the pad and Vdd in series with the driver. With this cell array structure, the junction capacitance which the ESD protection devices contribute to the pad can be significantly reduced for high speed I/O applications.

Abstract: An optical semiconductor device includes a semiconductor substrate having an active layer, a semiconductor mesa stripe formed on the semiconductor substrate, a dummy mesa stripe formed on the semiconductor substrate, an insulating layer formed to fill up a gap between the semiconductor mesa stripe and the dummy mesa stripe, a main electrode formed on the semiconductor mesa stripe, and an extension electrode formed on top surfaces of the insulating layer and the dummy mesa stripe. The extension electrode is connected to the main electrode.

Abstract: A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped.

Abstract: Disclosed is a manufacturing method capable of easily manufacturing a semiconductor device exhibiting a high reliability but no decrease in a field isolation voltage due to an influence by overetching. Field oxide is formed on a silicon substrate by a LOCOS method. Polysilicon is deposited on the surface of the field oxide and on the surface of a silicon nitride layer formed on the silicon substrate when forming the field oxide layer. The polysilicon layer is deposited thicker than a thickness of the silicon nitride layer. The polysilicon layer deposited on the silicon nitride layer and on the field oxide is removed by polishing like a CMP method, whereby the surface of the silicon nitride layer is exposed. A structure having the polysilicon layer existing on only the surface of the field oxide is obtained by removing the silicon nitride layer. The polysilicon layer functions as a protective layer for the field oxide, thereby preventing the field oxide layer 34 from being etched when in overetching.

Abstract: Provided is an electrostatic discharge protection circuit according to the invention. In a drain between a gate and a contact plug which is electrically coupled to an input line, a plurality of shallow trench isolation regions are alternately formed in a shape of lattices for extending a current flow path and efficiently increasing a dissipation length. Therefore, a current caused by an electrostatic discharge can be uniformly distributed, so that the inventive electrostatic discharge protection circuit can have an enhanced protective capability.

Abstract: A high breakdown voltage HFET includes a reduced surface field (RESURF) layer of p-type conductivity GaN positioned on a substrate with a channel layer of n-type conductivity GaN positioned thereon. A barrier layer of n-type conductivity Al.sub.x Ga.sub.1-x N is positioned on the channel layer to form a lateral channel adjacent to and parallel with the interface. A gate electrode is positioned on the barrier layer overlying the lateral channel and a drain electrode is positioned on the channel layer in contact with the lateral channel and spaced to one side of the gate electrode a distance which determines the breakdown voltage. A source electrode is positioned on the channel layer to the opposite side of the gate electrode, in contact with the lateral channel and also in contact with the RESURF layer.

Abstract: A semiconductor device of SiC is adapted to hold high voltages in the blocking state thereof. The device comprises two parts (1, 2) each comprising one or more semiconductor layers of SiC and connected in series between two opposite terminals of the device, namely a sub-semiconductor device (1) able to withstand only low voltages in the blocking state thereof and a voltage-limiting part (2) able to withstand high voltages in the blocking state of the device and adapted to protect said sub-semiconductor device by taking a major part of the voltage over the device in the blocking state thereof.

Abstract: An interconnect in a microelectronic device is formed by forming a first mesa on a substrate. A first insulation layer is then formed on the substrate, the first insulation layer covering the first mesa to define a step at an edge thereof. A second mesa is formed on the first insulation layer adjacent the step, the second mesa being lower than the step. A second insulation layer is formed on the substrate, covering the second mesa and forming a step in the second insulation layer overlying the step in the first insulation layer. A spun-on-glass (SOG) layer on the second insulation layer, and then is planarized to expose a first portion of the second insulation layer at the step in the second insulation layer and to expose a second portion of the second insulation layer overlying the second mesa, thereby defining a planarized SOG region between the step and the second mesa.

Abstract: A semiconductor power device includes a high-resistance semiconductor substrate of the first conductivity type having first and second major surfaces and a recess in either one of the first and second major surfaces, and a semiconductor power element with a field relaxation structure, at least part of which is formed in a region of the semiconductor substrate where the recess is formed.

Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.

Abstract: A semiconductor component, which comprises a pn junction, where both the p-conducting and the n-conducting layers of the pn junction constitute doped silicon carbide layers and where the edge of at least one of the conducting layers of the pn junction, exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.

Abstract: A solar cell comprising multi-crystalline silicon or an alloy thereof, having a surface that is to receive light radiation, wherein said silicon surface includes a multi-tude of pits of depth lying in the range 0.10 .mu.m to 10 .mu.m and of diameter lying in the range 0.1 .mu.m to 10 .mu.m, and in which the ratio of said depth to said diameter is greater than 1, the area of said holes occupying more than half the area of said silicon surface.

Abstract: An edge termination structure is created by forming trench structures (14) near a PN junction. The presence of the trench structures (14) extends a depletion region (13) between a doped region (12) and a body of semiconductor material or a semiconductor substrate (11) of the opposite conductivity type away from the doped region (12). This in turn forces junction breakdown to occur in the semiconductor bulk, leading to enhancement of the breakdown voltage of a semiconductor device (10). A surface of the trench structures (14) is covered with a conductive layer (16) which keeps the surface of the trench structures (14) at an equal voltage potential. This creates an equipotential surface across each of the trench structures (14) and forces the depletion region to extend laterally along the surface of semiconductor substrate (11).

Abstract: To ensure bulk breakdown when the mesa diode with a positive bevel angle is reverse biased, the diffused region is formed with thinner edge portions. This eliminates corner or edge effects which create conditions of high electric field, resulting in decreased breakdown voltage and clamping voltage levels. The edges of the surface of epitaxial region are covered with a narrow oxide layer prior to diffusion. The middle portion of the surface remains uncovered. Diffusing through the oxide results in a diffused region which is thinner along the edges of the device than in the interior region below the exposed surface portion. The oxide thickness controls the depth of the edge diffusion.

Abstract: A lateral IGBT has a n-source layer and a p-contact layer both in contact with a source electrode. The source layer has a trunk adjacent to a channel region under a gate electrode, and a plurality of branches extending from its trunk to the source electrode to be in contact with the source electrode. The contact layer has a trunk in contact with the source electrode, and a plurality of branches extending from its trunk to the source layer trunk The source layer branches and the contact layer branches have shapes complementary with each other and are alternately arranged. The source layer trunk has a width La in an X direction (channel direction), which satisfies a condition, 0.5 .mu.m<La<2 .mu.m.

Abstract: Disclosed is a semiconductor device, comprising a substrate having a first region and a second region surrounding the first region, a MOS transistor formed in the first region, a first conductive layer formed in the first region and constituting the lower layer of a two-layered gate electrode of the MOS transistor, a second conductive layer for isolation, the second conductive layer being formed in the second region and having an upper surface whose level is lower than that of the upper surface of the first conductive layer, a first insulating layer formed between the first and second regions, a second insulating layer formed on the second conductive layer, and a third conductive layer formed over the first conductive layer and the second insulating layer and constituting the upper layer of the two-layered gate electrode of the MOS transistor.