High Power Or High Voltage Device Extends Completely Through Semiconductor Substrate (e.g., Backside Collector Contact) Patents (Class 257/502)
  • Patent number: 6570237
    Abstract: A semiconductor device forms a protective diode with a high breakdown voltage at a power terminal of a power IC. An N-type well is formed in a P-type semiconductor substrate, the well electrically connected to a power supply terminal. An N-type channel stopper region is formed in the well. A P-type substrate pickup region is formed outside the well. The distance between the substrate pickup region and the channel stopper region is adjusted such that the breakdown voltage of the parasitic diode is not lower than the rated voltage and not higher than the breakdown voltage of the high voltage PMOSFET fabricated in the well. The protective diode absorbs electrostatic breakdown and electrical noises without an additional circuit protection device or manufacturing process.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: May 27, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Akio Kitamura
  • Patent number: 6559505
    Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: May 6, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventor: Piero Fallica
  • Patent number: 6559515
    Abstract: An insulating wall of a second conductivity type intended for separating elementary components formed in different wells of a semiconductive layer of a first conductivity type, a component located in one at least one of the wells being capable of operating with a high current density. The insulating wall includes at least two elementary insulating walls separated by a portion of the wafer material and, in operation, this portion is connected to a reference potential.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: May 6, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Franck Duclos
  • Patent number: 6548874
    Abstract: An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: April 15, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Alec Morton, Taylor Efland, Chin-yu Tsai, Jozef C. Mitros, Dan M. Mosher, Sam Shichijo, Keith Kunz
  • Patent number: 6538294
    Abstract: An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and the highly doped layer is doped with the same type of dopant as the buried collector, but to a lower concentration. The sub-layer causes a more even distribution of the potential lines in the substrate and in a sub-collector layer, thereby eliminating areas of dense potential lines and increasing the breakdown voltage of the component, (i.e., because the breakdown voltage is lower in areas with dense potential lines).
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: March 25, 2003
    Assignee: Telefonaktiebolaget LM Ericson (publ)
    Inventors: Håkan Sjödin, Anders Söderbärg
  • Publication number: 20030047793
    Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.
    Type: Application
    Filed: May 30, 2002
    Publication date: March 13, 2003
    Applicant: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Patent number: 6528859
    Abstract: The present invention provides a foil wound low profile power L-C processor. A magnetic winding is disposed within a core. The magnetic winding can be made of one or more sets of conductive foil and insulation film wound together in a spiral pattern. The magnetic winding can also include dielectric film. The magnetic winding can have a center aperture in which a non-magnetic and non-conductive center post can be disposed. The center post can also be divided into portions with a combined length less than the length of the center aperture to form an air gap within the center aperture.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: March 4, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Willem G. Odendaal
  • Publication number: 20030020136
    Abstract: A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.
    Type: Application
    Filed: August 15, 2002
    Publication date: January 30, 2003
    Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
  • Patent number: 6507085
    Abstract: A semiconductor device is provided which minimizes a reduction in the breakdown voltage caused by a metal electrode to which a high voltage is applied. An n− semiconductor layer (3) is formed on a p− semiconductor substrate (1). A p+ impurity region (4) is formed within the n− semiconductor layer (3), extending from the surface of the n− semiconductor layer (3) to the interface of the n− semiconductor layer (3) and the p− semiconductor substrate (1). The p+ impurity region (4) is formed to surround part of the n− semiconductor layer (3) and forms a high-potential island region (101) where a logic circuit (103), an n+ impurity region (5) which is a cathode region of a bootstrap diode (102), and a p+ impurity region (6) which is an anode region are located.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: January 14, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuhiro Shimizu
  • Publication number: 20020171116
    Abstract: A power device includes a gate electrode, a source electrode, and a drain electrode provided within an active region of a semiconductor substrate of first conductivity type. A vertical diffusion region of second conductivity is provided at a periphery the active region. The vertical diffusion region extends continuously from a top surface of the substrate to a bottom surface of the substrate. The vertical diffusion region includes an upper portion having a first depth and a lower portion having a second depth that is substantially greater than the first depth.
    Type: Application
    Filed: March 13, 2002
    Publication date: November 21, 2002
    Applicant: IXYS Corporation
    Inventors: Ulrich Kelberlau, Peter Ingram, Nathan Zommer
  • Patent number: 6448630
    Abstract: A semiconductor device having a polish preventing pattern that can improve the planarity of an element formation region after the CMP method polishing is provided. To the shape of an element formation region, a loop-shaped element formation region dummy is formed in a uniform width and at a uniform distance from the edge of the element formation region to have a loop shape. That can prevent formation of such a portion that is on a line extended from a gap between polish preventing patterns as well as a large gap between an element formation region and a polish preventing pattern. Accordingly, local application of large pressure to an end of an element formation region is suppressed which is caused when a polishing cloth bends. As a result, the semiconductor device does not have a locally substantially etched portion. The planarity of the surface of an element formation region is maintained in the semiconductor device.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: September 10, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shigeki Komori
  • Publication number: 20020113286
    Abstract: A semiconductor device is provided which minimizes a reduction in the breakdown voltage caused by a metal electrode to which a high voltage is applied. An n− semiconductor layer (3) is formed on a p− semiconductor substrate (1). A p+ impurity region (4) is formed within the n− semiconductor layer (3), extending from the surface of the n− semiconductor layer (3) to the interface of the n− semiconductor layer (3) and the p− semiconductor substrate (1). The p+ impurity region (4) is formed to surround part of the n− semiconductor layer (3) and forms a high-potential island region (101) where a logic circuit (103), an n+ impurity region (5) which is a cathode region of a bootstrap diode (102), and a p+ impurity region (6) which is an anode region are located.
    Type: Application
    Filed: September 27, 2001
    Publication date: August 22, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Kazuhiro Shimizu
  • Publication number: 20020105054
    Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
    Type: Application
    Filed: March 6, 2002
    Publication date: August 8, 2002
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
  • Patent number: 6376919
    Abstract: A method of making circuit edit structures through the backside of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the backside. Next, a polyimide layer is vapor deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the polyimide layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited polyimide layer from the backside of the integrated circuit to couple together the circuit edit connection targets. The polyimide layer may acts as both an insulation layer and an anti-reflective coating layer.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: April 23, 2002
    Assignee: Intel Corporation
    Inventors: Jian Li, Paul Winer, Adam J. DeGrush, Steven P. Maher
  • Publication number: 20020041003
    Abstract: A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane (16) which has opposed top and bottom surfaces (15, 17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.
    Type: Application
    Filed: September 21, 2001
    Publication date: April 11, 2002
    Applicant: CAMBRIDGE SEMICONDUCTOR LIMITED
    Inventors: Florin Udrea, Gehan Amaratunga
  • Patent number: 6297549
    Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: October 2, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Michiaki Hiyoshi
  • Patent number: 6255710
    Abstract: An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material. The high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: July 3, 2001
    Assignee: Motorola, Inc.
    Inventors: Charles E. Weitzel, Nada El-Zein
  • Patent number: 6225673
    Abstract: An integrated circuit (13) includes a P-epi substrate (51) having first and second n+ isolation layers (53, 54) buried therein, the first and second isolation layers being respectively coupled to ground and to a supply voltage (VCC). A contact region (52) of the substrate is closely adjacent a first isolation layer, is spaced from the second isolation layer, and is coupled to ground. First and second P-epi portions (57, 58) of the substrate are disposed within the first and second isolation layers. The first portion includes an n+ source region (62) disposed in a p-well (61) which is closely adjacent the first isolation layer in the vicinity of the contact region, and includes an n+ drain region (68). The second portion includes an n+ source region (77) coupled to the drain region in the first portion, and an n+ drain region (82) coupled to the supply voltage.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: May 1, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Taylor R. Efland
  • Patent number: 6211549
    Abstract: A semiconductor device includes a first semiconductor element and a second semiconductor element, wherein the first semiconductor element of trench structure and the control circuit including the second semiconductor element such as a TFT or a bipolar transistor can be easily integrated by making the device structure such that the source layer of the buried gate electrode of the first semiconductor element and part of the second semiconductor element, such as the emitter or collector region, can be simultaneously formed.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: April 3, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Funaki, Akio Nakagawa
  • Patent number: 6194773
    Abstract: A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: February 27, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Satwinder Malhi
  • Patent number: 6091657
    Abstract: When flash memory devices are scaled down into the deep-submicron regime, tub erase is being increasingly deployed because it features lower erase current and better reliability performance than the conventional source-side erase scheme. However, tub erase requires higher voltages to be applied to the flash memory device. In a typical design, during tub erase 10 to 12 volts is applied to the tub, source and drain, and -6V is applied to the control gate of the flash memory device. However, in the state-of-the-art CMOS processes (usually used at a power supply voltage 3.3 V and below), it is difficult to build high voltage (HV) devices to support source/drain voltages of more than 6 volts unless the process complexity is significantly increased. Therefore, the required HV devices prevent tub erase from being widely used, especially for embedded applications.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: July 18, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Chun Chen, Richard Joseph McPartland
  • Patent number: 6084286
    Abstract: An integrated device comprises a high-voltage transistor and a low-voltage transistor in an emitter-switching configuration integrated in a chip (400) of semiconductor material comprising a buried P-type region (120) and a corresponding P-type contact region (405) which delimit a portion of semiconductor material within which the low-voltage transistor is formed. The contact region (405) has a network structure such as to divide this portion of semiconductor material into a plurality of cells (410) within each of which there is an elemental P-type base region (425) and an elemental N-type emitter region (430) of the low-voltage transistor. The elemental regions (425) and (430) of the various cells (410) are electrically connected to one another by means of surface metal contacts.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: July 4, 2000
    Assignee: SGS-Thomsom Microelectronics, S.r.l.
    Inventors: Natale Aiello, Vito Graziano, Atanasio La Barbera, Stefano Sueri
  • Patent number: 5994763
    Abstract: A wiring groove 5 and a via-hole 7 (9) is formed on the backside surface 3 of a semiconductor chip 1. A circuit electrode ER led from the circuit formed on the chip 1 and a boding pad BP, both of which are formed on the front surface of the semiconductor element, are electrically connected with each other with the help of a backside wiring formed in the wiring groove 5 and a penetration wiring 13 formed in the via-hole 7 (9). With such a wiring structure, it is made possible to form a wiring pattern using the wire having an adequate width, without increasing the size of the semiconductor chip 1.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: November 30, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kazuhiko Ohmuro
  • Patent number: 5982016
    Abstract: A monolithic component including, in an N-type lightly-doped substrate of a semiconductor wafer, two portions separated by a P-type insulating wall. A first portion of the two portions includes a high voltage lateral component, a layer of which substantially corresponds to the thickness of the wafer. The second portion includes logic circuit components. A rear surface of the substrate includes a P-type layer coated with a metallization. The insulating wall is in electrical contact with a low voltage terminal of the high voltage lateral component, such as the gate region of a thyristor. The logic portion includes at least one vertical component.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: November 9, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Robert Pezzani, Eric Bernier
  • Patent number: 5841197
    Abstract: A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: November 24, 1998
    Inventor: Fred W. Adamic, Jr.
  • Patent number: 5811854
    Abstract: A composite semiconductor device comprised of a power MOS FET and a low level signal element. The MOS FET includes an n type buried layer embedded between p type substrate and n type epitaxial layer. As conventionally formed due to the pn junctions between the p substrate and the n epitaxial layer, and between the p substrate and the n buried layer, the depletion layers had abrupt transitions therebetween, inviting field concentrations and consequent voltage drops. In order to mitigate the abrupt transitions, one or more n type additional buried regions are provided in and between the substrate and the epitaxial layer and in the adjacency of the buried layer. The additional buried regions are higher in impurity concentration than the epitaxial layer.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: September 22, 1998
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Akio Iwabuchi, Kazuyoshi Sugita
  • Patent number: 5811868
    Abstract: An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance.Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: September 22, 1998
    Assignee: International Business Machines Corp.
    Inventors: Claude Louis Bertin, Wayne John Howell, William Robert Patrick Tonti, Jerzy Maria Zalesnski
  • Patent number: 5767578
    Abstract: An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: June 16, 1998
    Assignee: Siliconix incorporated
    Inventors: Mike F. Chang, King Owyang, Fwu-Iuan Hshieh, Yueh-Se Ho, Jowei Dun, Hans-Jurgen Fusser, Reinhard Zachai
  • Patent number: 5757081
    Abstract: An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: May 26, 1998
    Assignee: Siliconix Incorporated
    Inventors: Mike F. Chang, King Owyang, Fwu-Iuan Hshieh, Yueh-Se Ho, Jowei Dun
  • Patent number: 5753962
    Abstract: A method of forming field oxide during the manufacture of a semiconductor device comprises the steps of providing a semiconductor wafer having a plurality of recesses or trenches therein. A layer of texturized polycrystalline silicon is formed within the recesses, which is subsequently oxidized to form field oxide. The instant method reduces stress imparted to the die as the texturized polycrystalline silicon has voids or holes which absorb the expanding volume as the silicon is oxidized to form field oxide.
    Type: Grant
    Filed: September 16, 1996
    Date of Patent: May 19, 1998
    Assignee: Micron Technology, Inc.
    Inventor: Nanseng Jeng
  • Patent number: 5723895
    Abstract: A field effect semiconductor device includes a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type provided above the first semiconductor region. A dielectric film is interposed between the first semiconductor region and the second semiconductor region to surround the second semiconductor region and to have at least one opening portion for connecting the second semiconductor region to the first semiconductor region. A field effect transistor is provided, in which a source region is provided in a surface portion of the second semiconductor region and connected to a source electrode and a drain region is provided in the surface portion of the second semiconductor region and connected to a drain electrode. A gate electrode provided between the source region and the drain region to form a channel region.
    Type: Grant
    Filed: October 2, 1996
    Date of Patent: March 3, 1998
    Assignee: NEC Corporation
    Inventor: Kenichiro Takahashi
  • Patent number: 5606195
    Abstract: A high-voltage bipolar transistor and fabrication method that comprises a shield electrode (or field-termination electrode) located between bond pads and underlying semiconductor material. The shield electrode is sandwiched between two isolating dielectric layers. High-voltage applied to the bond pad establishes an electric field between the bond pad and the shield electrode), preventing field penetration into and inversion of the underlying semiconductor material. Using this overlapping field-termination structure, low leakage current and high breakdown voltage is maintained in the transistor. The present overlapping field-termination structure provides an effective field termination underneath the bond pads, and because of its overlapping design, provides for a more compact transistor.
    Type: Grant
    Filed: December 26, 1995
    Date of Patent: February 25, 1997
    Assignee: Hughes Electronics
    Inventors: William W. Hooper, Michael G. Case, Chanh N. Nguyen
  • Patent number: 5602416
    Abstract: A PIC structure comprises a lightly doped semiconductor layer of a first conductivity type, superimposed over a heavily doped semiconductor substrate of the first conductivity type, wherein a power stage and a driving and control circuitry including first conductivity type-channel MOSFETs and second conductivity type-channel MOSFETs are integrated; the first conductivity type-channel and the second conductivity type-channel MOSFETs are provided inside second conductivity type and first conductivity type well regions, respectively, which are included in at least one isolated lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolation region of a second conductivity type.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: February 11, 1997
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventor: Raffaele Zambrano
  • Patent number: 5565701
    Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.
    Type: Grant
    Filed: July 2, 1992
    Date of Patent: October 15, 1996
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventor: Raffaele Zambrano
  • Patent number: 5521414
    Abstract: A structure of an electronic device having a predetermined unidirectional conduction threshold is formed on a chip of an N-type semiconductor material and includes a plurality of isolated N-type regions. Each isolated N-type region is bounded laterally by an isolating region and at the bottom by buried P-type and N-type regions which form in combination a junction with a predetermined reverse conduction threshold and means of connecting the junctions of the various isolated regions serially together. The buried N-type region of the first junction in the series is connected to a common electrode, which also is one terminal of the device, over an internal path of the N-type material of the chip, and the buried P-type region of the last junction in the series contains an additional buried N-type region which is connected electrically to a second terminal of the device.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: May 28, 1996
    Assignee: SGS-Thomson Microelectronics s.r.l.
    Inventor: Sergio Palara
  • Patent number: 5500551
    Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: March 19, 1996
    Assignees: SGS-Thomson Microelectronics, S.r.l., Consorzio per la Ricerca Sulla Microelettronica nel Mezzogiorro
    Inventors: Santo Puzzolo, Raffaele Zambrano, Mario Paparo
  • Patent number: 5473181
    Abstract: In an integrated circuit arrangement having at least one power component and low-voltage components, the at least one power component is realized in a semiconductor substrate. At least one contact of the power component is arranged on a principal surface of the substrate. The contact is covered with an insulation layer at a surface of which at least one thin-film component, particularly a thin-film transistor, is provided above the contact.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: December 5, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Udo Schwalke, Michael Stoisiek
  • Patent number: 5444289
    Abstract: A method is provided for making a power device (54) and a small signal device (52) on a bonded silicon substrate (41). A first silicon substrate (10) provided. A first surface (17) is etched to form a plurality of cavities (11) with a depth (13). A dielectric layer (14) is created on the first surface (17), wherein the dielectric layer (14) is created with a thickness less than or equal to the depth of the plurality of cavities. The dielectric layer (14) is patterned so that a plurality of islands (22) of dielectric remain in the cavities. A second silicon substrate (42) is provided. The first and the second silicon substrates (10, 42) are bonded together in such a manner that the islands (22) are buried. A predetermined portion of the first silicon substrate (10) is removed, thereby creating a surface that is suitable for semiconductor device fabrication.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: August 22, 1995
    Assignee: Motorola
    Inventors: Bertrand F. Cambou, Donald L. Hughes
  • Patent number: 5436173
    Abstract: A method for forming a semiconductor on insulator device is provided that begins with an outer semiconductor layer (16). Trenches (12) of a predetermined depth are formed in outer semiconductor layer (16). An insulator layer (20) is formed outwardly from outer semiconductor layer (16). A mesa (18a) having a predetermined thickness is formed by removing portions of outer semiconductor layer (16) to expose a working surface such that mesa (18a) has a thickness substantially equal to the predetermined depth of the trenches (12) after the working surface is exposed.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 5432376
    Abstract: The base region of the power stage and the horizontal isolation region of the integrated control circuit or collector region of a transistor of an integrated circuit consist of portions of an epitaxial layer with a first conductivity type grown in sequence on an underlying epitaxial layer with a second conductivity type opposite the first.
    Type: Grant
    Filed: April 16, 1992
    Date of Patent: July 11, 1995
    Assignee: Consorzio per la Ricera Sulla Microelettronica Nel Mezzogiorno
    Inventor: Raffaele Zambrano
  • Patent number: 5416354
    Abstract: A semiconductor device is disclosed having improved vertical gain symmetry, and which includes thick, lightly-doped regions which are dielectrically isolated and provided by at least two separately processed semiconductor wafers which are bonded together and further processed to provide the finished device. Alternate embodiments include buried layers exhibiting very low resistance. Further alternate embodiments provide high voltage and/or high current devices which are fabricated together with low-power circuitry as an integrated circuit.
    Type: Grant
    Filed: January 3, 1994
    Date of Patent: May 16, 1995
    Assignee: Unitrode Corporation
    Inventor: Scott C. Blackstone
  • Patent number: 5382821
    Abstract: There is disclosed an FET having a high drain breakdown voltage and a short gate length comprising an active layer 2 formed on a surface layer of a semiconductor substrate 1; a highly doped impurity source region 4 and highly doped impurity drain region 4 formed in the surface layer of the semiconductor substrate 1 to sandwich the active layer 2; an insulation film 5 formed on the highly doped impurity source region 4; a gate electrode 8 formed on the active layer 2 and the insulation film 5 while maintaining a constant distance 1.sub.GD from the highly doped impurity drain region 4; and a source electrode 6 and a drain electrode 7 formed on the highly doped impurity source region 4 and the highly doped impurity drain region 4, respectively.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: January 17, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shigeru Nakajima
  • Patent number: 5376821
    Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N-epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: December 27, 1994
    Assignees: SGS-Thomson Microelectronics, S.r.l., Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno
    Inventors: Santo Puzzolo, Raffaele Zambrano, Mario Paparo
  • Patent number: 5317182
    Abstract: A smart power integrated circuit, in which the power stage includes a vertical-current-flow NMOS power transistor having many paralleled cells. A deeper P-type diffusion surrounds the P-type body region of the cells at the edge of the power stage. The junction between this deep P-type diffusion and the laterally adjacent N-type material has a lower curvature than the junction which would be formed by the P-type body region alone. This increases the transistor's breakdown voltage without degrading the transistor's on-state resistance R.sub.on.
    Type: Grant
    Filed: May 29, 1991
    Date of Patent: May 31, 1994
    Assignee: Consorzio Per la Ricerca Sulla Microelectronica
    Inventors: Raffaele Zambrano, Antonio Grimaldi
  • Patent number: 5245211
    Abstract: A device accomplishes protection against breakdown of an N+ type diffused region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffused region (6). The diffused region (6) is insulated electrically with respect to the P type containment region (5).
    Type: Grant
    Filed: October 30, 1990
    Date of Patent: September 14, 1993
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Mario Paparo, Sergio Palara
  • Patent number: 5243207
    Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: September 7, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Donald L. Plumton, Francis J. Morris, Jau-Yuann Yang
  • Patent number: 4909960
    Abstract: A semiconductive resin composition comprising 100 parts by weight of a polymer component comprising an ethylene-based copolymer, an ethylene-propylene rubber, and a low molecular weight polyethylene having an average molecular weight of 1,000 to 4,000 and 40 parts by weight or more of electroconductive carbon black.
    Type: Grant
    Filed: September 27, 1988
    Date of Patent: March 20, 1990
    Assignee: Hitachi Cable Ltd.
    Inventors: Kiyoshi Watanabe, Toshio Shiina, Yukio Shimazaki, Hideki Yagyu, Katsutoshi Hanawa, Moritada Marumo