With Metallic Conductor Within Isolating Dielectric Or Between Semiconductor And Isolating Dielectric (e.g., Metal Shield Layer Or Internal Connection Layer) Patents (Class 257/508)
  • Publication number: 20120273918
    Abstract: A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics.
    Type: Application
    Filed: January 10, 2012
    Publication date: November 1, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Tae O Jung
  • Patent number: 8299506
    Abstract: A method of forming CMOS circuitry integrated with MEMS devices includes bonding a wafer to a top surface layer having contacts formed to CMOS circuitry. A handle wafer is then removed from one of the top or bottom surfaces of the CMOS circuitry, and MEMS devices are formed in a remaining silicon layer.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: October 30, 2012
    Assignee: Honeywell International Inc.
    Inventors: Andy Peczalski, Robert E. Higashi, Gordon Alan Shaw, Thomas Keyser
  • Publication number: 20120242400
    Abstract: A high-voltage MEMS system compatible with low-voltage semiconductor process technology is disclosed. The system comprises a MEMS device coupled to a high-voltage bias generator employing an extended-voltage isolation residing in a semiconductor technology substrate. The system avoids the use of high-voltage transistors so that special high-voltage processing steps are not required of the semiconductor technology, thereby reducing process cost and complexity. MEMS testing capability is addressed with a self-test circuit allowing modulation of the bias voltage and current so that a need for external high-voltage connections and associated electro-static discharge protection circuitry are also avoided.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: INVENSENSE, INC.
    Inventors: Derek SHAEFFER, Baris CAGDASER, Joseph SEEGER
  • Patent number: 8264059
    Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: September 11, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee
  • Publication number: 20120217612
    Abstract: A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter Baars, Till Schloesser
  • Publication number: 20120217611
    Abstract: An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap.
    Type: Application
    Filed: February 24, 2011
    Publication date: August 30, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hung LIU, Ku-Feng YANG, Pei-Ching KUO, Ming-Tsu CHUNG, Hsin-Yu CHEN, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Patent number: 8247965
    Abstract: An object of the invention is to provide a display device which can be manufactured with usability of a material improved and with a manufacturing step simplified and to provide a manufacturing technique thereof. One feature of a light emitting display device of the present invention is to comprise a gate electrode formed over a substrate having an insulating surface with a substance having a photocatalytic function therebetween, a gate insulating layer formed over the gate electrode, a semiconductor layer and a first electrode formed over the gate insulating layer, a wiring layer formed over the semiconductor layer, a partition wall covering an edge portion of the first electrode and the wiring layer, an electroluminescent layer over the first electrode, and a second electrode over the electroluminescent layer, wherein the wiring layer covers the edge portion of the first electrode.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Osamu Nakamura
  • Patent number: 8247883
    Abstract: An embodiment is a method and apparatus to construct a shielded cable, wire, or circuit. A first insulator layer is deposited on a first conductor or semiconductor layer. A second conductor or semiconductor layer is deposited on the first insulator layer. A second insulator layer is deposited on the first insulator layer. The second insulator layer covers the second conductor or semiconductor layer and defines a shielded region. A third conductor or semiconductor layer is deposited on the first conductor or semiconductor layer. The third conductor or semiconductor layer covers the first and second insulator layers. At least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: August 21, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Tse Nga Ng
  • Publication number: 20120205776
    Abstract: The invention relates to a semiconductor structures and methods of manufacture and, more particularly, to a dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture. In a first aspect of the invention, a method comprises forming a trench in a substrate; forming a first insulator layer within the trench; forming a first electrode within the trench, on the first insulator layer, and isolated from the substrate by the first insulator layer; forming a second insulator layer within the trench and on the first electrode; and forming a second electrode within the trench, on the second insulator layer, and isolated from the substrate by the first insulator layer and the second insulator layer.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy W. KEMERER, James S. NAKOS, Steven M. SHANK
  • Publication number: 20120205777
    Abstract: A semiconductor device includes a trench formed in a substrate and defining a plurality of active regions, a punch-through prevention layer filling a part of the trench and coupled to a ground, and an isolation layer formed over the punch-through prevention layer and filling the other part of the trench.
    Type: Application
    Filed: December 28, 2011
    Publication date: August 16, 2012
    Inventor: Sang-Hyun LEE
  • Patent number: 8242586
    Abstract: An integrated circuit chip includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and an inner seal ring, wherein the inner seal ring comprises a gap that is situated in front of the analog and/or RF circuit block.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 14, 2012
    Assignee: Mediatek Inc.
    Inventors: Tien-Chang Chang, Shi-Bai Chen, Tao Cheng, Yu-Hua Huang
  • Patent number: 8242541
    Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Sasaki, Yasuto Igarashi, Naozumi Morino
  • Patent number: 8237285
    Abstract: Semiconductor device includes semiconductor substrate, through hole having first opening and second opening, and including an expansion portion so that an opening area of first opening is greater than an opening area of lowermost portion of expansion portion, first insulating layer, and having an opening which communicates with through hole and has an area smaller than opening area of first opening, first wiring layer provided on first insulating layer, second insulating layer provided on expansion portion of through hole, and to cover first opening and an inner wall surface of through hole, second insulating layer having an opening communicating with opening of first insulating layer so as to expose first wiring layer through opening of first insulating layer, and second wiring layer provided on second insulating layer to extend from inside of through hole, and being connected to first wiring layer via openings of first and second insulating layers.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Mie Matsuo, Masahiro Sekiguchi, Chiaki Takubo
  • Patent number: 8227889
    Abstract: A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed on the substrate, and the TSV penetrates through the substrate. The shelter is disposed on the substrate and at least one part thereof is between the circuit area and the TSV in order to shelter EMI between the TSV and the circuit area. The novel structure prevents the circuits in the circuit area being affected by noise caused by TSV when TSV acts as a power pin.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: July 24, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Chien-Li Kuo
  • Patent number: 8227892
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 24, 2012
    Assignee: Broadcom Corporation
    Inventor: James Y. C. Chang
  • Publication number: 20120175727
    Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 12, 2012
    Inventors: Geeng-Lih Lin, Kwang-Ming Lin, Shang-Hui Tu, Jui-Chun Chang
  • Publication number: 20120175728
    Abstract: A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.
    Type: Application
    Filed: January 11, 2011
    Publication date: July 12, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Jung YANG, Yu-Wen LIU, Michael Shou-Ming TONG, Hsien-Wei CHEN, Chung-Ying YANG, Tsung-Yuan YU
  • Patent number: 8212331
    Abstract: According to an exemplary embodiment, a method for fabricating a backside through-wafer via in a processed wafer includes forming a through-wafer via opening through a substrate and extending the through-wafer via opening through at least one interlayer dielectric layer situated over the substrate. The method further includes forming a metal layer in the through-wafer via opening, where the metal layer forms an electrical connection to substrate. The metal layer is also in electrical contact with an interconnect metal segment situated above the at least one interlayer dielectric layer. The method further includes performing a thinning process to reduce the substrate to a target thickness before forming the through-wafer via opening. The method further includes forming an electrically conductive passivation layer on the metal layer and over a bottom surface of the substrate, where the electrically conductive passivation layer is in electrical contact with the metal layer and the substrate.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: July 3, 2012
    Assignee: Newport Fab, LLC
    Inventors: Arjun Kar-Roy, Marco Racanelli, David J. Howard
  • Patent number: 8212332
    Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
  • Publication number: 20120153431
    Abstract: Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
    Type: Application
    Filed: February 28, 2012
    Publication date: June 21, 2012
    Applicant: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Herbert L. Ho, Edward J. Nowak
  • Publication number: 20120153430
    Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 21, 2012
    Applicant: LSI Corporation
    Inventors: Mark A. Bachman, Sailesh M. Merchant, John Osenbach
  • Patent number: 8193603
    Abstract: A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor. As a result, both semiconductor resistors and MIM capacitors can be formed in the same process flow.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: June 5, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey Klatt
  • Patent number: 8188565
    Abstract: A semiconductor chip including a substrate, a metal interconnection structure and a circuit region is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring, wherein the guard ring comprises a plurality of individual segments, and the individual segments are individually and electrically coupled to the ground contacts. The circuit region disposed on the substrate. A projection of the dielectric ring on the substrate surface surrounds a projection of the circuit region on the substrate surface, and the projection of the guard ring on the substrate surface surrounds that of the dielectric ring and that of the circuit region on the substrate surface.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: May 29, 2012
    Assignee: VIA Technologies, Inc.
    Inventor: Sheng-Yuan Lee
  • Publication number: 20120119325
    Abstract: A device may comprise a substrate formed of a first semiconductor material, a first trench formed in the substrate, a second trench formed in the substrate proximate the first trench, an oxide layer formed in the first trench and the second trench, and a second semiconductor material formed upon the oxide layer. The oxide layer in the second trench may be adapted to mitigate undercut of the oxide layer in the first trench during an etching process.
    Type: Application
    Filed: November 15, 2010
    Publication date: May 17, 2012
    Applicant: Tessera MEMS Technologies, Inc.
    Inventors: Ankur Jain, Robert J. Calvet, Roman C. Gutierrez
  • Publication number: 20120119324
    Abstract: A device may comprise a substrate formed of a first semiconductor material and a trench formed in the substrate. A second semiconductor material may be formed in the trench. The second semiconductor material may have first and second portions that are isolated with respect to one another and that are isolated with respect to the first semiconductor material.
    Type: Application
    Filed: November 15, 2010
    Publication date: May 17, 2012
    Applicant: Tessera MEMS Technologies, Inc.
    Inventors: Ankur Jain, Roman C. Gutierrez, Shi-Sheng Lee, Robert J. Calvet, Xiaolei Liu
  • Patent number: 8178921
    Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: May 15, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Sang Tae Ahn, Seok Pyo Song, Hyeon Ju An
  • Publication number: 20120112268
    Abstract: The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.
    Type: Application
    Filed: March 1, 2011
    Publication date: May 10, 2012
    Inventors: Sung-Shan Tai, Hung-Sheng Tsai
  • Publication number: 20120104541
    Abstract: The present disclosure provides a semiconductor device, including a substrate having a seal ring region and a circuit region, a seal ring structure disposed over the seal ring region, a first passivation layer disposed over the seal ring structure, the first passivation layer having a first passivation layer aperture over the seal ring structure, and a metal pad disposed over the first passivation layer, the metal pad coupled to the seal ring structure through the first passivation layer aperture and having a metal pad aperture above the first passivation layer aperture. The device further includes a second passivation layer disposed over the metal pad, the second passivation layer having a second passivation layer aperture above the metal pad aperture, and a polyimide layer disposed over the second passivation layer, the polyimide layer filling the second passivation layer aperture to form a polyimide root at an exterior tapered edge of the polyimide layer.
    Type: Application
    Filed: November 3, 2010
    Publication date: May 3, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tzu-Wei Chiu
  • Publication number: 20120104542
    Abstract: The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface.
    Type: Application
    Filed: January 26, 2011
    Publication date: May 3, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 8171441
    Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: May 1, 2012
    Assignee: Synopsys, Inc.
    Inventors: Kenneth S. McElvain, William Halpin
  • Patent number: 8169059
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Oliver Nagy
  • Patent number: 8166434
    Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: April 24, 2012
    Assignee: Synopsys, Inc.
    Inventors: Kenneth S. McElvain, William Halpin
  • Patent number: 8164132
    Abstract: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: April 24, 2012
    Assignee: Round Rock Research, LLC
    Inventor: H. Montgomery Manning
  • Patent number: 8161442
    Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: April 17, 2012
    Assignee: Synopsys, Inc.
    Inventors: Kenneth S. McElvain, William Halpin
  • Publication number: 20120086098
    Abstract: There has been very little (if any) attention to address contamination diffusion within an integrated circuit (IC) because there are very few applications where a protective overcoat will be penetrated as part of the manufacturing process. Here, a sealing ring is provided that address this problem. Preferably, the sealing ring uses the combination of electrically conductive barrier rings and the tortuous migration path to allow an electronic device (i.e., thermopile), where a protective overcoat is penetrated during manufacture, to communicate with external devices while being isolated to prevent contamination.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 12, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Walter Meinel, Kalin V. Lazarov
  • Publication number: 20120074519
    Abstract: An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.
    Type: Application
    Filed: September 26, 2011
    Publication date: March 29, 2012
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Alfred Yeo, Kai Chong Chan
  • Publication number: 20120049318
    Abstract: To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 ?m. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.
    Type: Application
    Filed: August 11, 2011
    Publication date: March 1, 2012
    Inventors: Tatsuya Kawamata, Atsushi Tachigami, Kazuya Horie, Tatsuya Shiromoto, Tetsuya Nitta, Hironori Shimizu
  • Patent number: 8125046
    Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: February 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Karl-Heinz Mueller, Bernhard Winkler, Robert Gruenberger
  • Patent number: 8122412
    Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: February 21, 2012
    Assignee: Synopsys, Inc.
    Inventors: Kenneth S. McElvain, William Halpin
  • Publication number: 20120018840
    Abstract: Disclosed are an element isolation structure of a semiconductor device and a method for forming the same, the method including preparing a semiconductor substrate having an inactive region and an active region defined thereon, forming a first hard mask on the semiconductor substrate, exposing the inactive region of the semiconductor substrate by patterning the first hard mask, forming a second hard mask on the entire surface of the semiconductor substrate including the first hard mask, forming a deep trench in the semiconductor substrate by patterning the second hard mask and the semiconductor substrate, removing the patterned second hard mask, forming a shallow trench overlapped with the deep trench by patterning the semiconductor substrate using the first hard mask as a mask, forming an insulation film on the entire surface of the substrate including the shallow trench and the deep trench, filling the shallow trench and the deep trench by forming an element isolation film on the insulation film, and forming
    Type: Application
    Filed: March 2, 2011
    Publication date: January 26, 2012
    Inventor: Yang-Beom Kang
  • Patent number: 8102010
    Abstract: A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third substrate is formed on the second substrate; and the metal element is formed on the third substrate. The second substrate is electrically grounded and is highly doped with acceptor dopant as compared to the first substrate. In this way, the second resistivity is lower than the first resistivity.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: January 24, 2012
    Assignee: Broadcom Corporation
    Inventor: Hung-Ming Chien
  • Publication number: 20120007176
    Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Christoph KADOW, Thorsten MEYER, Norbert KRISCHKE
  • Publication number: 20120007211
    Abstract: The present disclosure relates to the field of microelectronic die packaging, particularly multi-chip packaging, wherein on-substrate modularity is enabled by using in-street die-to-die interconnects to facilitate signal routing between microelectronic dice. These in-street die-to-die interconnects may allow for manufacturing of several products on a single microelectronic substrate, which may lead to improved microelectronic die and/or microelectronic module harvesting and increased product yields.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 12, 2012
    Inventors: Aleksandar Aleksov, Arnab Sarkar, Henning Braunisch, Jerry R. Bautista
  • Patent number: 8093677
    Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: January 10, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Matthias Stecher, Hans-Joachim Schulze, Thomas Neidhart
  • Patent number: 8093645
    Abstract: A non-volatile semiconductor memory device includes a plurality of memory cell regions including a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a first insulating film formed in a region between any two adjacent bit lines, a bit line contact region including bit line contacts connected to the plurality of bit lines, a first UV light shielding film covering at least a portion of the semiconductor substrate in the bit line contact region, an interlayer insulating film, and a second UV light shielding film covering the plurality of memory cell regions. The first UV light shielding film effectively reduces or blocks UV light generated during a fabrication step.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: January 10, 2012
    Assignee: Panasonic Corporation
    Inventor: Yukihiro Yamashita
  • Patent number: 8089129
    Abstract: Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: January 3, 2012
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Donald R. Disney, Richard K. Williams
  • Patent number: 8084839
    Abstract: A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive shield member surrounding at least a portion of the conductive connector. The shield member prevents distortion of a data signal applied to the conductive connector, and also intercepts electromagnetic waves generated by the conductive connector.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: December 27, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Bok Kyu Choi, Sang Joon Lim, Eul Chul Jang
  • Publication number: 20110309468
    Abstract: A semiconductor chip package includes a substrate, a first layer disposed on the substrate and a second layer substantially similar to and disposed on the first layer. The first layer has a first input/output (I/O) circuit, a first through-via connected to the first input/output (I/O) circuit and a second through-via that is not connected to the first I/O circuit. The second layer has a second I/O circuit, a third through-via connected to the second I/O circuit and a fourth through-via that is not connected to the second I/O circuit. The first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. The package maybe fabricated by stacking the layers, and changing the orientation of the second layer relative to the first to ensure that the first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via.
    Type: Application
    Filed: April 18, 2011
    Publication date: December 22, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-young Oh, Kwang-il Park, Seung-jun Bae, Yun-seok Yang, Young-soo Sohn, Si-hong Kim
  • Patent number: 8076730
    Abstract: System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first poly-silicon layer. The semiconductor device further includes a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second poly-silicon layer. An electrical connection connects the first semiconductor device with the second semiconductor device and overlies the first active area, the second active area and a portion of the substrate between the first active area and the second active area.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: December 13, 2011
    Assignee: Infineon Technologies AG
    Inventors: Martin Ostermayr, Chandraserhar Sarma
  • Patent number: 8074197
    Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: December 6, 2011
    Assignee: Synopsys, Inc.
    Inventors: Kenneth S. McElvain, William Halpin