Abstract: An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.

Abstract: Generally provided is a circuit assembly construction for controlling impedance in an electronic package. A large scale, parallel-plate capacitor includes two electrodes separated by a dielectric material. The electrodes serve as reference voltage planes for the electronic package. At least one of the electrodes is patterned such that both electrodes are accessible from a common side of the capacitor. The capacitor is positioned with a first electrode mounted adjacent to an interconnect circuit portion of the electronic package. An electronic device portion of the electronic package is electrically connected, directly or indirectly, to one or more of the electrodes of the capacitor.

Abstract: A capacitor including a polysilicon layer doped with impurities to be conductive, a first dielectric layer formed on the polysilicon layer, a first conductive layer formed on the first dielectric layer, a second dielectric layer formed on the first conductive layer, and a second conductive layer formed on the first dielectric layer. The second conductive layer is coupled to the polysilicon layer.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.

Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: In a capacitor device of the present invention, a capacitor parts that has a pair of terminals on both end sides respectively is embedded in an insulating film in a state that a lower surface of the capacitor parts is not covered with the insulating film, then upper wiring patterns that are connected to upper surfaces of a pair of terminals via holes formed in the insulating film on a pair of terminals are formed on an upper surface side of the insulating film respectively, and then lower wiring patterns that are connected to lower surfaces of a pair of terminals are formed on a lower surface side of the insulating film respectively.

Abstract: The specification describes flip bonded dual substrate inductors wherein a portion of the inductor is constructed on a base IPD substrate, a mating portion of the inductor is constructed on a cover (second) substrate. The cover substrate is then flip bonded to the base substrate, thus mating the two portions of the inductor. Using this approach, a two level inductor can be constructed without using a multilevel substrate. Using two two-level substrates yields a four-level flip bonded dual substrate inductor.

Abstract: A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof.

Abstract: An electrical fuse has a substrate and a resistor. The resistor has a first area and a second area embedded in the first area. The first area is formed of a first material and the second area is formed of a second material having a lower thermal stability than that of the first material. Because of the different thermal stabilities, the second area is more likely to rupture when a programming voltage is applied. The eFuse provides increased reliability and enables lower programming voltages to be used.

Abstract: The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an auxiliary structure is arranged on the substrate adjacent to the useful structure, the auxiliary structure having an auxiliary structure side edge, wherein the useful structure side edge is opposite to the auxiliary structure side edge separated by a distance, and wherein the auxiliary structure useful structure distance is dimensioned such that a form of the useful structure side edge or a form of the substrate next to the useful structure side edge differs from a form in a device where there is no auxiliary structure.

Abstract: A dielectric thin film 8, comprising a first bismuth layer-structured compound layer 8a expressed by a composition formula of (Bi2O2)2+(Am?1 Bm O3m+1)2? or Bi2 Am?1 Bm O3m+3, wherein “m” is a positive number, “A” is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and “B” is at least one element selected from Fe, Co, Cr, Ga, Ti, Nb, Ta, Sb, V, Mo and W. Between the first bismuth layer-structured compound layer 8a and a lower portion electrode 6, a second bismuth layer-structured compound layer 8b including bismuth in excess of that in the composition formula of said first bismuth layer-structured compound layer 8a.

Abstract: Disclosed herein is a parallel capacitor of a semiconductor device. According to the present invention, a first capacitor and a second capacitor are formed in different layers of the same region, wherein a metal layer connected to an upper electrode of the first capacitor is formed in the same layer as a metal layer connected to a lower electrode of the second capacitor. Thus, twp capacitors can be connected in parallel only with a metal layer composed of three layers. Accordingly, the present invention is advantageous in that it can reduce process steps for forming multiple metal layers, lower a step and cut manufacture cost.

Abstract: In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.

Abstract: A semiconductor device includes an upper conductive strip group and a lower conductive strip group crossing under the upper conductive strip group. Adjacent first and second conductive strips of the upper conductive strip group are adapted to receive a first voltage, a third conductive strip of the lower conductive strip group is adapted to receive a second voltage. A capacitor is provided at a first intersection between the first and third conductive strips and at a second intersection between the second and third conductive strip, and the capacitor extends from the first intersection to the second intersection.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A capacitor includes a first electrode, an insulating film and a second electrode. The insulating film includes n layers of barrier layers each consisting of a material having a bandgap larger than a first bandgap and having a relative permittivity smaller than a first relative permittivity, and (n?1) layers of well layers each consisting of a material having a bandgap smaller than the first bandgap and having a relative permittivity larger than the first relative permittivity. The barrier layers and the well layers are stacked by turns. Discrete energy levels are formed in each of the well layers by a quantum effect. Thicknesses of the n layers of the barrier layers are not smaller than 2.5 angstroms. A thickness dm (angstrom) and a relative permittivity ?m of an m-th barrier layer satisfying the condition: 2.5 >(d1/?1+d2/?2+. . . +dn/?n).

Abstract: A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the second metal layer. The first metal layer has a first terminal and a second terminal. The first terminal is electrically isolated from the second terminal.

Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a first electrode (2, 3, 5). This auxiliary layer (6) is then opened up (15) via the first electrode. Then, a dielectric layer (7) is produced, and the metal track stack (8, 9, 10) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

Abstract: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.

Abstract: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).

Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.

Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

Abstract: A bump-less chip package is provided. The bump-less chip package includes a chip, an interconnection structure and a panel-shaped component. The panel-shaped component has a plurality of electrical terminals on a first surface thereof. The back surface of the chip is disposed on the first surface of the panel-shaped component, and the chip has a plurality of first pads on the active surface thereof away from the panel-shaped component. The interconnection structure is disposed on the first surface of the panel-shaped component and the active surface of the chip. The first pads of the chip may electrically connect with the electrical terminals of the panel-shaped component through the interconnection structure. Furthermore, the interconnection structure has a plurality of second pads on the surface away from the chip.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: An electronic device or signal processing device consists of a rectifier and capacitor which share common elements facilitating the construction and application of the device to various types of substrates and, particularly, flexible substrates. Components of the device may be fabricated from organic conductors and semiconductors.

Abstract: To satisfy the different requirement of TFTs function as peripheral driving circuit and pixel switching device, the modified TFT structure with various thicknesses of gate insulating layers is disclosed. For the peripheral driving circuit, the thinner thickness of the gate-insulating layer is formed, the higher driving ability the TFT performs. However, for the pixel switching device, the thicker thickness of the gate insulating layer is formed, the better reliability the TFT has. The present invention provides a first TFT (peripheral driving circuit) comprising a first gate insulating layer and a second TFT (pixel switching device) comprising a first and second gate insulating layer. Thus, the gate insulating layer of the peripheral driving circuit has a thickness less then that of the pixel switching device.

Abstract: In one embodiment, an electrically conductive trench in an integrated circuit allows for the formation of capacitors between the trench and other portions of the integrated circuit. For example, a capacitor may be formed between the trench and an electrically conductive line. Among other advantages, the capacitor provides a relatively large capacitance while occupying a relatively small area.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first to fourth inner electrodes are alternately arranged, and first to fourth terminal electrodes formed on side faces of the multilayer body. The multilayer capacitor has a first capacitor portion including first and second inner electrodes, and a second capacitor portion including third and fourth inner electrodes and exhibiting a capacitance different from that of the first capacitor portion. The first inner electrodes are electrically connected to respective ones of the plurality of first terminal electrodes through lead conductors, whereas the second inner electrodes are electrically connected to respective ones of the plurality of second terminal electrodes through lead conductors. The third and fourth inner electrodes are electrically connected to the third and fourth terminal electrodes through lead conductors, respectively.

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract: In a chip type solid electrolytic capacitor including a capacitor element and a packaging resin covering the capacitor element, the packaging resin has a mount surface and a side surface adjacent to the mount surface. A terminal is electrically connected to the capacitor element and coupled to the packaging resin. The terminal extends along the mount surface and the side surface to have an outer surface exposed from the packaging resin and to have an inner surface opposite to the outer terminal surface. The inner surface has a stepwise shape formed by forging.

Abstract: A semiconductor device having an isolation region formed in a semiconductor substrate and a capacitance device formed above that isolation region. The capacitance device has a first capacitor conductive layer disposed above the isolation region and a second capacitor conductive layer in the shape of a side wall formed along one side surface of the first capacitor conductive layer. The second capacitor conductive layer is disposed facing the first capacitor conductive layer, with a first capacitor insulating layer interposed.

Abstract: A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first dielectric layer and the second dielectric layer. The two-layer conductive structure is an equal potential structure and includes a conductive coupling between the two layers.

Abstract: A capacitor element configured to mount a semiconductor element thereon includes a base. A capacitor part is provided on the base. The base is made of a resin whose coefficient of linear expansion is adjusted in accordance with a coefficient of linear expansion of the semiconductor element mounted on the capacitor element.

Abstract: A semiconductor device includes: a semiconductor substrate including a first semiconductor layer, an insulation layer and a second semiconductor layer, which are laminated in this order; a trench penetrating both of the second semiconductor layer and the insulation layer and reaching the first semiconductor layer; and a third semiconductor layer. The trench has a ring shape on a principal surface of the substrate so that a part of the second semiconductor layer and a part of the insulation layer are surrounded with the trench. The third semiconductor layer is disposed in the trench through a first insulation film disposed on a sidewall of the trench so that the third semiconductor layer contacts the first semiconductor layer at a bottom of the trench.

Abstract: An electronic package including a conductive trace layer having a first side and a second side. The conductive trace layer is patterned to define a plurality of interconnect pads. A flexible dielectric substrate is mounted on the first side of the conductive trace layer. A flexible capacitor including a first conductive layer, a second conductive layer and a layer of dielectric material disposed between the first and the second conductive layers is mounted with the first conductive layer adjacent to the second side of the conductive trace layer. A plurality of interconnect regions extend through the first conductive layer and the dielectric material layer of the capacitor. An interconnect member is connected between each one of the conductive layers of the capacitor and a corresponding set of the interconnect pads.

Abstract: There is here disclosed a semiconductor device comprising a capacitor provided on a substrate and formed by sandwiching a capacitive insulating film between lower and upper electrodes, an interlayer insulating film of an n-th layer (n is 1 or greater integer) provided on the substrate to cover the capacitor, and a plurality of plugs and a plurality of wirings provided on the substrate, wherein an electrode wiring among the wirings which is electrically connected to the lower or upper electrode above the capacitor is provided in an interlayer insulating film of an (n+1)-th layer or more formed on the interlayer insulating film of the n-th layer.

Abstract: A user-selectable integrated circuit capacitance apparatus may include first and second electrodes defining a first fractal geometry, along with second and third electrodes defining a second fractal geometry. A dielectric may be located adjacent to the first and third electrodes. A method of fabricating the apparatus may include selecting a dielectric layer, forming the first and second electrodes so as to define the first fractal geometry on the dielectric layer, and then forming third and fourth electrodes so as to define a second fractal geometry on the dielectric layer. A circuit package may include external package connections connected to the electrodes of the apparatus. A system may include the apparatus coupled to a wireless transceiver by way of a power supply trace.

Abstract: A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.

Abstract: A capacitor formed in a substrate including a recess dug into a substrate; a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; a second layer of a conductive material covering the first layer; a third layer of a conductive or insulating material filling the recess; trenches crossing the third layer; a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges thereof; a fifth layer of a dielectric material covering the fourth layer; and a sixth layer of a conductive material covering the fifth layer.

Abstract: A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

Abstract: A device includes a transistor, and two interdigital capacitors. The transistor is located on an imaginary extension line aligned with a common electrode of the two interdigital capacitors.

Abstract: A semiconductor device for charge-up damage evaluation and an evaluation method for the same are provided which permit to detect charge-up damage caused by static electricity. There are provided a silicon substrate 9, a first insulation film 10 formed on the silicon substrate 9, a first conductive layer 6 formed on the first insulation film 10 and connected to the silicon substrate 9, a second insulation film 11 formed on the first conductive layer 6, a second conductive layer 8 formed on the second insulation film 11 and serving as an antenna, and a third insulation film 12 formed on the second conductive layer 8.

Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.

Abstract: A metal-to-metal capacitor in a semiconductor integrated circuit is converted to a conductive structure by connecting the first metal plate of the capacitor to ground and the second metal plate of the capacitor to a programming voltage, thus causing the insulator material to breakdown and conduct current from the first plate to the second plate.

Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Abstract: There is provided a semiconductor device which is manufactured via steps of forming a capacitor which is obtained by forming in sequence an upper electrode, a dielectric film formed of ferroelectric material or high-dielectric material, and a lower electrode on a semiconductor substrate, then forming an interlayer insulating film on the capacitor, then planarizing a surface of the interlayer insulating film by the CMP polishing, then removing a moisture attached to a surface of the interlayer insulating film or a moisture contained in the interlayer insulating film by applying the plasma annealing using an N2O gas, and then forming a redeposited interlayer film on the interlayer insulating film.

Abstract: A structure and method of fabrication of a capacitor and other devices by providing a semiconductor structure and providing a top insulating layer and conductive features over the semiconductor structure; forming a first conductive layer over the top insulating layer; patterning the first conductive layer to form at least a capacitor bottom plate and a first portion of the first conductive layer; forming a capacitor dielectric layer over the top insulating layer and the capacitor bottom plate and the first portion of the first conductive layer; forming a second conductive layer over the capacitor dielectric layer; and patterning the second conductive layer to form at least a top plate over the bottom plate and a first section of the second conductive layer on the capacitor dielectric layer. The embodiment can further comprise conductive features in the top insulating layer that can underlie the bottom plate, the first portion or/and the first section.

Abstract: A semiconductor device having an isolation region formed in a semiconductor substrate and a capacitance device formed above that isolation region. The capacitance device has a first capacitor conductive layer disposed above the isolation region and a second capacitor conductive layer in the shape of a side wall formed along one side surface of the first capacitor conductive layer. The second capacitor conductive layer is disposed facing the first capacitor conductive layer, with a first capacitor insulating layer interposed.